INTEGRATED CIRCUITS HSTL16918 9-bit to 18-bit HSTL-to-LVTTL memory address latch Product data 2001 Jun 16 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch FEATURES HSTL16918 PIN CONFIGURATION • Inputs meet JEDEC HSTL Std. JESD 8–6, and outputs meet Level III specifications • ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. • Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA. • Packaged in 48-pin plastic thin shrink small outline package (TSSOP48) DESCRIPTION The HSTL16918 is a 9-bit to 18-bit D-type latch designed for 3.15 to 3.45 V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels. 2Q1 1 48 VCC 1Q1 2 47 VCC GND 3 46 1Q2 D1 4 45 2Q2 D2 5 44 GND VCC 6 43 1Q3 D3 7 42 2Q3 D4 8 41 VCC GND 9 40 1Q4 1LE 10 The HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE) input. Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is LOW the Q outputs of the corresponding nine latches follow the D inputs. When LE is taken HIGH, the Q outputs are latched at the levels set up at the D inputs. The HSTL16918 is characterized for operation from 0 to +70 °C. 39 2Q4 GND 11 38 GND VREF 12 37 1Q5 GND 13 36 2Q5 2LE 14 35 GND GND 15 34 1Q6 D5 16 33 2Q6 D6 17 32 VCC D7 18 31 1Q7 VCC 19 30 2Q7 D8 20 29 GND D9 21 28 1Q8 GND 22 27 2Q8 2Q9 23 26 VCC 1Q9 24 25 VCC SW00768 ORDERING INFORMATION PACKAGES 48-pin plastic thin shrink small outline package (TSSOP48) 2001 Jun 16 TEMPERATURE RANGE ORDER CODE DWG NUMBER 0 to +70 °C HSTL16918DGG SOT362-1 2 853-2258 26484 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch PIN DESCRIPTION HSTL16918 LOGIC DIAGRAM (positive logic) PIN SYMBOL 4, 5, 7, 8, 16, 17, 18, 20, 21 D[1–9] 2, 46, 43, 40, 37, 34, 31, 28, 24 1Q[1–9] 1, 45, 42, 39, 36, 33, 30, 27, 23 2Q[1–9] 10 1LE FUNCTION VREF 12 Inputs 1LE D1 10 4 1D Outputs 2 1Q1 C1 2LE Latch enable 14 2LE 12 VREF Reference voltage 6, 19, 25, 26, 32, 41, 47, 48 VCC Supply voltage 3, 9, 11, 13, 15, 22, 29, 35, 38, 44 GND Ground 14 1D 1 2Q1 C1 TO EIGHT OTHER CHANNELS SW00769 FUNCTION TABLE INPUTS OUTPUT LE D Q L H H L L L H X Q0 1 NOTE: 1. Output level before the indicated steady-state input conditions were established. 2001 Jun 16 3 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 ABSOLUTE MAXIMUM RATINGS1 Over operating free-air temperature range (unless otherwise noted). PARAMETER SYMBOL VCC VI CONDITIONS RATING UNIT –0.5 to +4.6 V –0.5 to VCC +0.5 V Supply voltage range Input voltage range 2 2 VO Output voltage range IIK Input clamp current IOK Output clamp current 3 IO Continuous output current –0.5 to VCC +0.5 V VI < 0 –50 mA VO < 0 or VO > VCC ±50 mA VO = 0 to VCC ±50 mA Continuous current through each VCC or GND θJA Package thermal impedance 4 Tstg Storage temperature range ±100 mA 89 °C/W –65 to +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This current flows only when the output is in the high state and VO > VCC. 4. The package thermal impedance is calculated in accordance with JESD 51. RECOMMENDED OPERATING CONDITIONS1 LIMITS SYMBOL PARAMETER Min VCC Supply voltage 3.15 VREF Reference voltage 0.68 VI Input voltage VIH AC high-level input voltage All inputs 0 VIL AC low-level input voltage All inputs VIH DC high-level input voltage All inputs All inputs VIL DC low-level input voltage IOH High-level output current IOL Low-level output current Tamb Operating free-air temperature range UNIT 3.45 V 0.9 V 1.5 V V VREF – 200 mV VREF + 100 mV 0 4 0.75 Max VREF + 200 mV NOTE: 1. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. 2001 Jun 16 Nom V V VREF – 100 mV V –24 mA 24 mA +70 °C Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise noted). LIMITS SYMBOL PARAMETER TEST CONDITIONS Typ 1 Min Max VIK VCC = 3.15 V; II = –18 mA VOH VCC = 3.15 V; IOH = –24 mA VOL VCC = 3.15 V; IOL = 24 mA 0.5 V Control inputs VCC = 3.45 V; VI = 0 or 1.5 V ±5 µA Data inputs VCC = 3.45 V; VI = 0 or 1.5 V ±5 µA VCC = 3.45 V; VREF = 0.68 V or 0.9 V 90 µA 100 mA II VREF ICC CI CO –1.2 UNIT 2.4 V V VCC = 3.45 V; VI = 0 or 1.5 V 50 Control inputs VCC = 0 or 3.3 V; VI = 0 or 3.3 V 2 pF Data inputs VCC = 0 or 3.3 V; VI = 0 or 3.3 V 2.5 pF VCC = 0 V; VO = 0 V 4 pF Outputs NOTE: 1. All typical values are at VCC = 3.3 V; Tamb = 25 °C. TIMING REQUIREMENTS Over recommended operating free-air temperature range (unless otherwise noted). SYMBOL PARAMETER tw Pulse duration tsu th tldr VCC = 3.3 V ±0.15 V TEST CONDITIONS Min Max UNIT LE LOW (Figure 1) 3 ns Setup time D before LE ↑ (Figure 2) 2 ns Hold time D after LE ↑ (Figure 2) 1 ns Data race condition timeĂ1 D after LE ↓ 0 ns NOTE: 1. This is the maximum time after LE switches LOW that the data input can return to the latched state from the opposite state without producing a glitch on the output. SWITCHING CHARACTERISTICS Over recommended operating free-air temperature range; VREF = 0.75 V. SYMBOL tpd PARAMETER FROM (INPUT) TO (OUTPUT) D VCC = 3.3 V ±0.15 V UNIT Min Max Q 1.9 3.4 ns LE Q 1.9 4.2 ns FROM (INPUT) TO (OUTPUT) D LE Propagation delay (Figure 3) SIMULTANEOUS SWITCHING CHARACTERISTICS Over recommended operating free-air temperature range; VREF = 0.75 V SYMBOL tpd 2001 Jun 16 PARAMETER Propagation g delay; y all outputs switching g (Figure 3) 5 VCC = 3.3 V ±0.15 V UNIT Min Max Q 1.9 4.4 ns Q 1.9 5.2 ns Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch VOLTAGE WAVEFORMS LOAD CIRCUIT tw FROM OUTPUT UNDER TEST 1.25 V VREF INPUT HSTL16918 CL = 80 PF (see Note) VREF 500 Ω 0.25 V SW00770 SW00773 Figure 1. Pulse duration NOTE: CL includes probe and jig capacitance. Figure 4. Load circuit 1.25 V LE VREF 0.25 V tsu th 1.25 V VREF DATA INPUT VREF 0.25 V SW00771 Figure 2. Setup and Hold times 1.25 V INPUT (Note 1) VREF VREF 0.25 V tPLH tPHL VOH OUTPUT 1.5 V 1.5 V VOL SW00772 Figure 3. Propagation delay times NOTES: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns. 2. The outputs are measured one at a time with one transition per measurement. 3. tPHL and tPLH are the same as tpd. 2001 Jun 16 6 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2001 Jun 16 7 HSTL16918 SOT362-1 Philips Semiconductors Product data 9-bit to 18-bit HSTL-to-LVTTL memory address latch HSTL16918 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 06-01 Document order number: 2001 Jun 16 8 9397 750 08474