TI DS50PCI402SQ Ds50pci402 2.5 gbps / 5.0 gbps 4 lane pci express repeater with equalization and de-emphasis Datasheet

DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
DS50PCI402 2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with
Equalization and De-Emphasis
Check for Samples: DS50PCI402
FEATURES
DESCRIPTION
•
The DS50PCI402 is a low power, 4 lane bidirectional
buffer/equalizer designed specifically for PCI Express
Gen1 and Gen2 applications. The device performs
both receive equalization and transmit de-emphasis,
allowing maximum flexibility of physical placement
within a system. The receiver is capable of opening
an input eye that is completely closed due to intersymbol interference (ISI) induced by the interconnect
medium.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input and Output signal conditioning
increases PCIe reach in backplanes and
cables
0.09 UI of residual deterministic jitter at 5Gbps
after 42” of FR4 (with Input EQ)
0.11 UI of residual deterministic jitter at 5Gbps
after 7m of PCIe Cable (with Input EQ)
0.09 UI of residual deterministic jitter at 5Gbps
with 28” of FR4 (with Output DE)
0.13 UI of residual deterministic jitter at 5Gbps
with 7m of PCIe Cable (with Output DE)
Adjustable Transmit VOD 800 to 1200mVp-p
Automatic and manual Receiver Detection and
input termination control circuitry
Automatic power management on an
individual lane basis via SMBus
Adjustable electrical idle detect threshold.
Data rate optimized 3-stage equalization to 27
dB gain
Data rate optimized 6-level 0 to 12 dB transmit
de-emphasis
Flow-thru pinout in 10mmx5.5mm 54-pin
leadless WQFN package
Single supply operation at 2.5V
>6kV HBM ESD rating
-10 to 85°C operating temperature range
The transmitter de-emphasis level can be set by the
user depending on the distance from the
DS50PCI402 to the PCI Express endpoint. The
DS50PCI402 contains PCI Express specific functions
such as Transmit Idle, RX Detection, and Beacon
signal pass through.
The device provides automatic receive detection
circuitry which controls the input termination
impedance. By automatically reflecting the current
load impedance seen on the outputs back to the
corresponding inputs the DS50PCI402 becomes
completely transparent to both the PCIe root complex
and endpoint. An internal rate detection circuit is
included to detect if an incoming data stream is at
Gen2 data rates, and adjusts the de-emphasis on it's
output accordingly. The signal conditioning provided
by the device allows systems to upgrade from Gen1
data rates to Gen2 without reducing their physical
reach. This is true for FR4 applications such as
backplanes, as well as cable interconnect.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Typical Application
PCI402
Slice 1 of 4
PCI Express Interconnect
Cable or Backplane
PCI Express
Root
Complex or
Bridge
PCI402
Slice 1 of 4
PCI Express
Endpoint
Block Diagram - Detail View Of Channel (1 of 8)
VOD/ DeEMPHASIS
CONTROL
VDD
Auto / Manual
RXDETECT
Ix_n+
RATE
DET
EQ
DEMA/B
SMBus
LIMITER
Ix_n-
EQA/B
SMBus
2
OUTBUF
Ox_n+
Ox_n-
IDLE
DET
TX Idle Enable
TXIDLEx
SMBus
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
DEMA1/SCL
DEMA0/SDA
ENSMB
EQB1/AD2
EQB0/AD3
49
48
47
46
VDD
50
PRSNT
51
DEMB0/AD1
53
52
DEMB1/AD0
54
Pin Diagram
SMBUS AND CONTROL
OB_0+
1
45
IB_0+
OB_0-
2
44
IB_0-
OB_1+
3
43
IB_1+
OB_1-
4
42
IB_1-
OB_2+
5
41
VDD
OB_2-
6
40
IB_2+
OB_3+
7
39
IB_2-
OB_3-
8
38
IB_3+
37
IB_3-
DAP = GND
VDD
9
IA_0+
10
36
VDD
IA_0-
11
35
OA_0+
IA_1+
12
34
OA_0-
IA_1-
13
33
OA_1+
VDD
14
32
OA_1-
IA_2+
15
31
OA_2+
IA_2-
16
30
OA_2-
21
22
23
24
25
26
27
RATE
RXDETA
RXDETB
TXIDLEA
TXIDLEB
ENRXDET
SD_TH
OA_3-
20
OA_3+
28
19
29
18
EQA1
17
IA_3-
EQA0
IA_3+
The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 8) vias to ensure optimal electrical and thermal performance.
DS50PCI402 Pin Diagram 54 lead
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
3
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Table 1. Pin Descriptions
Pin Name
Pin Number
I/O,
Type (1) (2) (3) (4)
Pin Description
Differential High Speed I/O's
IA_0+, IA_0- ,
IA_1+, IA_1-,
IA_2+, IA_2-,
IA_3+, IA_3-
10,
12,
15,
17,
11
13
16
18
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A
gated on-chip 50Ω termination resistor connects INA_0+ to VDD and
INA_0- to VDD when enabled.
OA_0+, OA_0-,
OA_1+, OA_1-,
OA_2+, OA_2-,
OA_3+, OA_3-
35,
33,
31,
29,
34
32
30
28
O,LPDS
Inverting and non-inverting low power differential signal (LPDS) 50Ω
driver outputs with de-emphasis. Compatible with AC coupled CML
inputs.
IB_0+, IB_0- ,
IB_1+, IB_1-,
IB_2+, IB_2-,
IB_3+, IB_3-
45,
43,
40,
38,
44
42
39
37
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A
gated on-chip 50Ω termination resistor connects INB_0+ to VDD and
INB_0- to VDD when enabled.
OB_0+, OB_0-,
OB_1+, OB_1-,
OB_2+, OB_2-,
OB_3+, OB_3-
1, 2
3, 4
5, 6
7, 8
O,LPDS
Inverting and non-inverting low power differential signal (LPDS) 50Ω
driver outputs with de-emphasis. Compatible with AC coupled CML
inputs.
I, LVCMOS
w/internal
pulldown
System Management Bus (SMBus) enable pin.
When pulled high provide access internal digital registers that are a
means of auxiliary control for such functions as equalization, deemphasis, VOD, rate, and idle detection threshold.
When pulled low, access to the SMBus registers are disabled and
SMBus function pins are used to control the Equalizer and De-Emphasis.
Please refer to SYSTEM MANAGEMENT BUS (SMBUS) AND
CONFIGURATION REGISTERS and Electrical Characteristics — Serial
Management Bus Interface for detail information.
Control Pins — Shared (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SCL
50
I, LVCMOS
ENSMB = 1
SMBUS clock input pin is enabled. External pull-up resistor maybe
needed. Refer to RTERM in the SMBus specification.
SDA
49
I, LVCMOS,
O, Open Drain
ENSMB = 1
The SMBus bi-directional SDA pin is enabled. Data input or open drain
output. External pull-up resistor is required.
Refer to RTERM in the SMBus specification.
AD0-AD3
54, 53, 47, 46
I, LVCMOS
w/internal
pulldown
ENSMB = 1
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs. See section — SYSTEM
MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS
for additional information.
ENSMB = 0 (NORMAL PIN MODE)
EQA0, EQA1
EQB0, EQB1
20, 19
46, 47
I,FLOAT,
LVCMOS
EQA/B ,0/1 controls the level of equalization of the A/B sides as shown in
Table 2. The EQA/B pins are active only when ENSMB is de-asserted
(Low). Each of the 4 A/B channels have the same level unless controlled
by the SMBus control registers. When ENSMB goes high the SMBus
registers provide independent control of each lane, and the EQB0/B1
pins are converted to SMBUS AD2/AD3 inputs.
DEMA0, DEMA1
DEMB0, DEMB1
49, 50
53, 54
I,FLOAT,
LVCMOS
DEMA/B ,0/1 controls the level of de-emphasis of the A/B sides as
shown in Table 5. The DEMA/B pins are only active when ENSMB is deasserted (Low). Each of the 4 A/B channels have the same level unless
controlled by the SMBus control registers. When ENSMB goes High the
SMBus registers provide independent control of each lane and the DEM
pins are converted to SMBUS AD0/AD1 and SCL/SDA inputs.
(1)
(2)
(3)
(4)
4
FLOAT = 3rd input state, don't drive pin. Pin is internally biased to mid level with 50 kΩ pull-up/pull-down. If high Z output not available,
drive input to VDD/2 to assert mid level state.
Internal pulldown = Internal 30 kΩ pull-down resistor to GND is present on the input.
LVCMOS inputs without the “Float” conditions must be driven to a logic Low or High at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Table 1. Pin Descriptions (continued)
Pin Name
Pin Number
I/O,
Type (1) (2) (3) (4)
Pin Description
RATE
21
I,FLOAT,
LVCMOS
RATE control pin controls the pulse width of de-emphasis of the output.
A Low forces Gen1 (2.5Gbps), High forces Gen 2 (5Gbps),
Open/Floating the rate is internally detected after each exit from idle and
the pulse width is set appropriately. When ENSMBUS= 1 this pin is
disabled and the RATE function is controlled internally by the SMBUS
registers. Refer to Table 5.
Control Pins — Both Modes (LVCMOS)
RXDETA,RXDETB
22,23
I, LVCMOS
w/internal
pulldown
The RXDET pins in combination with the ENRXDET pin controls the
receiver detect function. Depending on the input level, a 50Ω or >50KΩ
termination to the power rail is enabled. Refer to Table 7.
PRSNT
52
I, LVCMOS
Cable Present Detect input. High when a cable is not present per PCIe
Cabling Spec. 1.0. Puts part into low power mode. When low (normal
operation) part is enabled.
ENRXDET
26
I, LVCMOS
w/internal
pulldown
Enables pin control of receiver detect function. The default is automatic
RXDET using the internal pulldown. Pin must be pulled high for manual
RXDETA/B operation. Controls individual A and B sides. Refer to
Table 7.
TXIDLEA,TXIDLEB
24,25
I, FLOAT,
LVCMOS
Controls the electrical idle function on corresponding outputs when
enabled. H= electrical Idle, Float=autodetect (Idle on input passed to
output), L=Idle squelch disabled as shown in Table 6.
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for
default 130mV DIFF p-p, otherwise connect resistor from SD_TH to GND
to set threshold voltage as shown in Table 7.
VDD
9, 14,36, 41, 51
Power
Power supply pins CML/analog.
GND
DAP
Power
Ground pad (DAP - die attach pad).
Analog
SD_TH
Power
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
5
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
FUNCTIONAL DESCRIPTION
The DS50PCI402 is a low power media compensation 4 lane repeater optimized for PCI Express Gen 1 and Gen
2 media including lossy FR-4 printed circuit board backplanes and balanced cables. The DS50PCI402 operates
in two modes: Pin Control Mode (ENSMB = 0) and SMBus Mode (ENSMB = 1).
Pin Control Mode:
When in pin mode (ENSMB = 0) , the repeater is configurable with external pins. Equalization and de-emphasis
can be selected via pin for each side independently. When de-emphasis is asserted VOD is automatically
increased per the De-Emphasis table below for improved performance over lossy media. The receiver detect
pins RXDETA/B provide manual control for input termination (50Ω or >50KΩ). Rate optimization is also pin
controllable, with pin selections for 2.5Gbps, 5Gbps, and auto detect. The receiver electrical idle detect threshold
is also programmable via an optional external resistor on the SD_TH pin.
SMBUS Mode:
When in SMBus mode the equalization, de-emphasis, and termination disable features are all programmable on
a individual lane basis, instead of grouped by sides as in the pin mode case. Upon assertion of ENSMB the
RATE, EQx and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to
AD0-AD3 SMBus address inputs. The other external control pins remain active unless their respective registers
are written to and the appropriate override bit is set, in which case they are ignored until ENSMB is driven low.
On powerup and when ENSMB is driven low all registers are reset to their default state. If PRSNT is asserted
while ENSMB is high, the registers retain their current state.
Equalization settings accessible via the pin controls were chosen to meet the needs of most PCIe applications. If
additional fine tuning or adjustment is needed, additional equalization settings can be accessed via the SMBus
registers. Each input has a total of 24 possible equalization settings. The tables show a typical gain for each gain
stage (GST[1:0]) and boost level (BST[2:0]) combination. When using SMBus mode, the Equalization and DeEmphasis levels are set using registers.
Table 2. Equalization Settings with GST=1 for Pins or SMBus Registers
EQ1 ( EQ0 (
EQ Setting
EQ Gain (dB)
2.5 GHz
Suggested Use
0
0
Bypass - Default Setting
1.6
3.2
1)
1)
GST[1
:0]
BST[2:
0]
F
F
00
000
01
000
01
001
2.1
4.2
01
010
2.6
5.0
01
011
3.2
5.9
01
100
4.0
7.3
01
101
4.9
7.9
01
110
5.4
8.5
01
111
5.6
9.0
1
(1)
1
1.25 GHz
8" FR4 (6-mil trace) or < 1m (28 AWG) PCIe cable
F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low
Table 3. Equalization Settings with GST=2 for Pins or SMBus Registers
EQ1 ( EQ0 (
GST[1
:0]
BST[2:
0]
1.25 GHz
2.5 GHz
Suggested Use
0
0
10
000
3.8
7.6
14" FR4 (6-mil trace) or 1m (28 AWG) PCIe cable
10
001
5.1
9.9
10
010
6.4
11.6
10
011
7.6
13.5
10
100
9.5
16.1
10
101
11.3
17.5
F
6
EQ Gain (dB)
1)
F
(1)
EQ Setting
1)
0
1
20" FR4 (6-mil trace) or 5m (26 AWG) PCIe cable
40" FR4 (6-mil trace) or 9m (24 AWG) PCIe cable
F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Table 3. Equalization Settings with GST=2 for Pins or SMBus Registers (continued)
EQ1 ( EQ0 (
1)
1)
0
1
EQ Setting
EQ Gain (dB)
GST[1
:0]
BST[2:
0]
1.25 GHz
2.5 GHz
10
110
12.3
18.6
10
111
12.8
19.8
Suggested Use
50" FR4 (6-mil trace) or 10m (24 AWG) PCIe cable
Table 4. Equalization Settings with GST=3 for Pins or SMBus Registers
EQ1 ( EQ0 (
1)
1)
1
(1)
0
0
F
1
F
EQ Setting
EQ Gain (dB)
GST[1
:0]
BST[2:
0]
1.25 GHz
2.5 GHz
11
000
6.4
12.2
11
001
8.5
15.6
11
010
10.4
18.3
11
011
12.4
21.3
11
100
15.2
25.0
11
101
18.1
27.2
11
110
19.6
28.8
11
111
20.2
30.7
Suggested Use
30" FR4 (6-mil trace) or 7m (24 AWG) PCIe cable
15m (24 AWG) PCIe cable
> 15m (24 AWG) PCIe cable
F=Float (don't drive pin, each float pin has an internal 50K Ohm resistor to VDD and GND), 1=High, 0=Low
The De-Emphasis level must be set when in SMBus mode. See SMBus TRANSACTIONS section and
Table 10 for specific De-Emphasis values.
Table 5. De-Emphasis Input Select Pins for A and B ports (3–Level Input)
RATE
(1)
DEM1 DEM0 (1
Typical DE Pulse
Width
Typical VOD
0dB
0ps
1000mV
-3.5dB
400ps
1000mV
-6dB
400ps
1000mV
-6dB
400ps enhanced
1000mV
F
-9dB
400ps enhanced
1000mV
1
F
-12dB
400ps enhanced
1000mV
0/F
F
0
-9dB
400ps enhanced
1200mV
30 inches FR4 (6-mil trace)
0/F
F
1
-12dB
400ps enhanced
1400mV
40 inches FR4 (6-mil trace)
0/F
F
F
Reserved, don't
use
1/F
0
0
0dB
0ps
1000mV
1/F
0
1
-3.5dB
200ps
1000mV
1/F
1
0
-6dB
200ps
1000mV
1/F
1
1
-6dB
200ps enhanced
1000mV
1/F
0
F
-9dB
200ps enhanced
1000mV
1/F
1
F
-12dB
200ps enhanced
1000mV
1/F
F
0
-9dB
200ps enhanced
1200mV
20 inches FR4 (6-mil trace)
1/F
F
1
-12dB
200ps enhanced
1400mV
30 inches FR4 (6-mil trace)
1/F
F
F
Reserved, don't
use
(1)
)
0/F
0
0
0/F
0
1
0/F
1
0
0/F
1
1
0/F
0
0/F
Typical DeEmphasis Level
Suggested Use
8 inches FR4 (6-mil trace) or less than 1
meter (28 AWG) PCIe cable
15 inches FR4 (6-mil trace)
10 inches FR4 (6-mil trace)
F=Float (don't drive pin - (each float pin has an internal 50K Ohm resistor to VDD and GND). Enhanced DE Pulse width provides
additional de-emphasis on second bit. VOD = Voltage Output Differential amplitude. When RATE is floated (F=Auto Rate Detection
Active) DE Level and Pulse Width settings follow detected RATE. RATE=0 is 2.5GBps, RATE=1 is 5 GBps
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
7
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Table 6. Idle Control (3–Level Input)
TXIDLEA/B
Function
0
This state is for lossy media, dedicated Idle threshold detect circuit disabled,
output follows input based on EQ settings. Idle state not ensured.
Float
Float enables automatic idle detection. Idle on the input is passed to the
output. This is the recommended default state. Output driven to Idle if diff input
signal less than value set by SD_TH pin.
1
Manual override, output forced to Idle. Diff inputs are ignored.
Table 7. Receiver Electrical Idle Detect Threshold Adjust (Analog input - Connect Resistor to GND or
Float)
Typical Receiver Electrical Idle Detect Threshold (DIFF p-p)
Float (no resistor required)
130mV (default condition)
0
225mV
80K
20mV
SD_TH resistor value can be set from 0 through 80K Ohms to achieve desired idle detect threshold, see Figure 1. 8K Ohm is approx
130mV.
ELECTRICAL IDLE DETECT THRESHOLD
(DIFF mVp-p)
(1)
SD_TH resistor value (Ω) (connect from pin to GND) (1)
250
VDD = 2.5V
TA = 25°C
200
150
100
50
0
0
10k 20k 30k 40k 50k 60k 70k 80k
SD_TH RESISTOR VALUE (:)
Figure 1. Typical Idle threshold vs SD_TH resistor value
Receiver Detection
The Rx detection process is a feature that can set the number of active channels on the DS50PCI402. By
sensing the presence of a valid PCIe load on the output, the channel can be automatically enabled for operation.
This allows the DS50PCI402 to configure inself to the proper lane width, whether it is a 4-lane, 2-lane, or 1-lane
PCIe link.
Automatic Rx Detection is enabled by a combination of PRSNT# and ENRXDET inputs. When these inputs are
set low, Automatic Rx Detection is enabled, cycling of the PRSNT# pin will reset the Rx detection circuitry,
initiating a new receiver detection sequence. Pulling the ENRXDET input to logic 1, allows for manual control of
the input termination.
The table below summarizes control pin and receiver detect operation for the DS50PCI402.
8
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Table 8. Receiver Detect Pins for A and B ports (LVCMOS inputs)
PRSNT#
ENRXDET
RXDETA/B
Input
Termination
Termination sensed on
Output
0
0
0
>50KΩ to VDD
Hi - Z
50Ω
PCIe Input
0
0
1
>50KΩ to VDD
Hi - Z
50Ω
PCIe Input
Function
Automatic RXDET: Rx detection state machine
enabled. Outputs will test for the presence of a
receiver input every 12 msec until detection
occurs. Input termination remains >50KΩ to
VDD until receiver is detected. Once receiver is
detected, input impedance to VDD is 50Ω.
Automatic RXDET: Rx detection state machine
enabled. Outputs will test for the presence of a
receiver input every 12 msec for 600 msec and
then stop. Input termination remains >50KΩ to
VDD until receiver is detected. Once receiver is
detected, input impedance to VDD is 50Ω.
Restart detection if RXDETA/B is pulsed lowhigh.
0
1
0
>50KΩ to VDD
X
Manual RXDET: Rx detection state machine
disabled. Input termination >50KΩ. Associated
output channels in low power idle mode.
0
1
1
50Ω
X
Manual RXDET: Rx detection state machine
disabled. Input termination 50Ω. Associated
output channels set to active.
1
X
X
>50KΩ to VDD
X
Power down mode: Input termination >50KΩ.
Associated output channels off. Part in power
saving mode. PRSNT# should be held high for
a minimum of 5 us to ensure complete analog
power down. The Automatic RXDET
functionality will be re-initialized on the falling
edge of PRSNT#.
RX Detect: Range of Operation
The Rx detection process used in the DS50PCI402 is designed to be fully compliant with the PCIe 2.0 base
specification. The receiver detection circuitry will accurately detect a receiver when both conditions listed below
are true:
• DS50PCI402 within Recommended Operating Range for Temperature and Supply Voltage
• For receiver ZRX-DC = 40 (min) to 60 (max) Ohms
Note: To ensure robust system operation, the DS50PCI402 will only signal a valid receiver detection if both
halves of the differential output pair detect a proper 40 - 60 Ohm receiver impedance. If the receiver detection
circuitry senses a load impedance greater than ZRX-DC on either trace of a differential pair, it will be interpreted as
no termination load present (i.e. the corresponding DS50PCI402 input termination will remain High-Z).
Manual Control Of RXDETA/B In A PCIe Environment
In some cases manual control of RXDETA/B may be desirable. In order for upstream and downstream PCIe
subsystems to communicate in a cabling environment, the PCIe specification includes several auxiliary or
sideband signals to manage system-level functionality or implementation. Similar methods are used in backplane
applications, but the exact implementation falls outside the PCIe standard. Initial communication from the
downstream subsystem to the upstream subsystem is done with the CPRSNT# auxiliary signal. The CPRSNT#
signal is asserted Low by the downstream componentry after the "Power Good" condition has been established.
This mechanism allows for the upstream subsystem to determine whether the power is good within the
downstream subsystem, enable the reference clock, and initiate the Link Training Sequence.
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
9
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
CPWRON
0V
CPRSNT# to RESET Removal
5 ms (min)
CPERST#
0V
DS50PCI402 PRSNT#
Min pulse width HIGH
5 Ps (min)
RESET Removed and
REFCLK Stable
CPRSNT#
0V
CREFCLK
Figure 2. Typical PCIe System Timing
The signals shown in the graphic could be easily replicated within the downstream subsystem and used to
externally control the common mode input termination impedance on the DS50PCI402. Often an onboard
microcontroller will be used to handle events like power-up, power-down, power saving modes, and hot insertion.
The microcontroller would use the same information to determine when to enable and disable the DS50PCI402
input termination. In applications that require SMBus control, the microcontroller could also delay any response
to the upstream subsystem to allow sufficient time to correctly program the DS50PCI402 and other devices on
the board.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Absolute Maximum Ratings
(1) (2)
Supply Voltage (VDD)
-0.5V to +3.0V
LVCMOS Input/Output Voltage
-0.5V to +4.0V
CML Input Voltage
-0.5V to (VDD+0.5V)
CML Input Current
-30 to +30 mA
LPDS Output Voltage
-0.5V to (VDD+0.5V)
Analog (SD_TH) (3)
-0.5V to (VDD+0.5V)
Junction Temperature
+125°C
Storage Temperature
-40°C to +125°C
Lead Temperature Range
Maximum Package Power Dissipation at 25°C
NJY Package
4.21 W
Derate NJY Package
52.6mW/°C above +25°C
ESD Rating
≥6 kV
HBM, STD - JESD22-A114C
≥250 V
MM, STD - JESD22-A115-A
≥1250 V
CDM, STD - JESD22-C101-C
Thermal Resistance
θJC
11.5°C/W
θJA, No Airflow, 4 layer JEDEC
19.1°C/W
For soldering specifications: see product folder at
www.ti.com
http://www.ti.com/lit/SNOA549
(1)
(2)
(3)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are specified for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
Measured at default SD_TH settings
Recommended Operating Conditions
Min
Typ
Max
Units
2.375
2.5
2.625
V
-10
25
+85
°C
Supply Voltage
VDD to GND
Ambient Temperature
SMBus (SDA, SCL)
Supply Noise Tolerance up to 50Mhz
(1)
(1)
3.6
V
100
mV pp
Allowed supply noise (mVP-P sine wave) under typical conditions.
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
11
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified.
(1) (2)
Symbol
POWER
Parameter
Conditions
Min
Typ
Max
Units
800
1000
mW
4
8
mW
(3)
PD
Power Dissipation
EQX=Float, DEX=0, VOD=1Vpp
,PRSNT=0
PRSNT=1, ENSMB=0
LVCMOS / LVTTL DC SPECIFICATIONS
High Level Input
Voltage
(4)
VIL
Low Level Input
Voltage
(4)
VOH
High Level Output
Voltage
SMBUS open drain VOH set by
pullup Resistor
VOL
Low Level Output
Voltage
IOL = 4mA
IIH
Input High Current
VIN = 3.6V , LVCMOS
-15
+15
VIN = 3.6V , w/
FLOAT,PULLDOWN input
-15
+120
VIN = 0V
-15
+15
VIN = 0V, w/FLOAT input
-80
+15
VIH
IIL
Input Low Current
2
3.6
0
0.8
V
V
V
0.4
V
μA
μA
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLRX-DIFF
(5)
Rx package plus Si
differential return loss
0.05GHz – 1.25GHz
1.25GHz – 2.5GHz
(5)
RLRX-CM
Common mode Rx
return loss
0.05GHz - 2.5GHz
(5)
ZRX-DC
Rx DC common mode
impedance
Tested at VDD=0
ZRX-DIFF-DC
Rx DC differential
impedance
Tested at VDD=0
VRX-DIFF-DC
Differential Rx peak to
peak voltage
Tested at DC, TXIDLEx=0
ZRX-HIGH-IMP-DC -POS
DC Input CM
impedance for V>0
Vin = 0 to 200 mV,
RXDETA/B = 0,
ENSMB = 0, VDD=2.625
Electrical Idle detect
threshold
SD_TH = float, see Table 5,
VRX-IDLE-DET-DIFF-PP
(6)
-21
dB
-20
-11.5
dB
40
50
60
Ω
85
100
115
Ω
1.2
V
0.10
50
KΩ
40
175
mVP-P
1200
mVP-P
LPDS OUTPUTS (OUT_n+, OUT_n-)
VTX-DIFF-PP
VOCM
(1)
(2)
(3)
(4)
(5)
(6)
12
Output Voltage Swing
Output Common-Mode
Voltage
Differential measurement with
OUT_n+ and OUT_n- terminated
by 50Ω to GND AC-Coupled,
Figure 4, (3)
Single-ended measurement DCCoupled with 50Ω termination, (1)
800
1000
VDD - 1.4
V
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Measured with DEM Select pins configured for 1000mV VOD, see De-emphasis table.
Input edge rate for LVCMOS/FLOAT inputs must be 50ns minimum from 10-90%.
Input Return Loss also uses the setup shown in Figure 6. The blocking / biasing circuit is replaced with a simple AC coupling capacitor
for each input to emulate a typical PCIe application.
Measured at package pins of receiver. Less than 40mV is IDLE, greater than 175mV is ACTIVE. SD_TH pin connected with resistor to
GND overrides this default setting.
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
(1) (2)
Symbol
VTX-DE-RATIO-3.5
VTX-DE-RATIO-6
Parameter
Conditions
Min
Typ
Max
Units
Tx de-emphasis level
ratio
VOD = 1000 mV, DEM1 = GND,
DEM0 = VDD, (1),
3.5
dB
Tx de-emphasis level
ratio
VOD = 1000 mV, DEM1 = VDD,
DEM0 = GND, (1),
6
dB
(7)
(7)
TTX-HF-DJ-DD
Tx Dj > 1.5 Mhz
(8)
0.15
UI
TTX-LF-RMS
Tx RMS jitter < 1.5Mhz
(8)
3.0
ps RMS
TTX-RISE-FALL
Transmitter Rise/ Fall
Time
20% to 80% of differential output
voltage, Figure 3
TRF-MISMATCH
Tx rise/fall mismatch
20% to 80% of differential output
voltage (1) (9)
0.01
RLTX-DIFF
Differential Output
Return Loss
0.05- 1.25 Ghz, See Figure 6
-23
dB
1.25- 2.5 Ghz, See Figure 6
-20
dB
RLTX-CM
Common Mode Return
Loss
0.05- 2.5 Ghz, See Figure 6
-11
dB
ZTX-DIFF-DC
DC differential Tx
impedance
100
Ω
VTX-CM-AC-PP
Tx AC common mode
voltage
ITX-SHORT
transmitter short circuit
current limit
VTX-CM-DC- ACTIVE-IDLEDELTA
VTX-CM-DC- LINE-DELTA
TTX-IDLE-SET-TO -IDLE
TTX-IDLE-TO -DIFF-DATA
TPDEQ
(1) (9)
ps
0.1
UI
mVpp
90
mA
Absolute Delta of DC
Common Mode Voltage
during L0 and electrical
Idle
40
mV
Absolute Delta of DC
Common Mode Voltage
between Tx+ and Tx-
25
mV
6.5
9.5
nS
5.5
8
nS
Total current transmitter can
supply when shorted to VDD or
GND
Max time to transition
to valid diff signaling
after leaving Electrical
Idle
VIN = 800 mVp-p, 5 Gbps,
Figure 5
Max time to transition
to valid diff signaling
after leaving Electrical
Idle
VIN = 800 mVp-p, 5 Gbps,
Figure 5
Differential Propagation EQ = 11,
Delay
+4.0 dB @ 2.5 GHz , Figure 4
150
200
250
ps
Differential Propagation EQ = FF,
Delay
Equalizer Bypass, Figure 4
120
170
220
ps
27
ps
(10) (11)
TLSK
67
100
(10)
TPD
50
Lane to Lane Skew in a TA = 25C,VDD = 2.5V
(12) (11)
Single Part
(7)
(8)
Measured with a repeating K28.5 pattern at a data rate of 2.5 Gbps and 5.0 Gbps.
PCIe 2.0 transmit jitter specifications - actual device jitter is much less. Actual device Rj and Dj has been characterized and specified
with test loads outlined in the EQUALIZATION and DE-EMPHASIS sections of the Electrical Characteristics table.
(9) Specified by device characterization
(10) Propagation Delay measurements will change slightly based on the level of EQ selected. EQ Bypass will result in the shortest
propagation delays.
(11) Propagation Delay measurements for Part to Part skew are all based on devices operating under indentical temperature and supply
voltage conditions.
(12) Specified by device characterization
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
13
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
(1) (2)
Symbol
TPPSK
Parameter
Conditions
Min
Max
Units
35
ps
0.02
0.09
UIP-P
42” of 5 mil stripline FR4,
EQ1,0=F,1; K28.5 pattern,
DEMx=0, Tx Launch Amplitude 1.0
Vp-p, SD_TH=F. (13) (14)
0.02
0.04
UIP-P
Residual Deterministic
Jitter at 5 Gbps
7 meters of 24 AWG PCIe cable,
EQ1,0=1,0; K28.5 pattern,
DEMx=0, Tx Launch Amplitude 1.0
Vp-p, SD_TH=F. (13) (14)
0.02
0.11
UIP-P
Residual Deterministic
Jitter at 2.5 Gbps
7 meters of 24 AWG PCIe cable,
EQ1,0=1,0; K28.5 pattern,
DEMx=0, Tx Launch Amplitude 1.0
Vp-p, SD_TH=F. (13) (14)
0.03
0.07
UIP-P
Random Jitter
Tx Launch Amplitude 1.0 Vp-p,
SD_TH=F, Repeating 1100b
(D24.3) pattern. (13)
<0.5
Part to Part
Propagation Delay
Skew
TA = 25C,VDD = 2.5V
Residual Deterministic
Jitter at 5 Gbps
42” of 5 mil stripline FR4,
EQ1,0=F,1; K28.5 pattern,
DEMx=0, Tx Launch Amplitude 1.0
Vp-p, SD_TH=F. (13) (14)
Residual Deterministic
Jitter at 2.5 Gbps
Typ
EQUALIZATION
DJE1
DJE2
DJE3
DJE4
RJ
psrms
DE-EMPHASIS
Residual Deterministic
Jitter at 5 Gbps
DJD1
28” of 5 mil stripline FR4,
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,1; Tx Launch
Amplitude 1.0 Vp-p, SD_TH=F.
(13)
0.02
0.09
UIP-P
0.03
0.05
UIP-P
0.03
0.13
UIP-P
0.04
0.06
UIP-P
(14)
Residual Deterministic
Jitter at 2.5 Gbps
DJD2
28” of 5 mil microstrip FR4,
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,0; Tx Launch
Amplitude 1.0 Vp-p, SD_TH=F.
(15)
(16)
Residual Deterministic
Jitter at 5 Gbps
DJD3
7 meters of 24 AWG PCIe cable,
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,1; Tx Launch
Amplitude 1.0 Vp-p, SD_TH=F. (15)
(16)
Residual Deterministic
Jitter at 2.5 Gbps
DJD4
7 meters of 24 AWG PCIe cable,
EQ1,0=F,F; K28.5 pattern,
DEM1,0=F,0; Tx Launch
Amplitude 1.0 Vp-p, SD_TH=F. (15)
(16)
(13) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(14) Residual DJ measurements subtract out deterministic jitter present at the generator outputs. For 2.5 Gbps generator Dj = 0.0275 UI and
for 5.0 Gbps generator Dj = 0.035 UI.
(15) Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(16) Residual DJ measurements subtract out deterministic jitter present at the generator outputs. For 2.5 Gbps generator Dj = 0.0275 UI and
for 5.0 Gbps generator Dj = 0.035 UI.
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
14
Data, Clock Input Low Voltage
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Electrical Characteristics — Serial Management Bus Interface (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor
or Current Source
VDD
Nominal Bus Voltage
Min
Typ
2.1
High Power Specification
Units
3.6
V
4
mA
2.375
(1)
Max
-200
3.6
V
+200
µA
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SCL
(1) (2)
RTERM
External Termination Resistance
pull to VDD = 2.5V ± 5% OR 3.3V ±
10%
Pullup VDD = 3.3V,
2000
Ω
Pullup VDD = 2.5V,
1000
Ω
-15
µA
10
(1) (2) (3)
(1) (2) (3)
pF
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 7
(4)
FSMB
Bus Operating Frequency
TBUF
Bus Free Time Between Stop and
Start Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
10
100
kHz
4.7
µs
4.0
µs
4.7
µs
At IPULLUP, Max
TSU:STA
Repeated Start Condition Setup
Time
TSU:STO
Stop Condition Setup Time
4.0
µs
THD:DAT
Data Hold Time
300
ns
TSU:DAT
Data Setup Time
TTIMEOUT
Detect Clock Low Timeout
TLOW
Clock Low Period
250
(5)
THIGH
Clock High Period
TLOW:SEXT
Cumulative Clock Low Extend Time
(Slave Device)
(5)
tF
Clock/Data Fall Time
tR
tPOR
(5)
ns
35
4.7
(5)
(1)
(2)
(3)
(4)
25
4.0
ms
µs
50
µs
2
ms
(5)
300
ns
Clock/Data Rise Time
(5)
1000
ns
Time in which a device must be
operational after power-on reset
(5)
500
ms
Recommended value. Parameter not tested in production.
Recommended maximum capacitance load per bus segment is 400pF.
Maximum termination voltage should be identical to the device supply voltage.
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
TIMING DIAGRAMS
Figure 3. CML Output Transition Times
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
15
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Figure 4. Propagation Delay Timing Diagram
Figure 5. Idle Timing Diagram
Supply
Iconnect/PC
Biasing/blocking Circuit
Rt + 2Rl = 98:
Gnd
2.5V
Rl
OUT+
PCIe EVK board
Bias T
Rt
CSA8000B w/TDR module
Biasing/
blocking
PCI402
Rl
Bias T
OUT-
Figure 6. Input and Output Return Loss Setup
16
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tF
tHD:DAT
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
ST
SP
Figure 7. SMBus Timing Parameters
SYSTEM MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be
pulled high to enable SMBus mode and allow access to the configuration registers.
The DS50PCI402 has the AD[3:0] inputs in SMBus mode. These pins are the user set SMBus slave address
inputs. The AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device
default address byte is A0'h. Based on the SMBus 2.0 specification, the DS50PCI402 has a 7-bit slave address
of 1010000'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The device
address byte can be set with the use of the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant. External pull-up resistor is required on the SDA.
The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also
require an external pull-up resistor and it depends on the Host that drives the bus.
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See Register Description table for register address, type
(Read/Write, Read Only), default value and function information.
When SMBus is enabled, the DS50PCI402 must use one of the following De-emphasis settings (Table 9).
The driver de-emphasis value is set on a per channel basis using 8 different registers. Each register (0x11, 0x18,
0x1F, 0x26, 0x2E, 0x35, 0x3C, 0x43) requires one of the following De-emphasis settings when in SMBus mode.
See Table 5 for suggested DE settings at 2.5 and 5.0 Gbps operation.
Table 9. De-Emphasis Register Settings (must write one of the following when in SMBus mode)
De-Emphasis Value
Register Setting
0.0 dB
0x01
-3.5 dB
0xE8
-6 dB
0x88
-9 dB
0x90
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
17
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Table 9. De-Emphasis Register Settings (must write one of the following when in SMBus
mode) (continued)
De-Emphasis Value
Register Setting
-12 dB
0xA0
WRITING A REGISTER
To
1.
2.
3.
4.
5.
6.
7.
write a register, the following protocol is used (see SMBus 2.0 specification).
The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
The Device (Slave) drives the ACK bit (“0”).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (“0”).
The Host drive the 8-bit data byte.
The Device drives an ACK bit (“0”).
The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
Please see SMBus Register Map Table for more information.
SMBus REGISTER WRITES:
The DS50PCI402 outputs will NOT be PCIe compliant with the SMBus registers enabled (ENSMB = 1) until the
VOD levels have been set. Below is an example to configure the VOD level to a PCIe compliant amplitude and
adjust the DE and EQ signal conditioning to work with a 7m PCIe cable interconnect on the input B-side / output
A-side of the device
1. Reset the SMBus registers to default values:
– Write 01'h to address 0x00.
2. Set VOD = 1.0V for all channels (OA[3:0] and OB[3:0]):
– Write 0F'h to address 0x10, 0x17, 0x1E, 0x25, 0x2D, 0x34, 0x3B, 0x42.
3. Set equalization to external pin level EQ[1:0] = 10 (~15.5 dB at 2.5 GHz) for all channels (IB[3:0]):
– Write 39'h to address 0x0F, 0x16, 0x1D, 0x24.
4. Set de-emphasis to DE[1:0] = F1 or -12 dB enhanced for all A channels (OA[3:0]):
– Write A0'h to address 0x2E, 0x35, 0x3C, 0x43.
18
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
IDLE AND RATE DETECTION TO EXTERNAL PINS
The functions of IDLE and RATE detection to external pins for monitoring can be supported in SMBus mode. The
external GPIO pins of 19, 20, 46 and 47 will be changed and they will serve as outputs for IDLE and RATE
detect signals.
The following external pins should be set to auto detection:
RATE = F (FLOAT) – auto RATE detect enabled
TXIDLEA/B = F (FLOAT) – auto IDLE detect enabled
There are 4 GPIO pins that can be configured as outputs with reg_4E[0].
To disable the external SMBus address pins, so pin 46 and 47 can be used as outputs:
Write 01'h to address 0x4E.
Care must be taken to ensure that only the desired status block is enabled and attached to the external pin as
the status blocks can be OR’ed together internally. Register bits reg_47[5:4] and bits reg_4C[7:6] are used to
enable each of the status block outputs to the external pins. The channel status blocks can be internally OR’ed
together to monitor more than one channel at a time. This allows more information to be presented on the status
outputs and later if desired, a diagnosis of the channel identity can be made with additional SMBus writes to
register bits reg_47[5:4] and bits reg_4C[7:6].
Below are examples to configure the device and bring the internal IDLE and RATE status to pins 19, 20, 46, 47.
To monitor the IDLE detect with two channels ORed (CH0 with CH2, CH1 with CH3, CH4 with CH6, CH5 with
CH7):
Write 32'h to address 0x47.
The following IDLE status should be observable on the external pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means IDLE is detected (no signal present).
Pin = LOW (GND) means ACTIVE (data signal present).
To monitor the RATE detect with two channels ORed (CH0 with CH2, CH1 with CH3, CH4 with CH6, CH5 with
CH7):
Write C0'h to address 0x4C.
The following RATE status should be observable on the external pins:
pin 19 – CH0 with CH2,
pin 20 – CH1 with CH3,
pin 46 – CH4 with CH6,
pin 47 – CH5 with CH7.
Pin = HIGH (VDD) means high data rate is detected (6 Gbps).
Pin = LOW (GND) means low rate is detected (3 Gbps).
Table 10. SMBus Register Map
Address
Register Name
Bit (s) Field
Type
Default Description
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
19
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Table 10. SMBus Register Map (continued)
0x00
Reset
7:1
Reserved
0
Reset
R/W
0x00
Set bits to 0.
SMBus Reset
1: Reset registers to default value
0x01
PWDN Channels
7:0
PWDN CHx
R/W
0x00
Power Down per Channel
[7]: CHA_3
[6]: CHA_2
[5]: CHA_1
[4]: CHA_0
[3]: CHB_3
[2]: CHB_2
[1]: CHB_1
[0]: CHB_0
00'h = all channels enabled
FF'h = all channels disabled
0x02
PWDN Control
7:1
Reserved
R/W
0x00
Set bits to 0.
0
Override PWDN
7:5
Reserved
4
Override IDLE
0: Allow IDLE pin control
1: Block IDLE pin control
3
Reserved
Set bit to 0.
2
Override RATE
0: Allow RATE pin control
1: Block RATE pin control
1:0
Reserved
Set bits to 0.
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
CH0 - CHB0
EQ Control
7:6
Reserved
5:0
CH0 IB0 EQ
CH0 - CHB0
VOD Control
7
Reserved
5:0
CH0 OB0 VOD
0x08
0x0E
0x0F
0x10
20
Pin Control Override
CH0 - CHB0
IDLE RATE Select
0: Allow PWDN pin control
1: Block PWDN pin control
R/W
R/W
R/W
0x00
0x00
0x20
Set bits to 0.
Set bits to 0.
Set bits to 0.
IB0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] = Hex
Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
R/W
0x03
Set bit to 0.
OB0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Table 10. SMBus Register Map (continued)
0x11
CH0 - CHB0
DE Control
7:0
CH0 OB0 DEM
R/W
0x03
OB0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level Control]
= Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x12
CH0 - CHB0
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
CH1 - CHB1
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
CH1 - CHB1
EQ Control
7:6
Reserved
5:0
CH1 IB1 EQ
CH1 - CHB1
VOD Control
7
Reserved
5:0
CH1 OB1 VOD
0x15
0x16
0x17
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x20
Set bits to 0.
Set bits to 0.
IB1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] = Hex
Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
R/W
0x03
Set bit to 0.
OB1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
21
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Table 10. SMBus Register Map (continued)
0x18
CH1 - CHB1
DE Control
7:0
CH1 OB1 DEM
R/W
0x03
OB1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level Control]
= Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x19
CH1 - CHB1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
CH2 - CHB2
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
CH2 - CHB2
EQ Control
7:6
Reserved
5:0
CH2 IB2 EQ
CH2 - CHB2
VOD Control
7
Reserved
5:0
CH2 OB2 VOD
0x1C
0x1D
0x1E
22
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x20
Set bits to 0.
Set bits to 0.
IB2 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] = Hex
Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
R/W
0x03
Set bit to 0.
OB2 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Table 10. SMBus Register Map (continued)
0x1F
CH2 - CHB2
DE Control
7:0
CH2 OB2 DEM
R/W
0x03
OB2 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level Control]
= Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x20
CH2 - CHB2
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
CH3 - CHB3
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
CH3 - CHB3
EQ Control
7:6
Reserved
5:0
CH3 IB3 EQ
CH3 - CHB3
VOD Control
7
Reserved
5:0
CH3 OB3 VOD
0x23
0x24
0x25
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x20
Set bits to 0.
Set bits to 0.
IB3 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] = Hex
Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
R/W
0x03
Set bit to 0.
OB3 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
23
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Table 10. SMBus Register Map (continued)
0x26
CH3 - CHB3
DE Control
7:0
CH3 OB3 DEM
R/W
0x03
OB3 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level Control]
= Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x27
CH3 - CHB3
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
CH4 - CHA0
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
CH4 - CHA0
EQ Control
7:6
Reserved
5:0
CH4 IA0 EQ
CH4 - CHA0
VOD Control
7
Reserved
5:0
CH4 OA0 VOD
0x2B
0x2C
0x2D
24
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x20
Set bits to 0.
Set bits to 0.
IA0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] = Hex
Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
R/W
0x03
Set bit to 0.
OA0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Table 10. SMBus Register Map (continued)
0x2E
CH4 - CHA0
DE Control
7:0
CH4 OA0 DEM
R/W
0x03
OA0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level Control]
= Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x2F
CH4 - CHA0
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
CH5 - CHA1
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
CH5 - CHA1
EQ Control
7:6
Reserved
5:0
CH5 IA1 EQ
CH5 - CHA1
VOD Control
7
Reserved
5:0
CH5 OA1 VOD
0x32
0x33
0x34
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x20
Set bits to 0.
Set bits to 0.
IA1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ0 EQ1] = Register [EN] [GST] [BST] = Hex
Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
R/W
0x03
Set bit to 0.
OA1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
25
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Table 10. SMBus Register Map (continued)
0x35
CH5 - CHA1
DE Control
7:0
CH5 OA1 DEM
R/W
0x03
OA1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level Control]
= Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x36
CH5 - CHA1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
CH6 - CHA2
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
CH6 - CHA2
EQ Control
7:6
Reserved
5:0
CH6 IA2 EQ
CH6 - CHA2
VOD Control
7
Reserved
5:0
CH6 OA2 VOD
0x39
0x3A
0x3B
26
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x20
Set bits to 0.
Set bits to 0.
IA2 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ1 EQ0] = Register [EN] [GST] [BST] = Hex
Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
R/W
0x03
Set bit to 0.
OA2 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
Table 10. SMBus Register Map (continued)
0x3C
CH6 - CHA2
DE Control
7:0
CH6 OA2 DEM
R/W
0x03
OA2 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level Control]
= Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x3D
CH6 - CHA2
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
CH7 - CHA3
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 Gbps
1: 5.0 Gbps
CH7 - CHA3
EQ Control
7:6
Reserved
5:0
CH7 IA3 EQ
CH7 - CHA3
VOD Control
7
Reserved
5:0
CH7 OA3 VOD
0x40
0x41
0x42
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x20
Set bits to 0.
Set bits to 0.
IA3 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Pin [EQ0 EQ1] = Register [EN] [GST] [BST] = Hex
Value
FF = 100000 = 20'h = Bypass (Default)
11 = 101010 = 2A'h
00 = 110000 = 30'h
F0 = 110010 = 32'h
10 = 111001 = 39'h
F1 = 110101 = 35'h
01 = 110111 = 37'h
0F = 111011 = 3B'h
1F = 111101 = 3D'h
R/W
0x03
Set bit to 0.
OA3 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
27
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
Table 10. SMBus Register Map (continued)
0x43
CH7 - CHA3
DE Control
7:0
CH7 OA3 DEM
R/W
0x03
OA3 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Pin [DEM1 DEM0] = Register [TYPE] [Level Control]
= Hex Value
00 = 00000001 = 01'h = 0.0 dB
01 = 11101000 = E8'h = −3.5 dB
11 = 10001000 = 88'h = −6.0 dB
0F = 10010000 = 90'h = −9.0 dB
1F = 10100000 = A0'h = −12.0 dB
F0 = 10010000 = 90'h = −9.0 dB
F1 = 10100000 = A0'h = −12.0 dB
FF = 11000000 = C0'h = Reserved
0x44
CH7 - CHA3
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
Global VOD Adjust
7:2
Reserved
1:0
VOD Adjust
0x47
28
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x02
Set bits to 0.
00
01
10
11
Submit Documentation Feedback
= -25.0%
= -12.5%
= +0.0% (Default)
= +12.5%
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
APPLICATION INFORMATION
GENERAL RECOMMENDATIONS
The DS50PCI402 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the information below and the latest version of the LVDS Owner's Manual for more detailed information on
high speed design tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and LPDS outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See AN1187 (SNOA401) for additional information on WQFN packages.
20 mils
EXTERNAL MICROSTRIP
100 mils
20 mils
INTERNAL STRIPLINE
VDD
VDD
18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
19
54
20
53
21
52
51
22
BOTTOM OF PKG
23
VDD
50
GND
24
49
25
48
26
47
27
46
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
VDD
VDD
Figure 8. Typical Routing Options
The graphic shown above depicts different transmission line topologies which can be used in various
combinations to achieve the optimal system performance. Impedance discontinuities at the differential via can be
minimized or eliminated by increasing the swell around each hole and providing for a low inductance return
current path. When the via structure is associated with thick backplane PCB, further optimization such as back
drilling is often used to reduce the deterimential high frequency effects of stubs on the signal path.
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
29
DS50PCI402
SNLS320H – APRIL 2010 – REVISED MARCH 2013
www.ti.com
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS50PCI402 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01 μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS50PCI402. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
Typical Performance Eye Diagrams and Curves
DS50PCI402 Return Loss
0
-RLRX-CM (S11)
-5
Return Loss (dB)
-10
-RLRX-DIFF (SDD11)
S11
-15
-20
SDD11
-25
-30
-35
-40
0.00
0.50
1.00
1.50
2.00
2.50
Frequency (GHz)
Figure 9. Receiver Return Loss Mask for 5.0 Gbps
0
-RLTX-CM (S11)
-5
Return Loss (dB)
-10
-RLTX-DIFF (SDD11)
S11
-15
-20
-25
SDD11
-30
-35
-40
0.00
0.50
1.00
1.50
2.00
2.50
Frequency (GHz)
Figure 10. Transmitter Return Loss Mask for 5.0 Gbps
30
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
DS50PCI402
www.ti.com
SNLS320H – APRIL 2010 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision G (March 2013) to Revision H
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 30
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS50PCI402
31
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DS50PCI402SQ/NOPB
ACTIVE
WQFN
NJY
54
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-10 to 85
DS50PCI402SQ
DS50PCI402SQE/NOPB
ACTIVE
WQFN
NJY
54
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-10 to 85
DS50PCI402SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS50PCI402SQ/NOPB
WQFN
NJY
54
2000
330.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
DS50PCI402SQE/NOPB
WQFN
NJY
54
250
178.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS50PCI402SQ/NOPB
WQFN
NJY
54
2000
367.0
367.0
38.0
DS50PCI402SQE/NOPB
WQFN
NJY
54
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
NJY0054A
WQFN
SCALE 2.000
WQFN
5.6
5.4
B
A
PIN 1 INDEX AREA
0.5
0.3
0.3
0.2
10.1
9.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
2X 4
SEE TERMINAL
DETAIL
3.51±0.1
19
(0.1)
27
28
18
50X 0.5
7.5±0.1
2X
8.5
1
45
54
PIN 1 ID
(OPTIONAL)
46
54X
54X
0.5
0.3
0.3
0.2
0.1
0.05
C A
C
B
4214993/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NJY0054A
WQFN
WQFN
(3.51)
SYMM
54X (0.6)
54
54X (0.25)
SEE DETAILS
46
1
45
50X (0.5)
(7.5)
SYMM
(9.8)
(1.17)
TYP
2X
(1.16)
28
18
( 0.2) TYP
VIA
19
27
(1) TYP
(5.3)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214993/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
NJY0054A
WQFN
WQFN
SYMM
METAL
TYP
(0.855) TYP
46
54
54X (0.6)
54X (0.25)
1
45
50X (0.5)
(1.17)
TYP
SYMM
(9.8)
12X (0.97)
18
28
19
27
12X (1.51)
(5.3)
SOLDERPASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
4214993/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated