AMIS-710651-A4: Color CIS Module Data Sheet 1.0 Description The AMIS-710651-A4 (PI651MC-A4C) is a color contact image sensor (CIS) module. The module contains 15 image-sensor chips, AMIS-720058 (PI6058E), a product of AMI Semiconductor. These chips are sequentially cascaded to provide a line array of photodetectors. Each photo-detector in the image sensor possesses its own independent processing circuit. As the photo-sensors’ digital shift register scans the image sensor chip, it sequentially produces the video signals at the output of the image array. The AMIS710651-A4’s mechanical outline drawing is shown in Figure 6. 2.0 Key Features • • • • • • • • • • 600 and 300dpi selectable resolutions 23.6dpm and 11.8dpm, 216mm scanning length 344 or 172 image sensor elements (pixels) Low power-single power supply at 3.3V Light source, lens and sensor are integrated into a single module High speed page scan - up to 1.30msec/line @ 4MHz pixel rate Analog output RGB color LED light source Compact size ≅ 12.3mm x 18.9mm x 23mm Light weight 3.0 Overview The AMIS-710651-A4 has a 216mm read width. Its minimum line rate is 1.30ms/line with a maximum clock pulse (CP) equal to 4.0MHz (pixel rate (PRATE) of 4.0MHz). Unless stated otherwise, all data was taken with CP = 3.0MHz (PRATE = 3.0MHz) and an integration time of 1.75ms/line. The sensor photo-site density is 23.64elements/mm. The module has one analog video output, two clock inputs, clock and start pulse (CP and SP), one reference voltage input for the amplifier output bias level control, one power supply input and four LED inputs. 4.0 Scan Overview Table 1 describes a scan overview. Table 1: Scan Overview Parameter Read width Sensor photo-site density Active photo elements (1) Line read time (1) Clock frequency (1) Pixel rate Specification 216mm 42.3 elements/mm 84.7 elements/mm 5160 elements ~ 1.30ms/line 4.0MHz 4.0MHz Note 600dpi 300dpi Tested @ 4.0MHz (PRATE) Max. rate Max. rate Note: Since the light power is fixed, if the line-scan rate is set proportional to the clock rate, then the integration time reduces as the clock frequency is increased, hence its exposure. The reduction in the exposure proportionately reduces the video output. Accordingly, the signal-to-noise ratio reduces as the frequency increased. AMI Semiconductor – Aug. 06, M-20609-001 www.amis.com 1 AMIS-710651-A4: Color CIS Module Data Sheet 5.0 Physical Overview Table 2 describes a physical overview. Table 2: Physical Overview Parameter Image sensors Module outside dimension Circuit power supply Data output Specification A<OS-720058 ≅12.3mm x 18.9mm x 232mm Typical 3.3V @ 70mA One analog output Note See image sensor data sheet Figure 6 6.0 Recommended Operating Conditions All tests were conducted at the typical pixel rate of 3.0MHz ° Table 3: Recommended Operating Conditions (25 C) Parameter Symbol Power supply VDD IDD (1) Video output level VP (2) Reference voltage input VREF Input voltage for digital high (input clocks, SP VIH and CP) Input voltage for digital low (input clocks SS VIL and CP) (3) Clock frequency FREQ (3) Pixel frequency PRATE (4) Clock pulse high duty cycle DUTY Clock pulse high duration TPW (5) Integration time TINT (6) Operating temperature TOP Notes: (1) (2) (3) (4) (5) (6) Min. 0.15 3.2 Typ. 3.3 70 0.2 1.2 VDD 0 0.50 0.50 3.0 3.0 50 200 ~1300 25 Max. VDD +0.3 Units V mA V V V 0.8 V 4.0 4.0 MHz MHz % ns µs ° C 100 10000 50 VP represents the average value Vp(n) for all n in line scans, where n is the sequential number of a pixel. This signal pixel level should be operated at less than saturation levels, i.e., <1.3V. VREF is used to adjust the video output bias. Under normal operation it is left unconnected. FREQ is the input clock (CP) frequency and the pixel rate (PRATE). The minimum rate for FREQ and PRATE should be consistent with the maximum TINT, see Note (5). DUTY is the ratio of the clock’s pulse width to its pulse period. TINT is the time interval between two start pulses (SP). Hence, if SP is generated from a clock count down circuit, it will be directly proportional to the clock frequency. There must be a minimum of (56+1204) clock cycles between the two SPs. The longest integration time is determined by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion to determine the desired leakage tolerance level for the given system. TOP is a conservative engineering estimate. It is based on measurements of similar CIS modules. In production, they are measured under standard QA practices, that is, under the control of ISO 9000 standards. AMI Semiconductor – Aug. 06, M-20609-001 www.amis.com 2 AMIS-710651-A4: Color CIS Module Data Sheet 7.0 Electro-Optical Characteristics (25°C) All tests were conducted at the typical pixel rate of 3.0MHz Table 4: Electro-Optical Characteristics (25°C) Parameter Number of active photo detectors Symbol Typ. 5160 2580 42.3 84.6 ~1.75 3.0 3.0 0.2 < /-30 <60 <25 <150 1.2<VDL<1.5 <24 <4 40 Pixel-to-pixel spacing Line scan rate Clock frequency Pixel rate Bright output voltage Bright output non-uniformity Bright output total non-uniformity Adjacent pixel non-uniformity Dark non-uniformity Dark output voltage range Random noise (1) TINT (2) FREQ (2) PRATE (3) Vpavg (4) +/- Up (5) Uptotal (6) Uadj (7) Ud (8) VDL (9) RNL Modulation transfer function MTF (10) Units Elements µm ms/line MHz MHz V % % % mV V p-p mV rms mV % Note 600dpi 300dpi 600dpi 300dpi @ 3.0MHz clock frequency Notes: (1) (2) (3) Scan rate (integration time), TINT, is determined by the time interval between two SPs. See Table 3, Note 5. Clock frequency, FREQ, is the input clock frequency and its corresponding PRATE is the pixel sample rate. Bright output voltage Vpmax = maximum pixel value of Vp(n), Vpmin = minimum pixel value of Vp(n), Vpavg = ∑ Vp(n)/5160; where Vp(n) is the nth pixel in a line scan with the module scanning a uniform white target and Vp values are measured with a uniform exposure. (4) Bright output non-uniformity Up(+) = [(Vpmax - Vpavg) / Vpavg] x 100%, Up(-)= [(Vpavg - Vpmin) / Vpavg] x 100%, whichever polarity with the highest absolute value is selected. (5) Bright output total non-uniformity: Uptotal = [Vpmax -Vpmin]/Vpavg x 100% (6) Adjacent pixel non-uniformity: Upadj = MAX[ | (Vp(n) - Vp(n+l) | / Vp(n))] x 100% Upadj is the non-uniformity in percentage. It is the maximum difference amplitude between two neighboring pixels. (7) Dark non-uniformity: Ud = Vdmax – Vdmin Vdmax is the max. pixel value of the video pixel in the dark. Vdmin is the min. pixel value of the video pixel in the dark. The references for these levels are the dark level (VDL). (8) Dark output voltage range (VDL) is the level between the output dark level and ground. (9) Random noise (RNL): The rms value was calculated from measured p-p thermal noise taken at output from a selected pixel. The rms is defined as one standard deviation of at least 64 pixels sampled. The calculation of the standard deviation is based on an idealized Gaussian probability curve. (10) Modulation transfer function is defined as MTF = [(Vmax - Vmin) / (Vmax + Vmin)] x 100%. MTF is a measure at the glass surface. Vmax is the maximum output voltage at 300lp/inch (at 1/2 of the optical Nyquest frequency) and Vmin is the minimum output voltage at 300lp/inch. 8.0 Electrical Clocking Characteristics ° Table 5: Clock Amplitude Duty Characteristics (25 C) Parameter Symbol (1) Clock input voltage VIH (1) VIL (2) Clock frequency FREQ (2) Pixel rate PRATE (4) Line read time TINT (5) Clock pulse duty cycle Ratio = twp / tp Notes: (1) (2) (3) (4) (5) Min. Typ. See Table 3 Note 3 ~1.30 45 3.0 3.0 Max. Units 4.0 4.0 ~10 MHz MHz ms % The clocks, CP and SP are compatible with CMOS clock drivers. FREQ is the clock frequency and PRATE is the pixel sample rate. Minimum values are not specified because it will be determined by the maximum TINT value. See Note 4. TINT is the line scan read time, which depends on the interval between the SP entries. The minimum time is determined by (1/clock frequency) x (5160 + 150) pixels. Note that there are a few extra pixels used to determine the typical line time of 820µsec @ 3.0MHz PRATE (see Figure 1). There are 55 clocks required to transfer and reset the photo-sites before the video can be scanned out. The longest integration time is determined by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion and determine the desired tolerance level for the given system. The definition for the symbols used in the ratio is defined in Figure 1. A duty cycle of exactly 50 percent is recommended to maintain equal pixel duration between odd and even pixels. AMI Semiconductor – Aug. 06, M-20609-001 www.amis.com 3 AMIS-710651-A4: Color CIS Module Data Sheet 9.0 Timing Diagram GBST CLK 1 2 3 4 79 80 81 82 83 84 85 416 86 417 418 422 423 424 425 426 SO VOUT 1 2 4 3 82 Inactive Pixels (82 Clocks) 334 335 336 340 341 342 343 344 344 Active Pixels (344 Clocks) Figure 1: Overall Timing Diagram for the 600dpi Mode GBST CLK 1 2 3 4 79 80 81 82 83 84 85 244 86 245 246 250 251 252 253 254 SO VOUT 1 2 82 Inactive Pixels (82 Clocks) 3 4 162 163 164 168 169 170 171 172 172 Active Pixels (172 Clocks) Figure 2: Overall Timing Diagram for the 300dpi Mode Figure 1 and Figure 2 detail the timing of the CLK, GBST, Vout, and SI/SO signals in further detail, which have the same timing requirements for both the 600 and 300dpi modes. In Figure 1, note that Pixel 83 is the first active pixel because the first 82 pixels are dummy pixels. AMI Semiconductor – Aug. 06, M-20609-001 www.amis.com 4 AMIS-710651-A4: Color CIS Module CLKpw CLKpw Data Sheet CLKp 50% 50% CLK 50% Thold CLKrt Tset CLKft GBST GBSTft GBSTrt Prt 90% VOUT SI/SO SI/SOrt SI/SOft Figure 3: Rise and Fall Times for both the 600/300dpi Modes 1 CLK Thold 2 Thold 3 82 3 82 83 84 85 Tset GBST Tset Video Signal (Vout) 1 2 83 Figure 4: Timing of GBST-to-First Pixel of the First Sensor for both the 600/300dpi Modes AMI Semiconductor – Aug. 06, M-20609-001 www.amis.com 5 84 85 AMIS-710651-A4: Color CIS Module Data Sheet 50% 50% CLK TS 90% VOUT Prt 1 Pixel Figure 5: Pixel Timing Table 6: Clock Timing Characteristics for Timing Diagrams Parameter Symbol Min. Clock cycle time CLKp 250 Clock pulse width CLKpw Clock duty cycle Prohibit crossing time SP tprh 30 Data setup time Tset 20 Data hold time Thold 25 Signal delay time tdl Signal settling time Signal fall time Notes: (1) (2) Typ. 250 125 50 Max. 2000 tst tsigf 50 Units ns ns % ns ns ns ns 130 60 ns ns All of the symbol definitions used in Table 6 are shown in the figures in Section 9.0. The clocks, CP and SP are compatible with CMOS clock drivers. Maximum clock cycle time, as with minimum FREQ, must be consistent with maximum TINT. See Table 3, Note 3. 10.0 Maximum Ratings Table 7: Maximum Ratings (Not to be Used for Continuous Operation) Parameter Symbol Power supply voltage VDD Input voltage VIN Ambient temperature TA (PCB surface) Ambient humidity Maximum operating case temperature AMI Semiconductor – Aug. 06, M-20609-001 www.amis.com Specification 3.3V VDD ° 0 to 50 C ° -10 to +75 C 0 to 80% ° 70 C HA PCB temperature 6 Note SP & CP Operational storage Non-condensing AMIS-710651-A4: Color CIS Module Data Sheet 11.0 I/O Connector Pin Configuration The connector is for a 12-pin flex-strip-line cable, PDK97-1201. The connector location is shown in Figure 6, an ISO drawing of the AMIS-710651-A4 module. It also shows the location of Pin 1. Use caution when connecting the power to the LED! Note that all the negative sides of the LED sources are connected to the cathodes. These I/O sources are current inputs. Constant current sources are used to control the balance of the color in the RGB outputs. Their typical voltage drops are between 2.3 to 2.7V. Under no circumstances should the applied current be greater than 30mA, otherwise the LED source will be damaged. Table 8: Connector Pin Outs Pin Number Pin Names 1 Analog signal output 2 Ground 3 Power supply Symbol VOUT GND VDD I/0 O I I 4 DPI-control SR I 5 Reference voltage VREF I 6 7 8 9 10 11 12 Start pulse Ground Clock Common LED green LED red LED blue SP GND CP (CLK on the schematic) VLED (common anode on the schematic) GLED RLED BLED I I I I I I I AMI Semiconductor – Aug. 06, M-20609-001 www.amis.com 7 Names and Functions Analog signal output Ground; 0V Positive 3.3V Selects resolution control For externally or internally controlling the dark bias level Shift register start pulse Ground; 0V Clock input for the module Common anodes for all LED, plus 5.0V terminal Cathode green LED input Cathode red LED input Cathode blue LED input AMIS-710651-A4: Color CIS Module Data Sheet 12.0 Mechanical Outline Drawing A simplified ISO drawing of the module housing is shown Figure 6. The drawing is not to scale but sufficient dimensions are shown for use in a preliminary application study. Furthermore, it shows the I/O connector location, its Pin 1 location, the read line location and LED pad locations. For detailed design information, please contact AMIS for a complete housing drawing. Figure 6: Mechanical Structure AMI Semiconductor – Aug. 06, M-20609-001 www.amis.com 8 AMIS-710651-A4: Color CIS Module Data Sheet 13.0 Company or Product Inquiries For more information about AMI Semiconductor, our technology and our product, visit our Web site at: http://www.amis.com North America Tel: +1.208.233.4690 Fax: +1.208.234.6795 Europe Tel: +32 (0) 55.33.22.11 Fax: +32 (0) 55.31.81.12 Production Technical Data - The information contained in this document applies to a product in production. AMI Semiconductor and its subsidiaries (“AMIS”) have made every effort to ensure that the information is accurate and reliable. However, the characteristics and specifications of the product are subject to change without notice and the information is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify that data being relied on is the most current and complete. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. Products sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no other warranty, express or implied, and disclaims the warranties of noninfringement, merchantability, or fitness for a particular purpose. AMI Semiconductor's products are intended for use in ordinary commercial applications. These products are not designed, authorized, or warranted to be suitable for use in life-support systems or other critical applications where malfunction may cause personal injury. Inclusion of AMIS products in such applications is understood to be fully at the customer’s risk. Applications requiring extended temperature range, operation in unusual environmental conditions, or high reliability, such as military or medical life-support, are specifically not recommended without additional processing by AMIS for such applications. Copyright © 2006 AMI Semiconductor, Inc. AMI Semiconductor – Aug. 06, M-20609-001 www.amis.com 9