AD ADG5404BRUZ High voltage, latch-up proof, 4-channel multiplexer Datasheet

High Voltage, Latch-up Proof,
4-Channel Multiplexer
ADG5404
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Latch-up proof
8 kV HBM ESD rating
Low on resistance (<10 Ω)
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS to VDD analog signal range
ADG5404
S1
S2
D
S3
S4
A0
A1
EN
09203-001
1 OF 4
DECODER
Figure 1.
APPLICATIONS
Relay replacement
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG5404 is a complementary metal-oxide semiconductor
(CMOS) analog multiplexer, comprising four single channels.
1.
The on-resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals.
The ADG5404 is designed on a trench process, which guards
against latch-up. A dielectric trench separates the P and N
channel transistors, thereby preventing latch-up even under
severe overvoltage conditions.
The ADG5404 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch
conducts equally well in both directions when on and has an
input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action.
2.
3.
4.
5.
6.
Trench Isolation Guards Against Latch-Up. A dielectric
trench separates the P and N channel transistors, thereby
preventing latch-up even under severe overvoltage
conditions.
Low RON.
Dual-Supply Operation. For applications where the analog
signal is bipolar, the ADG5404 can be operated from dual
supplies of up to ±22 V.
Single-Supply Operation. For applications where the
analog signal is unipolar, the ADG5404 can be operated
from a single-rail power supply of up to 40 V.
3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
No VL logic power supply required.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADG5404
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 1
ESD Caution...................................................................................8
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ............................9
Revision History ............................................................................... 2
Truth Table .....................................................................................9
Specifications..................................................................................... 3
Typical Performance Characteristics ........................................... 10
±15 V Dual Supply ....................................................................... 3
Test Circuits..................................................................................... 14
±20 V Dual Supply ....................................................................... 4
Terminology .................................................................................... 17
+12 V Single Supply ..................................................................... 5
Trench Isolation.............................................................................. 18
+36 V Single Supply ..................................................................... 6
Applications Information .............................................................. 19
Continuous Current per Channel, S or D ................................. 7
Outline Dimensions ....................................................................... 20
Absolute Maximum Ratings............................................................ 8
Ordering Guide .......................................................................... 20
REVISION HISTORY
7/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG5404
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
9.8
11
0.35
0.7
1.2
1.6
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −10 mA; see Figure 23
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −10 mA
14
16
0.9
1.1
2
2.2
nA typ
±0.25
±0.1
±0.75
±3.5
nA max
nA typ
±0.4
±2
±12
nA max
±0.1
±0.4
±2
±12
nA typ
nA max
2.0
0.8
0.002
5
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
220
−78
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−58
0.009
dB typ
% typ
53
−0.7
19
92
132
MHz typ
dB typ
pF typ
pF typ
pF typ
tOFF (EN)
285
330
247
278
168
183
12
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
ISS
45
55
0.001
VDD/VSS
1
V min
V max
μA typ
μA max
pF typ
187
242
160
204
125
145
45
tON (EN)
VS = ±10 V, IS = −10 mA
VDD = +16.5 V, VSS = −16.5 V
±0.05
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
Ω max
Ω typ
Ω max
70
1
±9/±22
Guaranteed by design; not subject to production test.
Rev. 0 | Page 3 of 20
μA typ
μA max
μA typ
μA max
V min/max
VS = VS = ±10 V, VD = ∓10 V; see Figure 24
VS = VS = ±10 V, VD = ∓10 V; see Figure 24
VS = VD = ±10 V; see Figure 25
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 31
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see
Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 1k Ω, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
ADG5404
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
25°C
9
10
0.35
0.7
1.5
1.8
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
VDD to VSS
V
Ω typ
Ω max
Ω typ
VS = ±15 V, IS = −10 mA; see Figure 23
VDD = +18 V, VSS = −18 V
VS = ±15 V, IS = −10 mA
13
15
0.9
1.1
2.2
2.5
Ω max
Ω typ
Ω max
VS = ±15 V, IS = −10 mA
nA typ
VS = ±15 V, VD = ∓15 V; see Figure 24
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
±0.05
±0.25
±0.1
±0.75
±3.5
Drain Off Leakage, ID (Off)
nA max
nA typ
±0.4
±0.1
±0.4
±2
±12
VS = VD = ±15 V; see Figure 25
±2
±12
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
VIN = VGND or VDD
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
VDD = +22 V, VSS = −22 V
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
5
Break-Before-Make Time Delay, tD
175
224
148
185
120
142
40
Charge Injection, QINJ
Off Isolation
290
−78
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
−58
0.008
dB typ
% typ
54
−0.6
18
88
129
MHz typ
dB typ
pF typ
pF typ
pF typ
tON (EN)
tOFF (EN)
262
301
222
250
159
173
10
Channel-to-Channel Crosstalk
Total Harmonic Distortion +
Noise
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
ISS
VDD/VSS
1
50
70
0.001
110
±9/±22
Guaranteed by design; not subject to production test.
Rev. 0 | Page 4 of 20
μA typ
μA max
μA typ
V min/max
VS = ±15 V, VD = ∓15 V; see Figure 24
RL = 300 Ω, CL = 35 pF
VS = +10 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 31
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
ADG5404
+12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
19
22
0.4
0.8
4.4
5.5
±0.02
±0.25
±0.05
±0.4
±0.05
±0.4
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
0 V to VDD
V
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −10 mA; see Figure 23
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
27
31
1
1.2
6.5
7.5
±0.75
±3.5
±2
±12
±2
±12
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
5
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
Break-Before-Make Time Delay, tD
266
358
260
339
135
162
125
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
92
−78
−58
0.075
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
43
−1.36
22
105
140
MHz typ
dB typ
pF typ
pF typ
pF typ
tON (EN)
tOFF (EN)
446
515
423
485
189
210
45
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
40
50
VDD
1
Ω max
Ω typ
Ω max
65
9/40
Guaranteed by design; not subject to production test.
Rev. 0 | Page 5 of 20
μA typ
μA max
V min/max
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = VD = 1 V/10 V; see Figure 25
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = +8 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 31
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1MHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 1k Ω, 6 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
ADG5404
+36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
10.6
12
0.35
0.7
2.7
3.2
±0.05
±0.25
±0.1
±0.4
±0.1
±0.4
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
0 V to VDD
V
Ω typ
Ω max
Ω typ
VS = 0 V to 30 V, IS = −10 mA; see Figure 23
VDD = 32.4 V, VSS = 0 V
VS = 0 V to 30 V, IS = −10 mA
15
17
0.9
1.1
3.8
4.5
±0.75
±3.5
±2
±12
±2
±12
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
5
196
256
170
214
130
172
52
V min
V max
μA typ
μA max
pF typ
280
−78
−58
0.03
47
−0.85
18
89
128
MHz typ
dB typ
pF typ
pF typ
pF typ
80
100
VDD
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
276
314
247
273
167
176
13
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion +
Noise
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
Ω max
Ω typ
Ω max
130
9/40
Guaranteed by design; not subject to production test.
Rev. 0 | Page 6 of 20
μA typ
μA max
V min/max
VS = 0 V to 30 V, IS = −10 mA
VDD =39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V; see Figure 24
VS = 1 V/30 V, VD = 30 V/1 V; see Figure 24
VS = VD = 1 V/30 V; see Figure 25
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 30
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V; see Figure 31
VS = 18 V, RS = 0 Ω, CL = 1 nF; see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1MHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 1k Ω, 18 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
ADG5404
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5.
Parameter
CONTINUOUS CURRENT, S OR D
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
25°C
85°C
125°C
Unit
165
290
96
141
49
57
mA max
mA max
176
282
101
146
51
58
mA max
mA max
114
203
72
112
42
53
mA max
mA max
149
263
89
133
48
56
mA max
mA max
Rev. 0 | Page 7 of 20
ADG5404
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs 1
Digital Inputs1
Peak Current, Sx or D Pins
Continuous Current, S or D 2
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
16-Lead TSSOP, θJA Thermal
Impedance (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free
1
2
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
515 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%
−40°C to +125°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
112.6°C/W
30.4°C/W
260(+0/−5)°C
Overvoltages at the Sx and D pins are clamped by internal diodes. Limit
current to the maximum ratings given.
See Table 5.
Rev. 0 | Page 8 of 20
ADG5404
1
14 A1
EN
2
13 GND
11 VDD
S1 3
TOP VIEW
(Not to Scale)
10 S3
9 S4
6
9
NC
7
8
NC
NC = NO CONNECT
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, VSS.
Figure 2. TSSOP Pin Configuration
09203-003
D
NC
11 S3
10 S4
NC 7
5
NC 8
4
S2
D 6
12 VDD
S1
TOP VIEW
(Not to Scale)
14 A1
ADG5404
NC 5
ADG5404
09203-002
3
12 GND
NC 2
S2 4
VSS
13 NC
16 EN
PIN 1
INDICATOR
VSS 1
A0
15 A0
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
15
2
16
3
4
5
6
7 to 9
10
11
12
13
14
Mnemonic
A0
EN
1
3
4
6
2, 5, 7, 8, 13
9
10
11
12
14
EP
Description
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are off.
When this pin is high, the Ax logic inputs determine the on switches.
Most Negative Power Supply Potential.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
No Connection.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
VSS
S1
S2
D
NC
S4
S3
VDD
GND
A1
Exposed Pad
TRUTH TABLE
Table 8.
EN
0
1
1
1
1
1
A1
X1
0
0
1
1
A0
X1
0
1
0
1
S1
Off
On
Off
Off
Off
X = don’t care.
Rev. 0 | Page 9 of 20
S2
Off
Off
On
Off
Off
S3
Off
Off
Off
On
Off
S4
Off
Off
Off
Off
On
ADG5404
TYPICAL PERFORMANCE CHARACTERISTICS
16
12
VDD = +10V
VDD = +9V VSS = –10V
VSS = –9V
TA = 25°C
14
10
ON RESISTANCE (Ω)
VDD = +11V
VSS = –11V
12
ON RESISTANCE (Ω)
TA = 25°C
10
8
VDD10
= +13.5V
VSS = –13.5V
6
VDD = +16.5V
VSS = –16.5V
VDD = +15V
VSS = –15V
VDD = 36V
VSS = 0V
VDD = 32.4V
VSS = 0V
8
6
VDD = 39.6V
VSS = 0V
4
4
2
–15
–10
–5
0
5
10
15
20
VS, VD (V)
0
09203-029
0
–20
0
5
10
15
20
25
30
35
40
45
VS, VD (V)
Figure 4. RON as a Function of VD (VS), Dual Supply
09203-028
2
Figure 7. RON as a Function of VD (VS), Single Supply
18
12
16
VDD = +18V
VSS = –18V
10
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
14
8
VDD = +20V
VSS = –20V
6
VDD = +22V
VSS = –22V
4
TA = +125°C
12
TA = +85°C
10
TA = +25°C
8
TA = –40°C
6
4
2
VDD = +15V
VSS = –15V
0
–15
–10
–20
–15
–10
–5
0
5
10
15
20
25
VS, VD (V)
09203-030
0
–25
10
15
16
VDD = +10V
VSS = 0V
VDD = 10.8V
VSS = 0V
VDD = +9V
VSS = 0V
14
12
ON RESISTANCE (Ω)
TA = 25°C
15
VDD = 11V
VSS = 0V
VDD = 12V
VSS = 0V
VDD = 13.2V
VSS = 0V
TA = +125°C
10
TA = +85°C
8
TA = +25°C
6
TA = –40°C
4
5
0
0
2
4
6
8
10
12
VS, VD (V)
14
Figure 6. RON as a Function of VD (VS), Single Supply
VDD = +20V
VSS = –20V
0
–20
–15
–10
–5
0
5
10
15
20
VS, VD (V)
Figure 9. RON as a Function of VD (VS) for Different Temperatures,
±20 V Dual Supply
Rev. 0 | Page 10 of 20
09203-024
2
09203-027
ON RESISTANCE (Ω)
5
Figure 8. RON as a Function of VD (VS) for Different Temperatures,
±15 V Dual Supply
25
10
0
VS, VD (V)
Figure 5. RON as a Function of VD (VS), Dual Supply
20
–5
09203-023
2
TA = 25°C
ADG5404
30
1.0
VDD = 12V
VSS = 0V
TA = +125°C
20
TA = +85°C
15
TA = +25°C
TA = –40°C
10
5
0
–0.5
IS (OFF) – +
ID, IS (ON) – –
–1.0
ID (OFF) + –
2
4
6
8
10
12
–2.0
0
25
50
75
100
125
TEMPERATURE (°C)
09203-033
0
VS, VD (V)
Figure 13. Leakage Currents vs. Temperature, ±20 V Dual Supply
Figure 10. RON as a Function of VD (VS) for Different Temperatures,
12 V Single Supply
0.6
16
14
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
LEAKAGE CURRENT (nA)
0.4
12
ON RESISTANCE (Ω)
ID (OFF) – +
IS (OFF) + –
–1.5
09203-025
0
ID, IS (ON) + +
0.5
LEAKAGE CURRENT (nA)
ON RESISTANCE (Ω)
25
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
TA = +125°C
10
TA = +85°C
8
TA = +25°C
6
TA = –40°C
4
ID, IS (ON) + +
ID (OFF) – +
IS (OFF) + –
0.2
0
–0.2
IS (OFF) – +
ID, IS (ON) – –
–0.4
0
5
10
15
20
25
30
35
40
VS, VD (V)
–0.6
09203-026
0
ID (OFF) + –
VDD = 36V
VSS = 0V
1.0
LEAKAGE CURRENT (nA)
0
IS (OFF) – +
ID, IS (ON) – –
125
ID (OFF) – +
IS (OFF) + –
0
IS (OFF) – +
–0.5
ID, IS (ON) – –
–1.0
ID (OFF) + –
ID (OFF) + –
–1.0
100
ID, IS (ON) + +
0.5
ID (OFF) – +
IS (OFF) + –
–0.5
75
VDD = 36V
VSS = 0V
VBIAS = 1V/30V
ID, IS (ON) + +
0.5
50
Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply
1.0
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
25
TEMPERATURE (°C)
Figure 11. RON as a Function of VD (VS) for Different Temperatures,
36 V Single Supply
–1.5
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 12. Leakage Currents vs. Temperature, ±15 V Dual Supply
–2.0
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. 0 | Page 11 of 20
09203-034
–1.5
09203-032
LEAKAGE CURRENT (nA)
0
09203-031
2
ADG5404
450
TA = 25°C
VDD = +15V
VSS = –15V
–10
TA = 25°C
400
–30
–40
–50
–60
–70
VDD = +20V
VSS = –20V
350
CHARGE INJECTION (pC)
OFF ISOLATION (dB)
–20
300
VDD = 36V
VSS = 0V
250
200
150
–80
–90
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
50
–20
09203-019
–100
–10
10
20
30
40
Figure 19. Charge Injection vs. Source Voltage
350
0
TA = 25°C
VDD = +15V
VSS = –15V
300
–20
VDD = +12V, VSS = 0V
250
–30
VDD = +36V, VSS = 0V
–40
TIME (ns)
CROSSTALK (dB)
0
VS (V)
Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply
–10
VDD = 12V
VSS = 0V
VDD = +15V
VSS = –15V
100
09203-021
0
–50
–60
200
VDD = +15V, VSS = –15V
150
VDD = +20V, VSS = –20V
–70
100
–80
100k
1M
10M
100M
1G
FREQUENCY (Hz)
0
–40
09203-016
–10
–30
ACPSRR (dB)
–20
–1.5
–2.0
–2.5
–3.0
40
60
80
100
120
TA = 25°C
VDD = +15V
VSS = –15V
NO DECOUPLING
CAPACITORS
–40
–50
DECOUPLING
CAPACITORS
–60
–3.5
–70
–4.0
–80
–90
–4.5
10k
100k
1M
10M
100M
FREQUENCY (Hz)
09203-020
INSERTION LOSS (dB)
0
–1.0
–5.0
1k
20
Figure 20. Transition Time vs. Temperature
TA = 25°C
VDD = +15V
VSS = –15V
–0.5
0
TEMPERATURE (°C)
Figure 17. Crosstalk vs. Frequency, ±15 V Dual Supply
0
–20
–100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply
Figure 18. On Response vs. Frequency, ±15 V Dual Supply
Rev. 0 | Page 12 of 20
10M
09203-017
–100
10k
09203-022
50
–90
ADG5404
0.10
LOAD = 1kΩ
TA = 25°C
0.09
VDD = 12V, VSS = 0V, VS = 6V p-p
0.08
0.06
0.05
0.04
VDD = 36V, VSS = 0V, VS = 18V p-p
0.03
0.02
VDD = 15V, VSS = 15V, VS = 15V p-p
0.01
0
VDD = 20V, VSS = 20V, VS = 20V p-p
0
5
10
15
FREQUENCY (MHz)
20
09203-018
THD + N (%)
0.07
Figure 22. THD + N vs. Frequency, ±15 V Dual Supply
Rev. 0 | Page 13 of 20
ADG5404
TEST CIRCUITS
VSS
VDD
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
50Ω
Sx
50Ω
VS
V
Sx
D
D
RL
50Ω
GND
VOUT
OFF ISOLATION = 20 log
Figure 23. On Resistance
09203-008
09203-005
IDS
VS
VOUT
VS
Figure 26. Off Isolation
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
50Ω
Sx
VS
D
GND
A
VS
VD
INSERTION LOSS = 20 log
Figure 24. Off Leakage
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 27. Bandwidth
VDD
VSS
0.1µF
NETWORK
ANALYZER
VOUT
0.1µF
VDD
S1
VSS
RL
50Ω
D
S2
VS
D
NC = NO CONNECT
A
VD
09203-007
Sx
RL
50Ω
GND
ID (ON)
NC
09203-009
D
VOUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
Figure 28. Channel-to-Channel Crosstalk
Figure 25. On Leakage
Rev. 0 | Page 14 of 20
09203-010
Sx
A
RL
50Ω
ID (OFF)
09203-006
IS (OFF)
ADG5404
VDD
VSS
0.1µF
0.1µF
AUDIO PRECISION
VDD
VSS
RS
Sx
IN
VS
V p-p
D
VIN
VOUT
RL
1kΩ
09203-011
GND
Figure 29. THD + Noise
VDD VSS
0.1µF
ADDRESS
DRIVE (VIN)
VDD VSS
S1
A1
S2
A0
S3
S4
VIN
2.4V
EN
VS1
VS4
3V
50%
50%
0V
90%
VOUT
90%
VOUT
D
GND
tTRANSITION
CL
35pF
RL
300Ω
tTRANSITION
09203-012
0.1µF
Figure 30. Address to Output Switching Times
VIN
300Ω
2.4V
VDD VSS
0.1µF
VDD VSS
S1
S2
S3
S4
EN
VOUT
D
GND
ADDRESS
DRIVE (VIN)
VS1
A1
A0
RL
300Ω
CL
35pF
0V
VOUT
Figure 31. Break-Before-Make Time Delay
Rev. 0 | Page 15 of 20
3V
80%
80%
tBBM
09203-013
0.1µF
ADG5404
VDD VSS
0.1µF
VDD VSS
S1
A1
S2
A0
S3
S4
EN
GND
VS
3V
50%
VOUT
0.9VOUT
OUTPUT
VOUT
D
RL
300Ω
300Ω
50%
0V
0.9VOUT
0V
CL
35pF
tON (EN)
tOFF (EN)
Figure 32. Enable-to-Output Switching Delay
VDD
VSS
VDD
VSS
Sx
D
VOUT
RS
VOUT
VIN
CL
1nF
VS
∆VOUT
QINJ = CL × ∆VOUT
SW OFF
SW OFF
SW ON
DECODER
GND
VIN
A1 A2
SW OFF
SW OFF
09203-015
VIN
ENABLE
DRIVE (VIN)
09203-014
0.1µF
EN
Figure 33. Charge Injection
Rev. 0 | Page 16 of 20
ADG5404
TERMINOLOGY
IDD
The positive supply current.
CIN
The digital input capacitance.
ISS
The negative supply current.
tTRANSITION
The delay time between the 50% and 90% points of the digital
input and switch-on condition when switching from one
address state to another.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between Terminal D and Terminal S.
RFLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range.
tON (EN)
The delay between applying the digital control input and the
output switching on. See Figure 32.
tOFF (EN)
The delay between applying the digital control input and the
output switching off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID, IS (On)
The channel leakage current with the switch on.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
VINL
The maximum input voltage for Logic 0.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
VINH
The minimum input voltage for Logic 1.
On Response
The frequency response of the on switch.
IINL (IINH)
The input current of the digital input.
Insertion Loss
The loss due to the on resistance of the switch.
CS (Off)
The off switch source capacitance, which is measured with
reference to ground.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
CD (Off)
The off switch drain capacitance, which is measured with
reference to ground.
CD, CS (On)
The on switch capacitance, which is measured with reference to
ground.
ACPSRR (AC Power Supply Rejection Ratio)
The ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the part’s
ability to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
Rev. 0 | Page 17 of 20
ADG5404
TRENCH ISOLATION
In the ADG5404, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction-isolated switches, are eliminated, and the result is a
completely latch-up proof switch.
PMOS
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 34. Trench Isolation
Rev. 0 | Page 18 of 20
09203-004
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
NMOS
ADG5404
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5404 high voltage multiplexer allows
single-supply operation from 9 V to 40 V and dual-supply
operation from ±9 V to ±22 V. The ADG5404, as well as three
other ADG54xx family members, ADG5412/ADG5413 and
ADG5436, achieve an 8 kV human body model ESD rating that
provides a robust solution and eliminates the need for separate
protection circuitry designs in some applications.
Rev. 0 | Page 19 of 20
ADG5404
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
061908-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 35. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
16
13
PIN 1
INDICATOR
12
1
EXPOSED
PAD
4
2.70
2.60 SQ
2.50
9
0.80
0.75
0.70
0.45
0.40
0.35
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
012909-B
TOP VIEW
8
Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG5404BRUZ
ADG5404BRUZ-REEL7
ADG5404BCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09203-0-7/10(0)
Rev. 0 | Page 20 of 20
Package Option
RU-14
RU-14
CP-16-17