Revised February 1999 MM74HCT138 3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits feature high noise immunity and low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. The MM74HCT138 have 3 binary select inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading decoders. Features The decoders’ output can drive 10 low power Schottky TTL equivalent loads and are functionally and pin equivalent to ■ Low input current: 1 µA maximum ■ TTL input compatible ■ Typical propagation delay: 20 ns ■ Low quiescent current: 80 µA maximum (74HCT Series) ■ Fanout of 10 LS-TTL loads Ordering Code: Order Number MM74HCT138M MM74HCT138SJ MM74HCT138MTC MM74HCT138N Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP © 1999 Fairchild Semiconductor Corporation DS005362.prf www.fairchildsemi.com MM74HCT138 3-to-8 Line Decoder February 1984 MM74HCT138 Truth Table Inputs Outputs Enable Select G1 G2 (Note 1) C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X H H H H H H H H L X X X X H H H H H H H H H L L L L L H H H H H H H H L L L H H L H H H H H H H L L H L H H L H H H H H H L L H H H H H L H H H H H L H L L H H H H L H H H H L H L H H H H H H L H H H L H H L H H H H H H L H H L H H H H H H H H H H L H = HIGH Level L = LOW Level X = Don’t Care Note 1: G2 = G2A + G2B Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA Supply Voltage (VCC) (VIN, VOUT) Operating Temperature Range (TA) 600 mW 500 mW 0 VCC V −40 +85 °C 500 ns Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 3: Unless otherwise specified all voltages are referenced to ground. Note 4: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. Lead Temperature (TL) (Soldering 10 seconds) V (tr, tf) Power Dissipation (PD) S.O. Package only Units 5.5 Input Rise or Fall Times −65°C to +150°C (Note 4) Max 4.5 DC Input or Output Voltage ±50 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Min 260°C DC Electrical Characteristics VCC = 5V ±10% (unless otherwise specified) Symbol VIH Parameter TA = 25°C Conditions Typ Minimum HIGH Level TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units 2.0 2.0 2.0 V 0.8 0.8 0.8 V Input Voltage VIL Maximum LOW Level Input Voltage VOH VOL IIN ICC Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| = 20 µA VCC VCC− 0.1 VCC− 0.1 VCC− 0.1 V |IOUT| = 4.0 mA, VCC = 4.5V 4.2 3.98 3.84 3.7 V |IOUT| = 4.8 mA, VCC = 5.5V 5.2 4.98 4.84 4.7 V Maximum LOW Level VIN = VIH or VIL Voltage |IOUT| = 20 µA Maximum Input 0 0.1 0.1 0.1 V |IOUT| = 4.0 mA, VCC = 4.5V 0.2 0.26 0.33 0.4 V |IOUT| = 4.8 mA, VCC = 5.5V 0.2 0.26 0.33 0.4 V ±0.1 ±1.0 ±1.0 µA 8.0 80 160 µA 0.3 0.4 0.5 mA VIN = VCC or GND, Current VIH or VIL Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA VIN = 2.4V or 0.5V (Note 5) Note 5: This is measured per input pin. All other inputs are held at VCC or ground. 3 www.fairchildsemi.com MM74HCT138 Absolute Maximum Ratings(Note 2) (Note 3) MM74HCT138 AC Electrical Characteristics TA = 25°C, VCC = 5.0V, tr = tf = 6 ns, CL = 15 pF (unless otherwise specified) Symbol Parameter Conditions Typ Guaranteed Limit Units tPHL Maximum Propagation Delay, A, B, or C to Output 20 35 ns tPLH Maximum Propagation Delay, A, B, or C to Output 13 25 ns tPHL Maximum Propagation Delay, G1 to Y Output 14 25 ns tPLH Maximum Propagation Delay, G1 to Y Output 13 25 ns tPHL Maximum Propagation Delay, G2A or G2B to Y Output 17 30 ns tPLH Maximum Propagation Delay, G2A or G2B to Y Output 13 25 ns AC Electrical Characteristics VCC = 5V ± 10%, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol tPHL Parameter TA = 25°C Conditions Typ Maximum Propagation Delay TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units 24 40 50 60 ns 18 30 38 45 ns 17 30 38 45 ns 20 30 38 45 ns 23 35 43 52 ns 18 30 38 45 ns 15 19 22 ns 5 10 10 A, B, or C to Output tPLH Maximum Propagation Delay A, B, or C to Output tPHL Maximum Propagation Delay G1 to Y Output tPLH Maximum Propagation Delay G1 to Y Output tPHL Maximum Propagation Delay G2A or G2B to Y Output tPLH Maximum Propagation Delay G2A or G2B to Y Output tTHL, tTLH Maximum Output Rise and Fall Time CIN Input Capacitance CPD Power Dissipation Capacitance 55 (Note 6) Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.fairchildsemi.com 4 pF pF MM74HCT138 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com MM74HCT138 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HCT138 3-to-8 Line Decoder Physical Dimensions inches (millimeters) unless otherwise noted (Continued)