HI2325 TM Data Sheet March 2000 3.3V Dual 8-Bit, 40MSPS A/D Converter with Internal Reference and Digital Clamp The HI2325 is a monolithic, dual 8-bit, 40MSPS analog-todigital converter fabricated in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. The HI2325 features a 2-stage parallel architecture. Only one external clock is necessary to drive both converters and an internal voltage reference is provided allowing the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. The HI2325 has excellent dynamic performance while consuming less than 100mW power at 40MSPS. The A/D only requires a single +3.3V power supply and encode clock. Data output latches are provided which present valid data to the output bus with a latency of 2 clock cycles. Features • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS • 6.5 Bits at fIN = 1MHz • Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW • Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 8mW • Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz • Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB • Internal Digital Clamp • Internal Voltage Reference • Single Supply Voltage Operation . . . . . . . . . . . . . . . +3.3V • TTL/CMOS Compatible Digital Inputs • CMOS Compatible Digital Outputs . . . . . . . . . . . . . . . 3.3V • Dual 8-Bit A/D Converters on a Monolithic Chip TEMP. RANGE (oC) PACKAGE -20 to 85 48 Ld MQFP/PQFP HI2325IN 4823.1 • Offset Binary or 2’s Complement Output Format Ordering Information PART NUMBER File Number PKG. NO. Q48.7x7-S Pinout Applications • Wireless Local Loop • PSK and QAM I&Q Demodulators • Medical Imaging and Instrumentation ARB STB • Portable Communications AVDD ARBS CLE SEL CLP A0 DVSS CLK A2 A1 48 LEAD LQFP TOP VIEW • Power Metering • Hand-Held Data Collection Instruments A3 1 48 47 46 45 44 43 42 41 40 39 38 37 36 A4 2 3 35 34 AIO 4 33 A7 DVDD DVDD 5 32 31 AVDD ART ARTS B0 8 9 1 BRTS BRT AVDD 27 BIN 26 BIO AVSS BRB BRBS TEST AVSS REF1 REF2 2S/B AIN 28 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 REF0 B4 10 B7 DVSS B3 30 29 B6 B1 B2 6 7 B5 A5 A6 AVSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HI2325 AVSS BIO BIN AVDD BRITS BRT ARTS ART AVDD AIO AIN AVSS Functional Block Diagram 36 35 34 33 32 31 30 29 28 27 26 25 24 BRB ARB 37 23 BRBS ARBS 38 A-CH 8-BIT ADC AND CLAMP DAC AVDD 39 STB 40 SEL 41 B-CH 8-BIT ADC AND CLAMP DAC 22 AVSS 21 TEST 20 REF2 19 REF1 CLE 42 18 REF0 CLP 43 8 CLK 44 8 17 2S/B 9 9 16 DVSS DVSS 45 15 B7 A0 46 CLAMP AND LATCH AND TEST A1 47 14 B6 2 4 5 6 7 8 9 A5 A6 A7 DVDD DVDD B0 B1 10 11 12 B4 3 B3 2 B2 1 A4 13 B5 A3 A2 48 HI2325 Pin Descriptions PIN NO. SYMBOL I/O EQUIVALENT CIRCUIT DESCRIPTION 46, 47, 48, 1- 5 A0 - A7 O Digital Output. A0(LSB) - A7(MSB) 8 - 15 B0 - B7 O Digital Output. B0(LSB) - B7(MSB) 6, 7 DVDD Digital power supply. 16 DVSS Digital ground. 17 2S/B I Pull-down resistors are incorporated. Selects output code. H: 2’s Compliment Code L: Binary Code 18, 19, 20 REF0 ~ 2 I Pull-down resistors are incorporated. Determines the clamp circuit reference data. See the table “Digital Clamp Reference Level”. 21 TEST I Pull-down resistors are incorporated. Normally open. 22, 25 DVSS Digital ground. 22, 25, 36 AVSS Analog ground. 23 38 BRBS ARBS Shorting these pins to AVSS generates voltage of about 0.5V at the BRB and ARB pins. 24 37 BRB ARB Reference voltage (bottom). 29 32 BRT ART Reference voltage (top). 30 31 BRTS ARTS 26 35 BIO AIO O Analog output. The digital clamp circuit comprises a D/A converter whose outputs are available on these pins. 27 34 BIN AIN I Analog input. 28, 33, 39 AVDD 40 STB I Pull-down resistors are incorporated. Stand-by input. H: Stand-by mode L: Operation mode. 41 SEL I Pull-down resistors are incorporated. Controls the CLP signal polarity. H: CLP is High active L: CLP is Low active. 42 CLE I Pull-down resistors are incorporated. Clamp enable input. H: Enable L: Disable. 43 CLP I Pull-down resistors are incorporated. Clamp pulse input. The polarity can be set to either High or Low by setting SEL. 44 CLK I Pull-down resistors are incorporated. Clock input. Shorting these pins to AVDD generates voltage of about 2.5V at the BRT and ART pins. Analog power supply. 3 HI2325 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .4V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) 48 Ld MQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Temperature Range HI2325IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = DVDD = +3.3V; VIN = 1.50V; fS = 40MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ACCURACY Resolution 8 - - Bits Integral Linearity Error, INL fIN = 1MHz - 0.2 - LSB Differential Linearity Error, DNL (Guaranteed No Missing Codes) fIN = 1MHz - ±0.7 - LSB Offset Error, VOS fIN = DC -50 - 50 mV Full Scale Error, FSE fIN = DC - 1 - LSB DYNAMIC CHARACTERISTICS Minimum Conversion Rate No Missing Codes 1 - - MSPS Maximum Conversion Rate No Missing Codes 40 - - MSPS Effective Number of Bits, ENOB fIN = 1MHz - 6.5 - Bits Signal to Noise and Distortion Ratio, SINAD RMS Signal = -------------------------------------------------------------RMS Noise + Distortion fIN = 1MHz - 41 - dB Signal to Noise Ratio, SNR RMS Signal = ------------------------------RMS Noise fIN = 1MHz - 42.5 - dB Total Harmonic Distortion, THD fIN = 1MHz - -46 - dBc 2nd Harmonic Distortion fIN = 1MHz - -48 - dBc 3rd Harmonic Distortion fIN = 1MHz - -52 - dBc Spurious Free Dynamic Range, SFDR fIN = 1MHz - 48.5 - dBc Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - - - dBc I/Q Channel Crosstalk - -75 - dBc I/Q Channel Offset Match - 1.0 - LSB I/Q Channel Full Scale Error Match - 0.25 - LSB Transient Response (Note 2) - 1 - Cycle Over-Voltage Recovery 0.2V Overdrive (Note 2) - 1 - Cycle - 1.0 - V ANALOG INPUT Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RINA or RINB VINA, VINB = VREF, DC - - - MΩ Analog Input Capacitance, CINA or CINB VINA, VINB = 1.5V, DC - - - pF 4 HI2325 Electrical Specifications AVDD = DVDD = +3.3V; VIN = 1.50V; fS = 40MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Unless Otherwise Specified (Continued) MIN TYP MAX UNITS Analog Input Bias Current, IBA or IBB PARAMETER VINA/VINB = ART/BRT, ARB/BRB, DC (Notes 2, 3) TEST CONDITIONS - - - µA Full Power Input Bandwidth, FPBW fS = 40MHz, (Note 2) - - - MHz Reference Voltage Input Range - - - V Total Reference Resistance, RRIN - 370 - kΩ mA REFERENCE VOLTAGE INPUT Reference Current, IRIN - 5.4 - VRB - 0.54 - VRT - 1.9 - Input Logic High Voltage, VIH CLK 2.0 - - V Input Logic Low Voltage, VIL CLK - - 0.8 V Input Logic High Current, IIH CLK, VIH = 3.3V - - - µA Input Logic Low Current, IIL CLK, VIL = 0V - - - µA Input Capacitance, CIN CLK - - - pF Output Logic High Voltage, VOH IOH = 100µA; DVDD = 3.3V - - - V Output Logic Low Voltage, VOL IOL = 1.5mA; DVDD = 3.3V - - - V Output Logic High Voltage, VOH IOH = 100µA; DVDD = 3.0V - - - V Output Logic Low Voltage, VOL IOL = 100µA; DVDD = 3.0V - - - V - - - pF Aperture Delay, tAP - 4 - ns Aperture Jitter, tAJ - 5 - psRMS Data Output Hold, tH - 10.7 - ns Data Output Delay, tOD - 11.7 - ns Self Bias SAMPLING CLOCK INPUT DIGITAL OUTPUTS Output Capacitance, COUT TIMING CHARACTERISTICS Data Latency, t LAT For a Valid Sample (Note 2) 2 2 2 Cycles Power-Up Initialization Data Invalid Time (Note 2) - - - Cycles Sample Clock Pulse Width (Low) (Note 2) 11.25 12.5 - ns Sample Clock Pulse Width (High) (Note 2) 11.25 12.5 - ns - ±5 - % Sample Clock Duty Cycle Variation POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVDD (Note 2) 3.0 3.3 3.6 V Digital Supply Voltage, DVDD (Note 2) 3.0 3.3 3.6 V Supply Current, IDD fS = 40MSPS - 30.3 - mA - 100 - mW Power Dissipation Offset Error Sensitivity, ∆VOS A VDD or DVDD = 3.3V ±5% - ±0.125 - LSB Gain Error Sensitivity, ∆FSE A VDD or DVDD = 3.3V ±5% - ±0.15 - LSB NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. 5 HI2325 TABLE 1. OUTPUT MODE INPUT OUTPUT A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 TEST STB 2S/B L L L Binary Code L L H 2’s Compliment Code L H X Hi-Z H X X Test Mode A2 B2 A1 B1 A0 B0 TABLE 2. DIGITAL OUTPUT The following table shows the relationship between analog input voltage and digital output code. DIGITAL OUTPUT CODE BINARY CODE 2’s COMPLIMENT CODE INPUT SIGNAL VOLTAGE STEP VART, VBRT 255 11111111 011111111 : : : : : 128 10000000 00000000 : 127 01111111 11111111 : : : : VARB, VBRB 0 00000000 10000000 MSB LSB MSB LSB TABLE 3. DIGITAL CLAMP REFERENCE LEVEL SETTING REFERENCE LEVEL REF2 REF1 REF0 MODE DECIMAL BINARY 2’s COMPLIMENT L L L 0 1 00000001 10000001 L L H 1 16 00010000 10010000 L H L 2 32 00100000 10100000 L H H 3 128 10000000 00000000 H L L 4 254 11111110 01111110 H L H 5 239 11101111 01101111 H H L 6 223 11011111 01011111 H H H 7 127 01111111 11111111 6 HI2325 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) D Q48.7x7-S D1 48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES E E1 e MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.056 0.066 1.40 1.70 - A1 0.000 0.007 0.00 0.20 - B 0.006 0.010 0.15 0.26 5 D 0.347 0.362 8.80 9.20 2 D1 0.272 0.279 6.90 7.10 3, 4 E 0.347 0.362 8.80 9.20 2 E1 0.272 0.279 6.90 7.10 3, 4 L 0.012 0.027 0.30 0.70 N 48 48 e 0.020 BSC 0.500 BSC 6 Rev. 1 4/95 PIN 1 NOTES: -H- SEATING PLANE A 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 0.10 0.004 -C- 0.24 M B 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. “N” is the number of terminal positions. A1 0o-10o L 0.107/0.177 0.004/0.007 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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