ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS87931I is a low voltage, low skew LVCMOS/LVTTL Clock Multiplier/Zero Delay HiPerClockS™ Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. With output frequencies up to 150MHz, the ICS87931I is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87931I contains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”. • Fully integrated PLL ,&6 • 6 LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock for redundant clock applications • Maximum output frequency: 150MHz • VCO range: 220MHz to 480MHz • External feedback for “zero delay” clock regeneration • Output skew, Same Frequency: 300ps (maximum) Selectable clock inputs, CLK1 and differential CLK0, nCLK0 support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A, B and C are controlled by the DIV_SELA, DIV_SELB and DIV_SELC, respectively. • Output skew, Different Frequency: 400ps (maximum) • Cycle-to-cycle jitter: 100ps (maximum) • 3.3V supply voltage • -40°C to 85°C ambient operating temperature For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When LOW, the nMR input resets the internal dividers and forces the outputs to the high impedance state. • Pin compatible with MPC931 PIN ASSIGNMENT GND QA1 QA0 VDDO DIV_SELA DIV_SELB DIV_SELC nc The effective fanout of the ICS87931I can be increased to 12 by utilizing the ability of each output to drive two series terminated transmission lines. 32 31 30 29 28 27 26 25 nc 1 24 GND VDDA 2 23 QB0 POWER_DN 3 22 QB1 CLK1 4 21 VDDO nMR 5 20 EXTFB_SEL CLK0 6 19 CLK_SEL nCLK0 7 18 PLL_SEL GND 8 17 nc BLOCK DIAGRAM GND QC1 QC0 VDDO EXTFB_SEL Pulldown EXT_FB Pullup 0 1 0 EXT_FB nCLK0 None CLK_EN1 CLK_SEL Pulldown CLK1 Pullup CLK_EN0 nc PLL_SEL Pullup Pullup 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View 9 10 11 12 13 14 15 16 POWER_DN Pullup CLK0 ICS87931I 0 PHASE DETECTOR 1 VCO ÷2 ÷2/÷4 QA1 LPF 1 ÷2/÷4 ÷8 0 QA0 1 QB0 QB1 DIV_SELA Pulldown DIV_SELB Pulldown ÷4/÷6 CLK_EN0 Pullup DISABLE LOGIC CLK_EN1 Pullup DIV_SELC Pulldown nMR Pullup 87931BYI QC0 QC1 POWER-ON RESET www.icst.com/products/hiperclocks.html 1 REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 9, 17, 32 nc Unused 2 VDDA Power 3 POWER_DN Input Pullup 4 CLK1 Input Pullup 5 nMR Input Pullup 6 CLK0 Input 7 nCLK0 Input 8, 16, 24,25 GND CLK_EN0, CLK_EN1 Power 12 EXT_FB Input 13, 21, 28 VDDO Power 14, 15 QC0, QC1 Output 18 PLL_SEL Input 19 CLK_SEL Input 20 EXTFB_SEL Input 22, 23 QB1, QB0 Output 26, 27 QA1, QA0 Output 29 DIV_SELA Input 30 DIV_SELB Input 31 DIV_SELC Input 10, 11 Type Input Description No connect. Analog supply pin. Controls the frequency being fed to the output dividers. LVCMOS / LVTTL interface levels. Clock input. LVCMOS / LVTTL interface levels. Active LOW Master reset. When logic LOW, the internal dividers are reset causing the outputs to go low. When logic HIGH, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Pullup Pullup/ Inver ting differential clock input. VCC/2 default when left floating. Pulldown Power supply ground. Controls the enabling and disabling of the clock outputs. See Table 3B. Pullup LVCMOS / LVTTL interface levels. External feedback. When LOW, selects internal feedback. Pullup When HIGH, selects EXT_FB. LVCMOS / LVTTL interface levels. Output supply pins. Bank C clock outputs.7Ω typical output impedance. LVCMOS / LVTTL interface levels. Selects between the PLL and reference clocks as the input to the Pullup output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL. LVCMOS / LVTTL interface levels. Clock select input. Selects the Phase Detector Reference. Pulldown When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Pulldown External feedback select. LVCMOS / LVTTL interface levels. Bank B clock outputs.7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank A clock outputs.7Ω typical output impedance. LVCMOS / LVTTL interface levels. Determines output divider values for Bank A as described in Table 4A. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank B as described in Table 4A. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank C as described in Table 4A. Pulldown LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 KΩ 12 pF 7 Ω CPD ROUT 87931BYI VDDA, VDDO = 3.465V www.icst.com/products/hiperclocks.html 2 REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Function Control Pin Logic 0 Logic 1 CLK_SEL CLK0, nCLK0 CLK1 PLL_SEL Bypass PLL PLL Enabled EXTFB_SEL Internal Feedback EXT_FB POWER_DN VCO/1 VCO/2 nMR Master Reset/Output Hi Z Enable Outputs DIV_SELA:DIV_SELC QA(÷2); QB(÷2); QC(÷4) QA(÷4); QB(÷4); QC(÷6) TABLE 3B. CLK_ENX FUNCTION TABLE Inputs CLK_EN1 CLK_EN0 0 0 1 0 1 1 DIV_SELA:DIVSELC QAx QBx QCx 0 Toggle LOW LOW 1 LOW LOW Toggle Toggle LOW Toggle Toggle Toggle Toggle TABLE 4A. VCO FREQUENCY FUNCTION TABLE Inputs Outputs QAx QBx QCx DIV_ SELA DIV_ SELB DIV_ SELC POWER_DN = 0 0 0 0 VCO/2 VCO/4 VCO/2 VCO/4 VCO/4 VCO/8 0 0 1 VCO/2 VCO/4 VCO/2 VCO/4 VCO/6 VCO/12 0 1 0 VCO/2 VCO/4 VCO/4 VCO/8 VCO/4 VCO/8 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1 0 1 1 VCO/2 VCO/4 VCO/4 VCO/8 VCO/6 VCO/12 1 0 0 VCO/4 VCO/8 VCO/2 VCO/4 VCO/4 VCO/8 1 0 1 VCO/4 VCO/8 VCO/2 VCO/4 VCO/6 VCO/12 1 1 0 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 1 1 1 VCO/4 VCO/8 VCO/4 VCO/8 VCO/6 VCO/12 TABLE 4B. INPUT REFERENCE FREQUENCY TO OUTPUT FREQUENCY FUNCTION TABLE (INTERNAL FEEDBACK ONLY) Inputs Outputs QAx QBx QCx DIV_ SELA DIV_ SELB DIV_ SELC POWER_DN = 0 0 0 0 4x 2x 4x 2x 2x x 0 0 1 4x 2x 4x 2x 4/3x 2/3x 0 1 0 4x 2x 2x x 2x x POWER_DN = 1 POWER_DN = 0 POWER_DN = 1 POWER_DN = 0 POWER_DN = 1 0 1 1 4x 2x 2x x 4/3x 2/3x 1 0 0 2x x 4x 2x 2x x 1 0 1 2x x 4x 2x 4/3x 2/3x 1 1 0 2x x 2x x 2x x 1 1 1 2x x 2x x 4/3x 2/3x 87931BYI www.icst.com/products/hiperclocks.html 3 REV. A JUNE 23, 2003 Integrated Circuit Systems, Inc. ICS87931I LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER VCO VCO/2 POWER_DN QA(÷2) QB(÷4) QC(÷6) FIGURE 1A. POWER_DN TIMING DIAGRAM QA QB QC CLK_EN0 CLK_EN1 QA(÷2) QB(÷4) QC(÷6) CLK_EN0 CLK_EN1 FIGURE 1B. CLK_ENX TIMING DIAGRAMS 87931BYI www.icst.com/products/hiperclocks.html 4 REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDDA + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VDDA Test Conditions Minimum Typical Maximum Units Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 VDDO Output Supply Voltage IDDA Analog Supply Current 20 mA V IDDO Output Supply Current 100 mA TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIN Input Current Test Conditions DIV_SELA:DIV_SELC, CLK_EN0, CLK_EN1, POWER_DN, nMR, CLK_SEL, PLL_SEL, EXTFB_SEL CLK1, EXT_FB DIV_SELA:DIV_SELC, CLK_EN0, CLK_EN1, POWER_DN, nMR, CLK_SEL, PLL_SEL, EXTFB_SEL CLK1, EXT_FB Minimum Typical Maximum Units 2 VDD + 0.3 V 2 VDD + 0.3 V -0.3 0.8 V -0.3 VOH Output High Voltage; NOTE 1 IOH = -20mA VOL Output Low Voltage; NOTE 1 IOL = 20mA 1.3 V ±120 µA 2.4 V 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, 3.3V Output Load Test Circuit. TABLE 5C. DIFFERENTIAL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter IIN Input Current Test Conditions Minimum Typical Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDDA + 0.3V. NOTE 2: Common mode voltage is defined as VIH. VPP 87931BYI www.icst.com/products/hiperclocks.html 5 Maximum Units ±120 µA 1.3 V VDD - 0.85 V REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Input Reference Frequency fREF NOTE: Input reference frequency is limited by the divider selection and the VCO lock range. Test Conditions Minimum Typical Maximum Units 150 MHz Maximum Units TABLE 7. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol fMAX Parameter Output Frequency Test Conditions Minimum Typical QAx, QBx ÷2 150 MHz QAx, QBx, QCx ÷4 120 MHz QCx ÷6 80 MHz CLK1 to EXT_FB tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 -375 -200 -50 ps -100 50 200 ps Same Frequency 300 ps Different Frequency 400 ps fref = 50MHz, FB = ÷ 8 CLK0, nCLK0 to EXT_FB tjitter(cc) Cycle-to-Cycle Jitter ; NOTE 4 fVCO PLL VCO Lock Range tR/tF Output Rise Time; NOTE 3 odc Output Duty Cycle tLOCK PLL Lock Time tPZL, tPZH Output Enable Time; NOTE 3 0.8V to 2.0V 100 ps 220 480 MHz 0.1 1 ns 45 55 % 10 ms 10 ns 8 ns 2 Output Disable Time; NOTE 3 2 tPLZ, tPHZ All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 87931BYI www.icst.com/products/hiperclocks.html 6 REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION VDDA, VDDO = 1.65V±5% VDDA SCOPE nCLK0 Qx LVCMOS V V Cross Points PP CMR CLK0 GND GND = -1.165V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL V V DDO V DDO V DDO 2 DDO 2 tcycle ➤ QAx, QBx, QCx 2 n ➤ Qx ➤ 2 tcycle n+1 ➤ V DDO 2 tsk(o) Qy t jit(cc) = tcycle n –tcycle n+1 1000 Cycles OUTPUT SKEW CYCLE-TO-CYCLE JITTER 2V 2V 0.8V 0.8V Clock Outputs t t R CLK1 VDD 2 F nCLK0 CLK0 OUTPUT RISE/FALL TIME EXT_FB V DDO VDDO 2 2 QAx, QBx, QCx Pulse Width t odc = odc & tPERIOD 87931BYI PERIOD t PW t PERIOD PROPAGATION DELAY www.icst.com/products/hiperclocks.html 7 REV. A JUNE 23, 2003 Integrated Circuit Systems, Inc. ICS87931I LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 87931BYI www.icst.com/products/hiperclocks.html 8 REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Receiv er R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 87931BYI nCLK Zo = 50 Ohm FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY www.icst.com/products/hiperclocks.html 9 BY REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER SCHEMATIC EXAMPLE Figure 4A shows a schematic example of using an ICS87931I. It is recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as pos- sible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VDDA pin as possible. R1 DIV_SELC DIV_SELB DIV_SELA VDD R7 10 - 15 43 Zo = 50 VDD Receiv er 32 31 30 29 28 27 26 25 C11 0.01u POWER_DN Zo = 50 Ohm Zo = 50 Ohm 1 2 3 4 5 6 7 8 nc VDDA POWER_DN CLK1 nMR CLK0 nCLK0 GND 3.3V PECL Driv er R8 50 R9 50 ICS87931I GND QB0 QB1 VDDO EXTFB_SEL CLK_SEL PLL_SEL nc nc CLK_EN0 CLK_EN1 EXT_FB VDDO QC0 QC1 GND 3.3V 24 23 22 21 20 19 18 17 R3 1K R4 1K R5 1K 9 10 11 12 13 14 15 16 C16 10u VDD nc DIV_SELC DIV_SELB DIV_SELA VDDO QA0 QA1 GND U1 Set Logic Input to ’1’ VDD RU1 1K Set Logic Input to ’0’ VDD R10 50 CLK_EN0 CLK_EN1 Logic Input Pin Examples Zo = 50 R2 43 RU2 Not Install To Logic Input pins RD1 Not Install Receiv er To Logic Input pins RD2 1K (U1-13) VDD C1 0.1uF VDD=3.3V (U1-21) C2 0.1uF (U1-28) C3 0.1uF SP = Space (i.e. not intstalled) FIGURE 4A. ICS87931I SCHEMATIC EXAMPLE 87931BYI www.icst.com/products/hiperclocks.html 10 REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER The following component footprints are used in this layout example: trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. All the resistors and capacitors are size 0603. POWER AND GROUNDING • The differential 50Ω output traces should have same length. Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the • Make sure no other signal traces are routed between the clock trace pair. • The series termination resistors should be located as close to the driver pins as possible. 50 Ohm Trace C3 VCC R1 U1 VIA R7 VCCA GND Pin 1 C11 C16 Other signals C2 R2 C1 50 Ohm Trace FIGURE 4B. PCB BOARD LAYOUT FOR ICS87931I 87931BYI www.icst.com/products/hiperclocks.html 11 REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87931I is: 2942 87931BYI www.icst.com/products/hiperclocks.html 12 REV. A JUNE 23, 2003 ICS87931I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 87931BYI www.icst.com/products/hiperclocks.html 13 REV. A JUNE 23, 2003 Integrated Circuit Systems, Inc. ICS87931I LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS87931BYI ICS87931BYIT ICS87931BI 32 Lead LQFP 250 per tray -40°C to 85°C ICS87931BI 32 Lead LQFP on Tape and Reel 1000 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87931BYI www.icst.com/products/hiperclocks.html 14 REV. A JUNE 23, 2003