Intersil ISL23315UFUZ Single, low voltage digitally controlled potentiometer (xdcpâ ¢) Datasheet

Single, Low Voltage Digitally Controlled Potentiometer
(XDCP™)
ISL23315
Features
The ISL23315 is a volatile, low voltage, low noise, low power, I2C
Bus™, 256 Taps, single digitally controlled potentiometer (DCP),
• 256 resistor taps
which integrates DCP core, wiper switches and control logic on
a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. The potentiometer has an associated
volatile Wiper Register (WR) that can be directly written to and
read by the user. The contents of the WR controls the position
of the wiper. When powered on, the ISL23315’s wiper will
always commence at mid-scale (128 tap position).
The low voltage, low power consumption, and small package
of the ISL23315 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23315 has a VLOGIC
pin allowing down to 1.2V bus operation, independent from the
VCC value. This allows for low logic levels to be connected
directly to the ISL23315 without passing through a voltage
level shifter.
• I2C serial interface
- No additional level translator for low bus supply
- Two address pins allow up to four devices per bus
• Wiper resistance: 70Ω typical @ VCC = 3.3V
• Shutdown Mode - forces the DCP into an end-to-end open
circuit and RW is shorted to RL internally
• Power-on preset to mid-scale (128 tap position)
• Standby current <2.5µA max
• Shutdown current <2µA max
• Power supply
- VCC = 1.7V to 5.5V analog power supply
- VLOGIC = 1.2V to 5.5V I2C bus/logic power supply
• DCP terminal voltage from 0V to VCC
• 10kΩ, 50kΩ or 100kΩ total resistance
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal processing.
• Extended industrial temperature range: -40°C to +125°C
Applications
• Pb-free (RoHS compliant)
• 10 Ld MSOP or 10 Ld µTQFN packages
• Power supply margining
• RF power amplifier bias compensation
• LCD bias compensation
• Laser diode bias compensation
10000
VREF
RESISTANCE (Ω)
8000
6000
ISL23315
-
VREF_M
+
4000
ISL28114
2000
0
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
POSITION, 10k DCP
December 15, 2010
FN7778.0
1
FIGURE 2. VREF ADJUSTMENT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners
ISL23315
Block Diagram
VCC
VLOGIC
SCL
SDA
I/O
BLOCK
A1
LEVEL
SHIFTER
A0
POWER-UP
INTERFACE,
CONTROL
AND
STATUS
LOGIC
RH
WR
VOLATILE
REGISTER
AND
WIPER
CONTROL
CIRCUITRY
RL
RW
GND
Pin Configurations
Pin Descriptions
ISL23315
(10 LD MSOP)
TOP VIEW
MSOP
µTQFN
SYMBOL
DESCRIPTION
1
10
VLOGIC
I2C bus /logic supply. Range 1.2V to
5.5V
VLOGIC
1
10
GND
2
1
SCL
Logic Pin - Serial bus clock input
SCL
2
9
VCC
3
2
SDA
SDA
3
8
RH
Logic Pin - Serial bus data
input/open drain output
A0
4
7
RW
4
3
A0
A1
5
6
RL
Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
5
4
A1
Logic Pin - Hardwire slave address
pin for I2C serial bus.
Range: VLOGIC or GND
6
5
RL
DCP “low” terminal
7
6
RW
DCP wiper terminal
8
7
RH
DCP “high” terminal
9
8
VCC
Analog power supply.
Range 1.7V to 5.5V
10
9
GND
Ground pin
10 VLOGIC
ISL23315
(10 LD µTQFN)
TOP VIEW
SCL
1
9
GND
SDA
2
8
VCC
A0
3
7
RH
6
RW
4
RL 5
A1
2
FN7778.0
December 15, 2010
ISL23315
Ordering Information
PART NUMBER
(Note 5)
ISL23315TFUZ (Notes 1, 3)
PART MARKING
RESISTANCE
OPTION
(kΩ)
TEMP RANGE
(°C)
100
-40 to +125
3315T
PACKAGE
(Pb-free)
10 Ld MSOP
PKG.
DWG. #
M10.118
ISL23315UFUZ (Notes 1, 3)
3315U
50
-40 to +125
10 Ld MSOP
M10.118
ISL23315WFUZ (Notes 1, 3)
3315W
10
-40 to +125
10 Ld MSOP
M10.118
ISL23315TFRUZ-T7A (Notes 2, 4) HB
100
-40 to +125
10 Ld 2.1x1.6 µTQFN
L10.2.1x1.6A
ISL23315TFRUZ-TK (Notes 2, 4)
100
-40 to +125
10 Ld 2.1x1.6 µTQFN
L10.2.1x1.6A
HB
ISL23315UFRUZ-T7A (Notes 2, 4) HA
50
-40 to +125
10 Ld 2.1x1.6 µTQFN
L10.2.1x1.6A
ISL23315UFRUZ-TK (Notes 2, 4)
HA
50
-40 to +125
10 Ld 2.1x1.6 µTQFN
L10.2.1x1.6A
ISL23315WFRUZ-T7A (Notes 2, 4) GZ
10
-40 to +125
10 Ld 2.1x1.6 µTQFN
L10.2.1x1.6A
ISL23315WFRUZ-TK (Notes 2, 4) GZ
10
-40 to +125
10 Ld 2.1x1.6 µTQFN
L10.2.1x1.6A
NOTES:
1. Add “-T*” suffix for Tape and Reel option. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23315. For more information on MSL please see techbrief TB363.
3
FN7778.0
December 15, 2010
ISL23315
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V
Wiper current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .6.5kV
CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Latch Up
(Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld MSOP Package (Notes 6, 7) . . . . . . .
170
70
10 Ld µTQFN Package (Notes 6, 7) . . . . . .
145
90
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V
VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V
DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC
Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
7. For θJC, the “case temp” location is the center top of the package.
Analog Specifications
SYMBOL
RTOTAL
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.
PARAMETER
RH to RL resistance
TEST CONDITIONS
VRH, VRL
RW
TYP
(Note 8)
MAX
(Note 20)
UNITS
W option
10
kΩ
U option
50
kΩ
T option
100
kΩ
RH to RL resistance tolerance
End-to-End Temperature Coefficient
MIN
(Note 20)
-20
±2
+20
%
W option
175
ppm/°C
U option
85
ppm/°C
T option
70
ppm/°C
DCP terminal voltage
VRH or VRL to GND
0
VCC
V
Wiper resistance
RH - floating, VRL = 0V, force IW current
to the wiper,
IW = (VCC - VRL)/RTOTAL,
VCC = 2.7V to 5.5V
70
200
Ω
VCC = 1.7V
580
Ω
22/22/32
pF
CH/CL/CW
Terminal capacitance
See “DCP Macro Model” on page 8
ILkgDCP
Leakage on DCP pins
Voltage at pin from GND to VCC
Noise
Resistor noise density
Wiper at middle point, W option
120
nV Hz
Wiper at middle point, U option
190
nV Hz
Wiper at middle point, T option
220
nV Hz
Digital feed-through from bus to wiper
Wiper at middle point
-65
dB
Power Supply Reject Ratio
Wiper output change if VCC change
±10%; wiper at middle point
-75
dB
Feed Thru
PSRR
4
-0.4
< 0.1
0.4
µA
FN7778.0
December 15, 2010
ISL23315
Analog Specifications
SYMBOL
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
W option
-1.0
±0.5
+1.0
LSB
(Note 9)
U, T option
-0.5
±0.15
+0.5
LSB
(Note 9)
-1
±0.4
+1
LSB
(Note 9)
U, T option
-0.4
±0.1
+0.4
LSB
(Note 9)
W option
-3.5
-2
0
LSB
(Note 9)
U, T option
-2
-0.5
0
LSB
(Note 9)
W option
0
2
3.5
LSB
(Note 9)
U, T option
0
0.4
2
LSB
(Note 9)
PARAMETER
TEST CONDITIONS
UNITS
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL
(Note 13)
DNL
(Note 12)
FSerror
(Note 11)
ZSerror
(Note 10)
Integral non-linearity, guaranteed
monotonic
Differential non-linearity, guaranteed
monotonic
Full-scale error
Zero-scale error
TCV
Ratiometric temperature coefficient
(Notes 14)
fcutoff
W option
W option, Wiper Register set to 80 hex
8
ppm/°C
U option, Wiper Register set to 80 hex
4
ppm/°C
T option, Wiper Register set to 80 hex
2.3
ppm/°C
Large Signal Wiper Settling Time
From code 0 to FF hex
300
ns
-3dB cutoff frequency
Wiper at middle point W option
1200
kHz
Wiper at middle point U option
250
kHz
Wiper at middle point T option
120
kHz
RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)
RINL
(Note 18)
Integral non-linearity, Guaranteed
monotonic
W option; VCC = 2.7V to 5.5V
-2.0
W option; VCC = 1.7V
U, T option; VCC = 2.7V to 5.5V
Differential non-linearity, Guaranteed
monotonic
W option; VCC = 2.7V to 5.5V
-1.0
U, T option; VCC = 1.7V
5
±0.3
-1
±0.4
+1.0
±0.15
±0.35
MI
(Note 15)
MI
(Note 15)
+1
±0.6
-0.5
MI
(Note 15)
MI
(Note 15)
2.1
W option; VCC = 1.7V
U, T option; VCC = 2.7V to 5.5V
+2.0
10.5
U, T option; VCC = 1.7V
RDNL
(Note 17)
±1
MI
(Note 15)
MI
(Note 15)
+0.5
MI
(Note 15)
MI
(Note 15)
FN7778.0
December 15, 2010
ISL23315
Analog Specifications
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
Roffset
(Note 16)
Offset, wiper at 0 position
W option; VCC = 2.7V to 5.5V
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
0
3
5.5
W option; VCC = 1.7V
U, T option; VCC = 2.7V to 5.5V
TCR
(Note 19)
Resistance temperature coefficient
Operating Specifications
SYMBOL
ILOGIC
ICC
ILOGIC SB
ICC SB
0.5
ILkgDig
tDCP
PARAMETER
VLOGIC supply current (write/read)
VCC supply current (write/read)
VLOGIC standby current
VCC standby current
VLOGIC shutdown current
VCC shutdown current
MI
(Note 15)
1.1
MI
(Note 15)
W option; Wiper register set between
32 hex and FF hex
220
ppm/°C
U option; Wiper register set between 32
hex and FF hex
100
ppm/°C
T option; Wiper register set between 32
hex and FF hex
75
ppm/°C
MAX
(Note 20)
UNITS
VLOGIC = 5.5V, VCC = 5.5V,
fSCL = 400 kHz (for I2C active read and
write)
200
µA
VLOGIC = 1.2V, VCC = 1.7V,
fSCL = 400 kHz (for I2C active read and
write)
5
µA
VLOGIC = 5.5V, VCC = 5.5V
18
µA
VLOGIC = 1.2V, VCC = 1.7V
10
µA
VLOGIC = VCC = 5.5V,
I2C interface in standby
1
µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
0.5
µA
VLOGIC = VCC = 5.5V,
I2C interface in standby
1.5
µA
1
µA
VLOGIC = VCC = 5.5V,
I2C interface in standby
1.3
µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
0.4
µA
VLOGIC = VCC = 5.5V,
I2C interface in standby
0.7
µA
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
0.5
µA
0.4
µA
TEST CONDITIONS
Leakage current, at pins A0, A1, SDA,
SCL
Voltage at pin from GND to VLOGIC
Wiper response time
SCL rising edge of the acknowledge bit
after data byte to wiper new position
6
2
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.
SHDN
ICC SHDN
MI
(Note 15)
U, T option; VCC = 1.7V
MIN
(Note 20)
TYP
(Note 8)
VLOGIC = 1.2V, VCC = 1.7V,
I2C interface in standby
ILOGIC
MI
(Note 15)
6.3
0
UNITS
-0.4
<0.1
1.5
µs
FN7778.0
December 15, 2010
ISL23315
Operating Specifications
SYMBOL
tShdnRec
VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise
stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
DCP recall time from shutdown mode
VCC, VLOGIC VCC ,VLOGIC ramp rate
Ramp
(Note 21)
Serial Interface Specification
SYMBOL
MIN
(Note 20)
TEST CONDITIONS
TYP
(Note 8)
UNITS
1.5
SCL rising edge of the acknowledge bit
after ACR data byte to wiper recalled
position and RH connection
Ramp monotonic at any level
MAX
(Note 20)
µs
0.01
50
V/ms
for SCL, SDA, A0, A1 Unless Otherwise Noted.
PARAMETER
TEST CONDITIONS
MIN
(Note 20)
TYP
(Note 8)
MAX
(Note 20)
UNITS
VIL
Input LOW Voltage
-0.3
0.3 x VLOGIC
V
VIH
Input HIGH Voltage
0.7 x VLOGIC
VLOGIC + 0.3
V
Hysteresis
VOL
SDA and SCL Input Buffer
Hysteresis
VLOGIC > 2V
0.05 x VLOGIC
VLOGIC <2V
0.1 x VLOGIC
SDA Output Buffer LOW Voltage
IOL = 3mA, VLOGIC > 2V
V
0
IOL = 1.5mA,
VLOGIC <2V
Cpin
SDA, SCL Pin Capacitance
fSCL
SCL Frequency
tsp
Pulse Width Suppression Time at
SDA and SCL Inputs
tAA
0.4
V
0.2 x VLOGIC
V
10
pF
400
kHz
Any pulse narrower than the
max spec is suppressed
50
ns
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30%
of VLOGIC, until SDA exits the
30% to 70% of VLOGIC window
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VLOGIC
during a STOP condition, to
SDA crossing 70% of VLOGIC
during the following START
condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of
VLOGIC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of
VLOGIC crossing
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling
edge; both crossing 70% of
VLOGIC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge
crossing 30% of VLOGIC to SCL
falling edge crossing 70% of
VLOGIC
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to
70% of VLOGIC window, to SCL
rising edge crossing 30% of
VLOGIC
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
70% of VCC to SDA entering
the 30% to 70% of VCC window
0
ns
7
FN7778.0
December 15, 2010
ISL23315
Serial Interface Specification
SYMBOL
for SCL, SDA, A0, A1 Unless Otherwise Noted. (Continued)
PARAMETER
TEST CONDITIONS
tSU:STO
STOP Condition Set-up Time
tHD:STO
STOP Condition Hold Time for Read From SDA rising edge to SCL
or Write
falling edge; both crossing
70% of VCC (Note 11)
MIN
(Note 20)
From SCL rising edge crossing
70% of VLOGIC, to SDA rising
edge crossing 30% of VLOGIC
TYP
(Note 8)
MAX
(Note 20)
UNITS
600
ns
1300
ns
0
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VLOGIC, until SDA
enters the 30% to 70% of
VLOGIC window.
IOL = 3mA, VLOGIC > 2V.
IOL = 0.5mA, VLOGIC < 2V
tR
SDA and SCL Rise Time
From 30% to 70% of VLOGIC
20 + 0.1 x Cb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VLOGIC
20 + 0.1 x Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
(Note 11)
10
400
pF
tSU:A
A1, A0 setup time
Before START condition
600
ns
tHD:A
A1, A0 hold time
After STOP condition
600
ns
NOTES:
8. Typical values are for TA = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)0/LSB.
11. FS error = [V(RW)255 – VCC]/LSB.
12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255
Max ( V ( RW ) i ) – Min ( V ( RW ) i )
for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
10 6
TC V = ------------------------------------------------------------------------------ × --------------------voltage and Min( ) is the minimum value of the wiper voltage over the temperature range.
V ( RW i ( +25°C ) )
+165°C
15. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00
hex respectively.
14.
16. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW255/MI, when measuring between RW and RH.
17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255.
18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255.
6
for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
[ Max ( Ri ) – Min ( Ri ) ]
10
TC R = ------------------------------------------------------- × --------------------- minimum value of the resistance over the temperature range.
Ri ( +25°C )
+165°C
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
19.
21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible it is recommended to ramp-up the VLOGIC
first followed by the VCC.
DCP Macro Model
RTOTAL
RH
CL
CH
CW
22pF
RL
22pF
32pF
RW
8
FN7778.0
December 15, 2010
ISL23315
Timing Diagrams
SDA vs SCL Timing
tF
tHIGH
SCL
tLOW
tsp
tR
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
A0 and A1 Pin Timing
STOP
START
SCL
CLK 1
SDA
tSU:A
tHD:A
A0, A1
0.4
0.30
0.2
0.15
DNL (LSB)
DNL (LSB)
Typical Performance Curves
0
-0.2
0
-0.15
-0.4
-0.30
0
50
100
150
200
TAP POSITION (DECIMAL)
FIGURE 3. 10k DNL vs TAP POSITION, VCC = 5V
9
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 4. 50k DNL vs TAP POSITION, VCC = 5V
FN7778.0
December 15, 2010
ISL23315
(Continued)
0.4
0.30
0.2
0.15
INL (LSB)
INL (LSB)
Typical Performance Curves
0
0
-0.15
-0.2
-0.30
-0.4
0
50
100
150
200
0
250
50
0.4
0.30
0.2
0.15
RDNL (MI)
RDNL (MI)
150
200
250
FIGURE 6. 50k INL vs TAP POSITION, VCC = 5V
FIGURE 5. 10k INL vs TAP POSITION, VCC = 5V
0
-0.2
-0.4
100
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
0
-0.15
0
50
100
150
200
-0.30
250
0
50
TAP POSITION (DECIMAL)
FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 5V
100
150
TAP POSITION (DECIMAL)
200
250
FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 5V
0.6
0.30
0.4
0.15
RINL (MI)
RINL (MI)
0.2
0
0
-0.2
-0.15
-0.4
-0.6
-0.30
0
50
100
150
200
TAP POSITION (DECIMAL)
FIGURE 9. 10k RINL vs TAP POSITION, VCC = 5V
10
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
FIGURE 10. 50k RINL vs TAP POSITION, VCC = 5V
FN7778.0
December 15, 2010
ISL23315
Typical Performance Curves
(Continued)
60
70
+125°C
+125°C
50
WIPER RESISTANCE (Ω)
WIPER RESISTANCE (Ω)
60
+25°C
50
40
30
20
-40°C
10
50
100
150
TAP POSITION (DECIMAL)
200
30
20
0
250
-40°C
0
100
150
200
250
FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 5V
300
70
250
60
50
TCv (ppm/°C)
200
150
100
40
30
20
50
0
15
50
TAP POSITION (DECIMAL)
FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 5V
TCv (ppm/°C)
40
10
0
0
+25°C
10
65
115
165
0
15
215
65
115
165
215
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 13. 10k TCv vs TAP POSITION
FIGURE 14. 50k TCv vs TAP POSITION
600
200
500
TCr (ppm/°C)
TCr (ppm/°C)
150
400
300
200
100
50
100
0
15
65
115
165
TAP POSITION (DECIMAL)
FIGURE 15. 10k TCr vs TAP POSITION
11
215
0
15
65
115
165
215
TAP POSITION (DECIMAL)
FIGURE 16. 50k TCr vs TAP POSITION
FN7778.0
December 15, 2010
ISL23315
Typical Performance Curves
(Continued)
120
35
30
90
TCr (ppm/°C)
TCv (ppm/°C)
25
20
15
10
60
30
5
0
15
65
115
165
215
0
15
65
TAP POSITION (DECIMAL)
FIGURE 17. 100k TCv vs TAP POSITION
115
165
TAP POSITION (DECIMAL)
215
FIGURE 18. 100k TCr vs TAP POSITION
SCL CLOCK
RW PIN
10mV/DIV
1µs/DIV
20mV/DIV
5µs/DIV
FIGURE 19. WIPER DIGITAL FEED-THROUGH
1V/DIV
1µs/DIV
FIGURE 20. WIPER TRANSITION GLITCH
1V/DIV
0.1s/DIV
WIPER
SCL 9TH CLOCK OF THE
DATA BYTE (ACK)
FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME
12
FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE
FN7778.0
December 15, 2010
ISL23315
Typical Performance Curves
(Continued)
1.2
STANDBY CURRENT ICC (µA)
CH1: 0.5V/DIV, 0.2µs/DIV RH PIN
CH2: 0.2V/DIV, 0.2µs/DIV RW PIN
RTOTAL = 10k
-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP
1.0
0.8
VCC = 5.5V, VLOGIC = 5.5V
0.6
0.4
VCC = 1.7V, VLOGIC = 1.2V
0.2
0
-40
-15
10
35
60
85
110
TEMPERATURE (°C)
FIGURE 23. 10k -3dB CUT OFF FREQUENCY
Functional Pin Descriptions
Potentiometers Pins
RH AND RL
The high (RH) and low (RL) terminals of the ISL23315 are
equivalent to the fixed terminals of a mechanical potentiometer.
RH and RL are referenced to the relative position of the wiper and
not the voltage potential on the terminals. With WR set to 255
decimal, the wiper will be closest to RH, and with the WR set to 0,
the wiper is closest to RL.
RW
RW is the wiper terminal, and it is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
FIGURE 24. STANDBY CURRENT vs TEMPERATURE
VLOGIC
This is an input pin, that supply internal level translator for serial
bus operation from 1.2V to 5.5V.
Principles of Operation
The ISL23315 is an integrated circuit incorporating one DCP with
its associated registers and an I2C serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a “make before
break” mode when the wiper changes tap positions.
Bus Interface Pins
Voltage at any DCP pins, RH, RL or RW, should not exceed VCC
level at any conditions during power-up and normal operation.
SERIAL DATA INPUT/OUTPUT (SDA)
The VLOGIC pin needs to be connected to the I2C bus supply
which allows reliable communication with the wide range of
microcontrollers and independent of the VCC level. This is
extremely important in systems where the master supply has
lower levels than DCP analog supply.
The SDA is a bidirectional serial data input/output pin for I2C
interface. It receives device address, operation code, wiper
address and data from an I2C external master device at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock.
SDA requires an external pull-up resistor, since it is an open drain
input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A1, A0)
The address inputs are used to set the least significant 2 bits of
the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL23315. A
maximum of four ISL23315 devices may occupy the I2C serial
bus (see Table 3).
13
DCP Description
The DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(RH and RL pins). The RW pin of the DCP is connected to
intermediate nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by an 8-bit volatile Wiper Register
(WR). When the WR of a DCP contains all zeroes (WR[7:0]= 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL). When
the WR register of a DCP contains all ones (WR[7:0]= FFh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As the
value of the WR increases from all zeroes (0) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the position closest to RH. At the same time, the
FN7778.0
December 15, 2010
ISL23315
resistance between RW and RL increases monotonically, while
the resistance between RH and RW decreases monotonically.
indicating START and STOP conditions (see Figure 26). On
power-up of the ISL23315, the SDA pin is in the input mode.
While the ISL23315 is being powered up, the WR is reset to 80h
(128 decimal), which locates RW roughly at the center between
RL and RH.
All I2C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
ISL23315 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 26). A START condition is ignored
during the power-up of the device.
The WR can be read or written to directly using the I2C serial
interface as described in the following sections.
Memory Description
The ISL23315 contains two volatile 8-bit registers: Wiper Register
(WR) and Access Control Register (ACR). Memory map of ISL23315
is in Table 1. The Wiper Register (WR) at address 0, contains current
wiper position. The Access Control Register (ACR) at address 10h
contains information and control bits described in Table 2.
TABLE 1. MEMORY MAP
ADDRESS
(hex)
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
10
ACR
42
0
WR
80
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
3
2
1
0
NAME/
VALUE
0
SHDN
0
0
0
0
1
0
The SHDN bit (ACR[6]) disables or enables Shutdown mode. When
this bit is 0, i.e. DCP is forced to end-to-end open circuit and RW is
shorted to RL as shown in Figure 25. Default value of the SHDN bit
is 1.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 26). A STOP condition at the end of a read
operation or at the end of a write operation places the device in
its standby mode.
An ACK (Acknowledge) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data
(see Figure 27).
The ISL23315 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of an Address Byte. The ISL23315 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 10100 as the five MSBs, and
the following two bits matching the logic values present at pins
A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a
Read operation and “0” for a Write operation (see Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
RH
LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY
RW
1
(MSB)
0
1
0
0
A1
A0
R/W
(LSB)
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
I2C Serial Interface
The ISL23315 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL23315 operates as a slave device
in all applications.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
14
FN7778.0
December 15, 2010
ISL23315
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 26. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 27. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
S
T
A
R
T
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
IDENTIFICATION
BYTE
ADDRESS
BYTE
1 0 1 0 0 A1 A0 0
SIGNALS FROM
THE SLAVE
S
T
O
P
DATA
BYTE
0 0 0
A
C
K
A
C
K
A
C
K
FIGURE 28. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
1 0 1 0 0 A1 A0 0
READ
A
C
K
IDENTIFICATION
BYTE WITH
R/W = 1
S
A T
C O
K P
A
C
K
1 0 1 0 0 A1 A0 1
0 0 0
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A
R
T
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 29. READ SEQUENCE
15
FN7778.0
December 15, 2010
ISL23315
Write Operation
Applications Information
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23315 responds
with an ACK. The data is transferred from I2C block to the
corresponding register at the 9th clock of the data byte and
device enters its standby state (see Figures 27 and 28).
VLOGIC Requirements
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 29). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23315 responds
with an ACK; then the ISL23315 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 29).
16
It is recommended to keep VLOGIC powered all the time during
normal operation. In a case where turning VLOGIC OFF is
necessary, it is recommended to ground the VLOGIC pin of the
ISL23315. Grounding the VLOGIC pin or both VLOGIC and VCC does
not affect other devices on the same bus. It is good practice to
put a 1µF cap in parallel to 0.1µF as close to the VLOGIC pin as
possible.
VCC Requirements and Placement
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the VCC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
EFh to FFh, which have higher transient glitch. Note, that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients.
However, that will also reduce the useful bandwidth of the circuit,
thus may not be a good solution for some applications. It may be
a good idea, in that case, to use fast amplifiers in a signal chain
for fast recovery.
FN7778.0
December 15, 2010
ISL23315
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
12/15/10
FN7778.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address
some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product
families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil
product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL23315
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN7778.0
December 15, 2010
ISL23315
Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L
SEATING
PLANE
C
0.20 (0.008)
MIN
MAX
MIN
MAX
NOTES
A
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.020 BSC
C
a
CL
E1
0.20 (0.008)
C D
-B-
-
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
0.50 BSC
E
L1
-A-
SIDE VIEW
SYMBOL
e
L1
MILLIMETERS
0.95 REF
10
R
0.003
R1
-
10
-
0.07
0.003
-
θ
5o
15o
α
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
Rev. 0 12/02
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
18
FN7778.0
December 15, 2010
ISL23315
Package Outline Drawing
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
8.
PIN 1
INDEX AREA
2.10
A
B
PIN #1 ID
1
0.05 MIN.
1
8.
4
4X 0.20 MIN.
1.60
0.10 MIN.
10
5
0.80
10X 0.40
0.10
6
9
2X
6X 0.50
10 X 0.20 4
TOP VIEW
0.10 M C A B
M C
BOTTOM VIEW
(10 X 0.20)
SEE DETAIL "X"
(0.05 MIN)
PACKAGE
OUTLINE
1
MAX. 0.55
0.10 C
(10X 0.60)
C
(0.10 MIN.)
(2.00)
SEATING PLANE
0.08 C
SIDE VIEW
(0.80)
(1.30)
C
0 . 125 REF
(6X 0.50 )
(2.50)
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
19
1.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2.
All Dimensions are in millimeters. Angles are in degrees.
Dimensions in ( ) for Reference Only.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Lead width dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Maximum package warpage is 0.05mm.
6.
Maximum allowable burrs is 0.076mm in all directions.
7.
Same as JEDEC MO-255UABD except:
No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm
Lead Length dim. = 0.45mm max. not 0.42mm.
8.
The configuration of the pin #1 identifier is optional, but must be located within
the zone indicated. The pin #1 identifier may be either a mold or mark feature.
FN7778.0
December 15, 2010