K6X4016T3F Family CMOS SRAM Document Title 256Kx16 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No History Draft Date Remark 0.0 Initial draft July 29, 2002 Preliminary 0.1 Revised - Added Commercial product - Deleted 44-TSOP2-400R Package Type. - Added 55ns product(@ 3.0V~3.6V) December 2, 2002 Preliminary 1.0 Finalized Revised - Changed ICC(Operating power supply current) from 4mA to 2mA - Changed ICC1(Average operating current) from 4mA to 3mA - Changed ICC2(Average operating current) from 40mA to 25mA - Changed ISB1(Standby Current(CMOS), Commercial) from 15µA to 10µA - Changed ISB1(Standby Current(CMOS), Industrial) from 20µA to 10µA - Changed ISB1(Standby Current(CMOS), Automotive) from 30µA to 20µA - Changed IDR(Data retention current, Commercial) from 15µA to 10µA - Changed IDR(Data retention current, Industrial) from 20µA to 10µA - Changed IDR(Data retention current, Automotive) from 30µA to 20µA August 8, 2003 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 August 2003 K6X4016T3F Family CMOS SRAM 256Kx16 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: Full CMOS • Organization: 256K x16 • Power Supply Voltage: 2.7~3.6V • Low Data Retention Voltage: 2V(Min) • Three State Outputs • Package Type: 44-TSOP2-400F The K6X4016T3F families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature range and have 44-TSOP2 package type for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range K6X4016T3F-B Commercial(0~70°C) K6X4016T3F-F Industrial(-40~85°C) K6X4016T3F-Q Automotive(-40~125°C) 2.7~3.6V Speed(ns) Standby (ISB1, Max) 551)/702)/85ns Operating (ICC2, Max) PKG Type 10µA 25mA 10µA 44-TSOP2-400F 20µA 702)/85ns 1. This parameter is measured with 30pF test load (Vcc=3.0~3.6V). 2. The parameter is measured with 30pF test load. FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-TSOP2 Forward A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 Clk gen. Precharge circuit. Vcc Vss Row Addresses I/O1~I/O8 Row select Data cont Memory array I/O Circuit Column select Data cont I/O9~I/O16 Data cont Name Function Name Function CS Chip Select Input Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input LB Lower Byte (I/O1~8) Address Inputs UB Upper Byte (I/O9~16) NC No Connection A0~A17 I/O1~I/O16 Data Input/Output Column Addresses WE OE UB Control logic LB CS SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 August 2003 K6X4016T3F Family CMOS SRAM PRODUCT LIST Commercial Products(0~70°C) Part Name K6X4016T3F-TB551) K6X4016T3F-TB70 K6X4016T3F-TB85 Industrial Products(-40~85°C) Function Part Name 44-TSOP2-F, 55ns, LL 44-TSOP2-F, 70ns, LL 44-TSOP2-F, 85ns, LL K6X4016T3F-TF551) K6X4016T3F-TF70 K6X4016T3F-TF85 Automotive Products(-40~125°C) Function 44-TSOP2-F, 55ns, LL 44-TSOP2-F, 70ns, LL 44-TSOP2-F, 85ns, LL Part Name Function K6X4016T3F-TQ70 K6X4016T3F-TQ85 44-TSOP2-F, 70ns, L 44-TSOP2-F, 85ns, L 1. Operating voltage range is 3.0~3.6V FUNCTIONAL DESCRIPTION CS OE WE LB UB I/O1~8 I/O9~16 1) 1) Mode Power H X X X X High-Z High-Z Deselected Standby L H H X1) X1) High-Z High-Z Output Disabled Active 1) 1) L X X H H High-Z High-Z Output Disabled Active L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active 1) 1) L 1) X L L H Din High-Z Lower Byte Write Active L X1) L H L High-Z Din Upper Byte Write Active L X1) L L L Din Din Word Write Active 1. X means don′t care. (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Symbol Ratings Unit Remark VIN,VOUT -0.2 to VCC+0.3(max. 3.9V) V - Voltage on Vcc supply relative to Vss VCC -0.2 to 3.9 V - Power Dissipation PD 1.0 W - TSTG -65 to 150 °C Storage temperature 0 to 70 Operating Temperature TA -40 to 85 -40 to 125 K6X4016T3F-B °C K6X4016T3F-F K6X4016T3F-Q 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 August 2003 K6X4016T3F Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Symbol Min Typ Max Unit Supply voltage Item Vcc 2.7 3.0/3.3 3.6 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.22) V Input low voltage VIL -0.23) - 0.6 V Note: 1. Commercial Product: TA=0 to 70°C, otherwise specified. Industrial Product: TA=-40 to 85°C, otherwise specified. Automotive Product: TA=-40 to 125°C, otherwise specified. 2. Overshoot: VCC+2.0V in case of pulse width ≤ 30ns. 3. Undershoot: -2.0V in case of pulse width ≤ 30ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIL=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 2 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V, VIN≤0.2V or VIN≥Vcc-0.2V - - 3 mA ICC2 Cycle time=Min2), 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - - 25 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.3 mA K6X4016T3F-B - 10 µA ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - Standby Current(CMOS) K6X4016T3F-F - - 10 µA K6X4016T3F-Q - - 20 µA Average operating current 4 Revision 1.0 August 2003 K6X4016T3F Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL CL1) 1.Including scope and jig capacitance AC CHARACTERISTICS ( VCC=2.7~3.6V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40 to 125°C ) Speed Bins Parameter List Symbol Read cycle time Read Write tRC 70ns 55ns1) Units 85ns Min Max Min Max Min Max 55 - 70 - 85 - ns Address access time tAA - 55 - 70 - 85 ns Chip select to output tCO - 55 - 70 - 85 ns Output enable to valid output tOE - 25 - 35 - 40 ns LB, UB valid to data output tBA - 25 - 35 - 40 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns LB, UB enable to low-Z output tBLZ 5 - 5 - 5 - ns Output hold from address change tOH 10 - 10 - 10 - ns Chip disable to high-Z output tHZ 0 20 0 25 0 25 ns OE disable to high-Z output tOHZ 0 20 0 25 0 25 ns LB, UB disable to high-Z output tBHZ 0 20 0 25 0 25 ns Write cycle time tWC 55 - 70 - 85 - ns Chip select to end of write tCW 45 - 60 - 70 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 45 - 60 - 70 - ns Write pulse width tWP 40 - 55 - 60 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 0 25 ns Data to write time overlap tDW 25 - 30 - 35 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns LB, UB valid to end of write tBW 45 - 60 - 70 - ns 1. Voltage range is 3.0V~3.6V for commercial and industrial product. DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS≥Vcc-0.2V Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V Min Typ Max Unit 2.0 - 3.6 V 10 µA - - K6X4016T3F-B K6X4016T3F-F K6X4016T3F-Q Data retention set-up time tSDR Recovery time tRDR See data retention waveform 5 10 µA 20 µA 0 - - 5 - - ms Revision 1.0 August 2003 K6X4016T3F Family CMOS SRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE Data out High-Z tOLZ tBLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 August 2003 K6X4016T3F Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tWR(4) tCW(2) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 1.0 August 2003 K6X4016T3F Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 2.7V 2.2V VDR CS≥VCC - 0.2V CS GND 8 Revision 1.0 August 2003 K6X4016T3F Family CMOS SRAM PACKAGE DIMENSIONS Unit: millimeter(inch) 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0~8° 0.25 ( ) 0.010 #44 #23 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 ( 0.50 ) 0.020 #1 #22 1.00±0.10 0.039±0.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.35± 0.10 0.014±0.004 0.80 0.0315 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41±0.10 0.725±0.004 9 0 + 0.1 5 - 0.0 04 .0 +0 02 .006 - 0.0 0.15 0 0.10 0.004 MAX Revision 1.0 August 2003