LTM4628 Dual 8A or Single 16A DC/DC µModule Regulator Features n n n n n n n n n n n n n n n n Description Complete Standalone Dual Power Supply Single 16A or Dual 8A Output Wide Input Voltage Range: 4.5V to 26.5V Output Voltage Range: 0.6V to 5.5V ±1.5% Total DC Output Error Differential Remote Sense Amplifier Current Mode Control/Fast Transient Response Adjustable Switching Frequency Overcurrent Foldback Protection Multiphase Parallel Current Sharing with Multiple LTM4628s Frequency Synchronization Internal Temperature Sensing Diode Output Selectable Burst Mode® Operation Soft-Start/Voltage Tracking Output Overvoltage Protection Small Surface Mount Footprint, Low Profile 15mm × 15mm × 4.32mm LGA and 15mm × 15mm × 4.92mm BGA Packages The LTM®4628 is a complete dual 8A output switching mode DC/DC power supply and can be easily configured to provide a single 2-phase 16A output. Included in the package are the switching controller, power FETs, inductor, and all supporting components. Operating from an input voltage range of 4.5V to 26.5V, the LTM4628 supports two outputs each with an output voltage range of 0.6V to 5.5V, set by a single external resistor. Its high efficiency design delivers 8A continuous current for each output. Only a few input and output capacitors are needed. The device supports frequency synchronization, multiphase operation, Burst Mode operation and output voltage tracking for supply rail sequencing. It has an onboard temperature diode for device temperature monitoring. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage and overcurrent protection. The power module is offered in space saving and thermally enhanced 15mm × 15mm × 4.32mm LGA and 15mm × 15mm × 4.92mm BGA packages. The LTM4628 is RoHS compliant with Pb-free finish. Applications n n n Telecom and Networking Equipment Storage and ATCA Cards Industrial Equipment L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase are registered and LTpowerCAD is a trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application Dual 8A, 1.5V and 1.2V Output DC/DC µModule® Regulator Efficiency and Power Loss at 12V Input 4.7µF 95 MODE_PLLIN CLKOUT INTVCC * 10k VOUT1 VIN 10µF 35V ×4 120k TEMP VOUTS1 RUN1 DIFFOUT RUN2 SW1 TRACK1 5.1V ZENER 470µF 6.3V VFB1 LTM4628 TRACK2 0.1µF VOUT1 1.5V AT 8A 100µF 6.3V VFB2 fSET COMP1 PHASMD COMP2 40.2k 60.4k VOUTS2 VOUT2 100k SW2 PGOOD2 * PULL-UP RESISTOR AND ZENER ARE OPTIONAL. SGND GND DIFFP 100µF 6.3V VOUT2 1.2V AT 8A 470µF 6.3V 1.2V 1.5V 90 2.0 1.8 EFFICIENCY 1.6 85 1.4 80 1.2 75 1.0 70 0.8 POWER LOSS 65 0.6 60 0.4 55 0.2 50 0 1 2 3 5 6 4 LOAD CURRENT (A) 7 8 POWER LOSS (W) * EXTVCC PGOOD1 EFFICIENCY (%) VIN 4.5V TO 26.5V 0 4628 TA01b DIFFN 4628 TA01a 4628fd 1 LTM4628 Absolute Maximum Ratings (Note 1) VIN.............................................................. –0.3V to 28V VSW1, VSW2.....................................................–1V to 28V PGOOD1, PGOOD2, RUN1, RUN2, INTVCC, EXTVCC........................................... –0.3V to 6V MODE_PLLIN, fSET, TRACK1, TRACK2, DIFFOUT, PHASMD................................ –0.3V to INTVCC VOUT1, VOUT2, VOUTS1, VOUTS2...................... –0.3V to 6V DIFFP, DIFFN.......................................... –0.3V to INTVCC VFB1, VFB2, COMP1, COMP2 (Note 6)......... –0.3V to 2.7V INTVCC Peak Output Current.................................100mA Internal Operating Temperature Range (Note 2)................................................... –40°C to 125°C Storage Temperature Range................... –55°C to 125°C Peak Package Body Temperature........................... 245°C Pin Configuration TOP VIEW TOP VIEW M M VIN VIN L L K K TEMP TEMP EXTVCC J EXTVCC J INTVCC H SW1 SGND MODE_PLLIN RUN1 F GND VFB1 D VOUTS1 C SGND fSET VFB2 DIFFP PHASMD CLKOUT SW2 PGOOD2 PGOOD1 G DIFFOUT RUN2 TRACK1 COMP1 COMP2 E SW1 SW2 PGOOD2 PGOOD1 PHASMD CLKOUT G INTVCC H GND GND DIFFN D SGND VOUTS2 DIFFOUT RUN2 TRACK1 COMP1 COMP2 E TRACK2 SGND MODE_PLLIN RUN1 F VFB1 SGND VOUTS1 fSET VFB2 DIFFP GND DIFFN TRACK2 SGND VOUTS2 C B B GND VOUT1 A 1 2 3 4 5 6 VOUT1 VOUT2 7 8 9 10 11 VOUT2 GND A 12 LGA PACKAGE 144-LEAD (15mm × 15mm × 4.32mm) TJMAX = 125°C, θJCtop = 17°C/W,θJCbottom = 2.75°C/W, θJB + θBA = 11°C/W, θJA = 9.5°C/W–11°C/W, θBA = BOARD TO AMBIENT RESISTANCE, θ VALUES DEFINED PER JESD 51-12 WEIGHT = 2.7g 1 2 3 4 5 6 7 8 9 10 11 12 BGA PACKAGE 144-LEAD (15mm × 15mm × 4.92mm) TJMAX = 125°C, θJCtop = 17°C/W,θJCbottom = 2.75°C/W, θJB + θBA = 11°C/W, θJA = 9.5°C/W–11°C/W, θBA = BOARD TO AMBIENT RESISTANCE, θ VALUES DEFINED PER JESD 51-12 WEIGHT = 2.9g Order Information LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE† LTM4628EV#PBF LTM4628EV#PBF LTM4628V 144-Lead (15mm × 15mm × 4.32mm) LGA –40°C to 125°C LTM4628IV#PBF LTM4628IV#PBF LTM4628V 144-Lead (15mm × 15mm × 4.32mm) LGA –40°C to 125°C LTM4628EY#PBF LTM4628EY#PBF LTM4628Y 144-Lead (15mm × 15mm × 4.92mm) BGA –40°C to 125°C LTM4628IY#PBF LTM4628IY#PBF LTM4628Y 144-Lead (15mm × 15mm × 4.92mm) BGA –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. † See Note 2. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ 2 4628fd LTM4628 Electrical Characteristics The l denotes the specifications which apply over the full internal operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted, per the typical application in Figure 28. SYMBOL PARAMETER CONDITIONS MIN VIN Input DC Voltage l VOUT Output Voltage l VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load CIN = 22µF × 3, COUT = 100µF × 1 Ceramic, 470µF POSCAP, MODE_PLLIN = GND, RFB1, RFB2 = 40.2k, VIN = 4.5V to 26.5V, l IOUT = 0A to 8A RUN Pin On/Off Threshold RUN Rising TYP MAX UNITS 4.5 26.5 V 0.6 5.5 V 1.477 1.5 1.523 V 1.1 1.25 1.40 V Input Specifications VRUN1, VRUN2 VRUN1HYS , VRUN2HYS RUN Pin On Hysteresis 150 mV IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A, CIN = 22µF × 3, COUT = 100µF , 470µF POSCAP VOUT1 = 1.5V, VOUT2 = 1.5V, VIN = 12V, TRACK = 0.01µF 1 A IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 1.5V, Burst Mode Operation VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode VIN = 12V, VOUT= 1.5V, Switching Continuous Shutdown, RUN = 0, VIN = 12V 5 15 65 60 mA mA mA µA IS(VIN) Input Supply Current VIN = 4.75V, VOUT = 1.5V, IOUT = 8A VIN = 12V, VOUT = 1.5V, IOUT = 8A VIN = 26.5V, VOUT = 1.5V, IOUT = 8A IOUT1(DC), IOUT2(DC) Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Note 7) ΔVOUT1(LINE) /VOUT1 ΔVOUT2(LINE) /VOUT2 Line Regulation Accuracy VOUT = 1.5V, VIN from 4.5V to 26.5V IOUT = 0A for Each Output, l 0.010 0.04 %/V ΔVOUT1(LOAD) /VOUT1 Load Regulation Accuracy ΔVOUT2(LOAD) /VOUT2 For Each Output, VOUT = 1.5V, 0A to 8A VIN = 12V (Note 7) l 0.15 0.3 % VOUT1(AC), VOUT2(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF X5R Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V 15 mVP-P fS (Each Channel) Output Ripple Voltage Frequency VIN = 12V, VOUT = 1.5V, fSET = 2.5V (Note 4) 780 kHz fSYNC (Each Channel) SYNC Capture Range ∆VOUTSTART (Each Channel) Turn-On Overshoot COUT = 100µF X5R Ceramic, 470µF POSCAP, VOUT = 1.5V, IOUT = 0A VIN = 12V 10 mV tSTART (Each Channel) Turn-On Time COUT = 100µF X5R Ceramic, 470µF POSCAP, No Load, TRACK/SS with 0.01µF to GND, VIN = 12V 5 ms ∆VOUT(LS) (Each Channel) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 22µF × 3 X5R Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V 30 mV tSETTLE (Each Channel) Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 12V, COUT = 100µF, COUT = 470µF 20 µs IOUT(PK) (Each Channel) Output Current Limit VIN = 12V, VOUT = 1.5V 15 A VFB1, VFB2 Voltage at VFB Pins IOUT = 0A, VOUT = 1.5V IFB1, IFB2 Leakage Current of VFB1, VFB2 (Note 6) VOVL Feedback Overvoltage Lockout 2.9 1.18 0.575 A A A Output Specifications 0 8 400 780 A kHz Control Section l 0.592 0.600 0.606 V l 0.64 –5 –20 nA 0.66 0.68 V 4628fd 3 LTM4628 Electrical Characteristics The l denotes the specifications which apply over the full internal operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted, per the typical application in Figure 28. SYMBOL PARAMETER CONDITIONS ITRACK1, ITRACK2 Track Pin Soft-Start Pull-Up Current TRACK1, TRACK2 = 0V UVLO Undervoltage Lockout Threshold VIN Falling VIN Rising tON(MIN) Minimum On-Time (Note 6) RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 and VFB1, VFB2 Pins for Each Output VOL_PGOOD (Each Channel) PGOOD Voltage Low IPGOOD = 2mA IPGOOD PGOOD Leakage Current VPGOOD = 5V VPGOOD PGOOD Trip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive MIN TYP MAX 1 1.25 1.5 3.3 3.9 UVLO Hysteresis 60.05 UNITS µA V V 0.6 V 90 ns 60.4 60.75 0.1 0.3 V ±5 µA –10 10 kΩ % % INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 26.5V VINTVCC Load Regulation INTVCC Load Regulation ICC = 0mA to 50mA VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V VEXTVCC(HYST) EXTVCC Hysteresis 4.8 4.5 5 5.2 V 0.5 2 % 100 mV 4.7 50 V 200 mV Oscillator and Phase-Locked Loop fNOM Nominal Frequency fSET = 1.2V 450 500 550 kHz fLOW Lowest Frequency fSET = 0V (Note 5) 210 250 290 kHz fSET > 2.4V, Up to INTVCC 700 780 860 kHz 9 10 11 µA fHIGH Highest Frequency IfSET Frequency Set Current RMODE_PLLIN Mode_PLLIN Input Resistance PhCLKOUT Phase (Relative to VOUT1) VOH_CLKOUT VOL_CLKOUT Clock High Output Voltage Clock Low Output Voltage PHASMD = GND PHASMD = Float PHASMD = INTVCC 250 kΩ 60 90 120 Deg Deg Deg 2 0.2 V V Differential Amplifier AV Voltage Gain RIN Input Resistance Measured at DIFFP Input VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA 5V < VIN < 20V PSRR Power Supply Rejection Ratio ICL Maximum Output Current DIFFOUT (MAX) Maximum Output Voltage GBW Gain Bandwidth Product IDIFFOUT = 300µA 1 V/V 80 kΩ 3 mV 90 dB 3 mA 3 MHz INTVCC – 1.4V V 4628fd 4 LTM4628 Electrical Characteristics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4628 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4628E is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4628I is guaranteed over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: Two outputs are tested separately and the same testing condition is applied to each output. Note 4: The switching frequency is programmable for 400kHz to 750kHz. Note 5: LTM4628 device is designed to operate from 400kHz to 750kHz Note 6: 100% tested at wafer level. Note 7: See output current derating curves for different VIN, VOUT and TA. Typical Performance Characteristics 5VIN Efficiency 12VIN Efficiency 100 FREQ = 500kHz 90 EFFICIENCY (%) EFFICIENCY (%) 95 85 80 3.3VOUT 2.5VOUT 1.5VOUT 1.2VOUT 0.8VOUT 75 70 65 0 1 4 5 2 3 6 OUTPUT CURRENT (A) 7 FREQ = 500kHz, 700kHz for 3.3V AND 5V 95 90 90 85 85 80 80 75 5VOUT 3.3VOUT 2.5VOUT 1.5VOUT 1.2VOUT 0.8VOUT 70 65 60 8 24VIN Efficiency 95 EFFICIENCY (%) 100 55 0 1 4 5 2 3 6 OUTPUT CURRENT (A) 7 FREQ = 500kHz, 700kHz for 3.3V AND 5V 75 70 65 5VOUT 3.3VOUT 2.5VOUT 1.5VOUT 60 55 50 8 0 1 4 5 2 3 6 OUTPUT CURRENT (A) 4628 G02 4628 G01 Burst Mode Pulse-Skipping Efficiency 7 8 4628 G03 0.8V Load Transient 1.2V Load Transient 100 90 EFFICIENCY (%) 80 Burst Mode OPERATION 70 VOUT 50mV/DIV VOUT 50mV/DIV IOUT 2A/DIV IOUT 2A/DIV 60 50 40 30 20 PULSE-SKIPPING MODE 10 0 0.001 0.01 1 0.1 OUTPUT CURRENT (A) 10 4628 G05 100µs/DIV 12VIN , 0.8VOUT , 0A TO 4A LOAD STEP AT 4A/µs COUT1 4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE SWITCHING FREQUENCY 400kHz CFF CAPACITOR = 47pF 100µs/DIV 4628 G06 12VIN , 1.2VOUT , 0A TO 4A LOAD STEP AT 4A/µs COUT1, 4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE SWITCHING FREQUENCY 500kHz CFF CAPACITOR = 47pF 4628 G04 4628fd 5 LTM4628 Typical Performance Characteristics 1.5V Load Transient 1.8V Load Transient VOUT 50mV/DIV VOUT 50mV/DIV IOUT 2A/DIV IOUT 2A/DIV 100µs/DIV 2.5V Load Transient VOUT 100mV/DIV IOUT 2A/DIV 100µs/DIV 4628 G07 4628 G08 100µs/DIV 4628 G09 12VIN , 1.5VOUT , 0A TO 4A LOAD STEP AT 4A/µs COUT1 4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE SWITCHING FREQUENCY 500kHz CFF CAPACITOR = 47pF 12VIN , 1.8VOUT , 0A TO 4A LOAD STEP AT 4A/µs COUT1 4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE SWITCHING FREQUENCY 500kHz CFF CAPACITOR = 47pF 12VIN , 2.5VOUT , 0A TO 4A LOAD STEP AT 4A/µs COUT1, 4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE SWITCHING FREQUENCY 500kHz CFF CAPACITOR = 47pF 3.3V Load Transient Output Start-Up Output Start-Up VOUT 100mV/DIV IOUT 2A/DIV 100µs/DIV VOUT 1V/DIV 5ms/DIV VOUT 1V/DIV 5ms/DIV INPUT CURRENT 1A/DIV INPUT CURRENT 1A/DIV 4628 G10 12VIN , 3.3VOUT , 0A TO 4A LOAD STEP AT 4A/µs COUT1, 4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE SWITCHING FREQUENCY 500kHz CFF CAPACITOR = 47pF Output Short-Circuit VIN = 12V VOUT = 2.5V IOUT = 0A 20ms/DIV 4628 G11 Output Short-Circuit VOUT 1V/DIV 5ms/DIV VIN = 12V VOUT = 2.5V IOUT = 8A 20ms/DIV 4628 G12 Coincident Tracking VOUT 1V/DIV 5ms/DIV INPUT CURRENT 2A/DIV INPUT CURRENT 2A/DIV VIN = 12V VOUT = 2.5V IOUT = 0A 50µs/DIV 4628 G13 VIN = 12V VOUT = 2.5V IOUT = 8A 50µs/DIV 4628 G14 10ms/DIV VOUT1 = 1.8V AT 8A VOUT2 = 1.2V AT 8A 4628 G15 4628fd 6 LTM4628 Typical Performance Characteristics COMP1 and COMP2 vs Output Current IOUT1 and IOUT2 vs Total Current for Parallel Operation 9 8 7 1.2 6 1.1 5 4 1.0 0.9 3 0.8 2 0.7 1 0.6 0 0 2 VITH1 VITH2 1.3 COMP (V) IOUT1 AND IOUT2 (A) 1.4 IOUT1 IOUT2 8 10 12 14 4 6 TOTAL OUTPUT CURRENT (A) 16 0.5 0 1 2 3 4 5 6 7 OUTPUT CURRENT (A) 4628 G16 Pin Functions 8 9 4628 G17 (Recommended to Use Test Points to Monitor Signal Pin Connections.) VOUT1 (A1-A5, B1-B5, C1-C4): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 4. GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12, F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1, J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power Ground Pins for Both Input and Output Returns. VOUT2 (A8-A12, B8-B12, C9-C12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 4. VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the VOUTS pins is connected to the DIFFOUT pin in remote sensing or directly to VOUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or VOUT since this is the feedback path, and cannot be left open. See the Applications Information section. fSET (C6): Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 27. VFB1, VFB2 (D5, D7): The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is connected to VOUTS1 or VOUTS2 with a 60.4kΩ precision resistor. Different output voltages can be programmed with an additional resistor between VFB and GND pins. In PolyPhase® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. 4628fd 7 LTM4628 Pin Functions (Recommended to Use Test Points to Monitor Signal Pin Connections.) TRACK1, TRACK2 (E5, D8): Output Voltage Tracking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave output’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. See the Applications Information section. COMP1, COMP2 (E6, E7): Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. Tie the COMP pins together for parallel operation. The device is internal compensated. DIFFP (E8): Positive input of the remote sense amplifier. This pin is connected to the remote sense point of the output voltage. Use of the remote sense amplifier is limited to an output voltage between 0.6V and 3.3V inclusive. Connect to GND if not used. See the Applications Information section. DIFFN (E9): Negative input of the remote sense amplifier. This pin is connected to the remote sense point of the output GND. See the Applications Information section. MODE_PLLIN (F4): Force Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into force continuous mode of operation. Connect to INTVCC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related channel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.2V an additional 4.5µA pull-up current is added to this pin. DIFFOUT (F8): Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation connect one of the VOUTS pin to DIFFOUT for remote sensing. Leave floating if the remote sense amplifier is not used. SW1, SW2 (G2, G11): Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, otherwise leave floating. See the Applications Information section. PHASMD (G4): Connect this pin to SGND, INTVCC, or floating this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. CLKOUT (G5): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. PGOOD1, PGOOD2 (G9, G8): Output Voltage Power Good Indicator. Open drain logic output that is pulled to ground when the output voltage is not within ±7.5% of the regulation point. INTVCC (H8): Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. INTVCC is controlled and enabled when RUN1 or RUN2 is activated high. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. TEMP (J6): Onboard Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section. EXTVCC (J7): External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V. An efficiency increase will occur that is a function of the (VIN – INTVCC) multiplied by power MOSFET driver current. Typical current requirement is 30mA. VIN must be applied before EXTVCC, and EXTVCC must be removed before VIN. VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. 4628fd 8 LTM4628 Simplified Block Diagram PGOOD1 TRACK1 VIN SS CAP 100µA = VIN RT VIN CIN1 10µF 35V 1µF GND RT TEMP MTOP1 SW1 CLKOUT 0.68µH RUN1 MODE_PLLIN VOUT1 2.2µF MBOT1 PHASEMD CIN2 10µF 35V + 1.5V/8A COUT1 GND VOUTS1 COMP1 60.4k VFB1 INTERNAL COMP SGND RFB1 40.2k POWER CONTROL PGOOD2 TRACK2 SS CAP VIN INTVCC CIN3 10µF 35V 1µF 4.7µF GND EXTVCC MTOP2 SW2 0.68µH RUN2 CIN4 10µF 35V VOUT2 2.2µF MBOT2 + 1.2V/8A COUT2 GND VOUTS2 COMP2 fSET 60.4k XI + – VFB2 RFB2 60.4k INTERNAL COMP INTERNAL FILTER RfSET SGND DIFFOUT DIFFN DIFFP 4628 BD Figure 1. Simplified LTM4628 Block Diagram Decoupling Requirements TA = 25°C. Use Figure 1 configuration. SYMBOL PARAMETER CONDITIONS CIN1, CIN3 CIN2, CIN4 External Input Capacitor Requirement (VIN1 = 4.5V to 26.5V, VOUT1 = 1.5V) (VIN2 = 4.5V to 26.5V, VOUT2 = 1.5V) IOUT1 = 8A IOUT2 = 8A 22 22 µF µF COUT1 COUT2 External Output Capacitor Requirement (VIN1 = 4.5V to 26.5V, VOUT1 = 1.5V) (VIN2 = 4.5V to 26.5V, VOUT2 = 1.5V) IOUT1 = 8A IOUT2 = 8A 300 300 µF µF MIN TYP MAX UNITS 4628fd 9 LTM4628 Operation Power Module Description The LTM4628 is a dual-output standalone nonisolated switching mode DC/DC power supply. It can provide two 8A outputs with few external input and output capacitors and setup components. This module provides precisely regulated output voltages programmable via external resistors from 0.6VDC to 5VDC over 4.5V to 26.5V input voltages. The typical application schematic is shown in Figure 28. The LTM4628 has dual integrated constant-frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 550kHz. For switching-noise sensitive applications, it can be externally synchronized from 400kHz to 780kHz. A resistor can be used to program a free run frequency on the fSET pin. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4628 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±7.5% window around the regulation point. If the output voltage exceeds 10% above its normal operating point then the bottom power MOSFET will try to clamp the output to protect it. Pulling the RUN pins below 1.1V forces the regulators into a shutdown state, by turning off both MOSFETs. The TRACK pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. See the Applications Information section. The LTM4628 is internally compensated to be stable over all operating conditions. Table 2 provides a guideline for input and output capacitances for several operating conditions. LTpowerCAD™ is available for transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to ground. A differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. Multiphase operation can be easily employed with the MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin to different levels. See the Applications Information section. High efficiency at light loads can be accomplished with selectable Burst Mode operation or pulse-skipping operation using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. See the Applications Information section for details. A temperature diode is included inside the module to monitor the temperature of the module. See the Applications Information section for details. The switch pins are available for functional operation monitoring and a resistor-capacitor snubber circuit can be carefully placed on the switch pin to ground to dampen any high frequency ringing on the transition edges. See the Applications Information section for details. 4628fd 10 LTM4628 Applications Information The typical LTM4628 application circuit is shown in Figure 28. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 4 for specific external capacitor requirements for particular applications. VIN to VOUT Step-Down Ratios There are restrictions in the maximum VIN and VOUT stepdown ratio that can be achieved for a given input voltage. Each output of the LTM4628 is capable of 98% duty cycle, but the VIN to VOUT minimum dropout is still shown as a function of its load current and will limit output current capability related to high duty cycle on the top side switch. Minimum on-time tON(MIN) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that tON(MIN) < D/fSW, where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 90ns. Output Voltage Programming The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 60.4kΩ internal feedback resistor connects between the VOUTS1 to VFB1 and VOUTS2 to VFB2. It is very important that these pins be connected to their respective outputs for proper feedback regulation. Overvoltage can occur if these VOUTS1 and VOUTS2 pins are left floating when used as individual regulators, or at least one of them is used in paralleled regulators. The output voltage will default to 0.6V with no feedback resistor on either VFB1 or VFB2. Adding a resistor RFB from VFB pin to GND programs the output voltage: VOUT = 0.6V • In parallel operation the VFB pins have an IFB current of 20nA maximum each channel. To reduce output voltage error due to this current, an additional VOUTS pin can be tied to VOUT, and an additional RFB resistor can be used to lower the total Thevenin equivalent resistance seen by this current. For example in Figure 2, the total Thevenin equivalent resistance of the VFB pin is (60.4k // RFB), which is 30.2k where RFB is equal to 60.4k for a 1.2V output. Four phases connected in parallel equates to a worse case feedback current of 4 • IFB equals 80nA maximum. The voltage error is 80nA • 30.2k = 2.4mV. If VOUTS2 is connected as shown in Figure 2 to VOUT, and another 60.4k resistor is connected from VFB2 to ground, then the voltage error is reduced to 1.2mV. If the voltage error is acceptable then no additional connections are necessary. The onboard 60.4k resistor is 0.5% accurate and the VFB resistor can be chosen by the user to be as accurate as needed. All COMP pins are tied together for current sharing between the phases. The TRACK pins can be tied together and a single soft-start capacitor can be used to soft-start the regulator. The soft-start equation will need to have the soft-start current parameter increased by the number of paralleled channels. See the Output Voltage Tracking section. COMP1 LTM4628 VOUT2 COMP2 60.4k TRACK1 60.4k VFB2 TRACK2 LTM4628 Table 1. VFB Resistor Table vs Various Output Voltages 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V RFB Open 90.9k 60.4k 40.2k 30.2k 19.1k 13.3k 8.25k For parallel operation of multiple channels the same feedback setting resistor can be used for the parallel design. This is done by connecting the VOUTS1 to the output as shown in Figure 2, thus tying one of the internal 60.4k resistors to the output. All of the VFB pins tie together with one programming resistor as shown in Figure 2. OPTIONAL RFB 60.4k VOUT1 USED TO LOWER TOTAL THEVENIN EQUIVALENT TO LOWER IFB VOLTAGE ERROR VOUT2 COMP2 1.0V OPTIONAL CONNECTION VFB1 COMP1 0.6V VOUTS1 VOUTS2 60.4k + RFB RFB VOUT 4 PARALLELED OUTPUTS FOR 1.2V AT 32A VOUT1 60.4k VOUTS1 VOUTS2 VFB1 TRACK1 0.1µF TRACK2 60.4k VFB2 4628 F02 RFB 60.4k Figure 2. 4-Phase Parallel Configurations 4628fd 11 LTM4628 Applications Information Input Capacitors The LTM4628 module should be connected to a low acimpedance DC source. For the regulator input three 22µF, or four 10µF input ceramic capacitors are used for RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter, the switching duty-cycle can be estimated as: D= VOUT VIN Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: IOUT(MAX) ICIN(RMS) = • D • (1− D) η% In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a Polymer capacitor. Output Capacitors The LTM4628 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, the low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range for each output is from 200µF to 470µF. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 4A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 4 matrix, and LTpowerCAD™ is available for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. LTpowerCAD can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be placed in series from VOUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be placed in series from VOUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. Burst Mode Operation The LTM4628 is capable of Burst Mode operation on each regulator in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. Burst Mode operation is enabled with the MODE_PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal operation even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the Burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMP to rise above 0.5V, the internal sleep line goes low, and the LTM4628 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Either regulator can be configured for Burst Mode operation. 4628fd 12 LTM4628 Applications Information Pulse-Skipping Mode Operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to SGND. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4628’s output voltage is in regulation. Either regulator can be configured for forced continuous mode. In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4628 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTVCC enables pulse-skipping operation. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. This mode will maintain higher effective frequencies thus lower output ripple and lower noise than Burst Mode operation. Either regulator can be configured for pulse-skipping mode. Multiphase Operation For output loads that demand more than 8A of current, two outputs in LTM4628 or even multiple LTM4628s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripple. The MODE_PLLIN pin allows the LTM4628 to synchronize to an external clock (between 400kHz and 780kHz) and the internal phase-locked loop allows the LTM4628 to lock Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation PHASMD PIN STATUS AND CORRESPONDING PHASE RELATIONSHIP 2-PHASE DESIGN PHASMD FLOAT CLKOUT 0 PHASE SGND OR FLOAT MODE_PLLIN VOUT1 VOUT2 SGND FLOAT CONTROLLER1 0° 0° 0° CONTROLLER2 180° 180° 240° CLKOUT 60° 90° 120° 180 PHASE INTVCC PHASMD 4-PHASE DESIGN 90 DEGREE CLKOUT 0 PHASE FLOAT CLKOUT MODE_PLLIN VOUT1 VOUT2 180 PHASE 90 PHASE FLOAT PHASMD MODE_PLLIN VOUT1 VOUT2 270 PHASE PHASMD 6-PHASE DESIGN 60 DEGREE 60 DEGREE CLKOUT 0 PHASE SGND CLKOUT MODE_PLLIN VOUT1 PHASMD VOUT2 180 PHASE 60 PHASE SGND CLKOUT MODE_PLLIN VOUT1 PHASMD VOUT2 240 PHASE 120 PHASE FLOAT MODE_PLLIN VOUT1 VOUT2 300 PHASE PHASMD 4628 F03 Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table 4628fd 13 LTM4628 Applications Information onto incoming clock phase as well. The CLKOUT signal can be connected to the MODE_PLLIN pin of the following stage to line up both the frequency and the phase of the entire system. Tying the PHASMD pin to INTVCC, SGND, or left floating generates a phase difference (between MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees, or 90 degrees respectively. A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin of each LTM4628 channel to different levels. Figure 3 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. The LTM4628 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 31 shows an example of parallel operation and pin connection. Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 4 shows this graph. 0.60 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.55 0.50 RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE (VOUT/VIN) 4628 F04 Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle 4628fd 14 LTM4628 Applications Information Frequency Selection and Phase-Locked Loop (MODE_PLLIN and fSET Pins) The LTM4628 device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the lower output voltages or lower duty cycle conversions at lower frequencies to improve efficiency by lowering power MOSFET switching losses. Higher output voltages or higher duty cycle conversions can be operated at higher frequencies to limit inductor ripple current. The efficiency graphs will show an operating frequency chosen for that condition. The LTM4628 switching frequency can be set with an external resistor from the fSET pin to SGND. An accurate 10µA current source into the resistor will set a voltage that programs the frequency or a DC voltage can be applied. Figure 5 shows a graph of frequency setting verses programming voltage. An external clock can be applied to the MODE_PLLIN pin from 0V to INTVCC over a frequency range of 400kHz to 780kHz. The clock input high threshold is 1.6V and the clock input low threshold is 0.5V. The LTM4628 has the PLL loop filter components on board. The frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock. Both regulators will operate in continuous mode while being externally clocked. The output of the PLL phase detector has a pair of complementary current sources that charge and discharge the internal filter network. When the external clock is applied the fSET frequency resistor is disconnected with an internal switch, and the current sources control the frequency adjustment to lock to the incoming external clock. When no external clock is applied, then the internal switch is on, thus connecting the external fSET frequency set resistor for free run operation. Minimum On-Time Minimum on-time tON is the smallest time duration that the LTM4628 is capable of turning on the top MOSFET on either channel. It is determined by internal timing delays, and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: VOUT > tON(MIN) VIN • FREQ If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the output ripple and current will increase. The minimum on-time can be increased by lowering the switching frequency. A good rule of thumb is to use an 110ns on-time. 900 800 FREQUENCY (kHz) 700 600 500 400 300 200 100 0 0 0.5 1 1.5 fSET PIN VOLTAGE (V) 2 2.5 4628 F05 Figure 5. Operating Frequency vs fSET Pin Voltage 4628fd 15 LTM4628 Applications Information INTVCC C10 4.7µF R2 10k PGOOD 5V TO 16V INTERMEDIATE BUS R1 10k C3 22µF 25V D1 5.1V ZENER C2 22µF 25V C1 22µF 25V R6 120k TEMP VOUTS1 RUN1 SW1 RUN2 VFB1 RTA 60.4k 1.5V fSET COMP2 PHASMD VOUTS2 VOUT2 SW2 PGOOD2 SGND GND DIFFP RFB 60.4k COMP1 R4 100k RAMP TIME tSOFTSTART = (CSS /1.3µA) • 0.6V 1.5V AT 8A C6 100µF 6.3V VFB2 LTM4628 TRACK2 RTB 60.4k PGOOD1 VOUT1 VIN TRACK1 MASTER CSS 0.1µF CLKOUT INTVCC EXTVCC MODE_PLLIN DIFFN DIFFOUT C8 470µF 6.3V 40.2k 1.2V AT 8A SLAVE PGOOD INTVCC C4 100µF 6.3V C7 470µF 6.3V R9 10k 4628 F06 Figure 6. Example of Output Tracking Application Circuit Output Voltage Tracking ⎛ 60.4k ⎞ VOUT _ SLAVE = ⎜1+ ⎟ • VTRACK RTA ⎠ ⎝ VTRACK is the track ramp applied to the slave’s track pin. VTRACK has a control range of 0V to 0.6V, or the internal reference voltage. When the master’s output is divided down with the same resistor values used to set the slave’s output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave’s regulation point. Voltage tracking is disabled when VTRACK is more than 0.6V. RTA in Figure 6 will be equal to the RFB for coincident tracking. Figure 7 shows the coincident tracking waveforms. MASTER OUTPUT OUTPUT VOLTAGE Output voltage tracking can be programmed externally using the TRACK pins. The output can be tracked up and down with another regulator. The master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider to implement coincident tracking. The LTM4628 uses an accurate 60.4k resistor internally for the top feedback resistor for each channel. Figure 6 shows an example of coincident tracking. Equations: SLAVE OUTPUT TIME 4628 F07 Figure 7. Output Coincident Tracking Waveform The TRACK pin of the master can be controlled by a capacitor placed on the master regulator TRACK pin to ground. A 1.3µA current source will charge the TRACK pin up to the reference voltage and then proceed up to INTVCC. After the 0.6V ramp, the TRACK pin will no longer be in control, and the internal voltage reference will control output regulation from the feedback divider. Foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. The TRACK pins are pulled low 4628fd 16 LTM4628 Applications Information when the RUN pin is below 1.2V. The total soft-start time can be calculated as: ⎛ C ⎞ tSOFT-START = ⎜ SS ⎟ • 0.6V ⎝ 1.3µA ⎠ Regardless of the mode selected by the MODE_PLLIN pin, the regulator channels will always start in pulse-skipping mode up to TRACK = 0.5V. Between TRACK = 0.5V and 0.54V, it will operate in forced continuous mode and revert to the selected mode once TRACK > 0.54V. In order to track with another channel once in steady state operation, the LTM4628 is forced into continuous mode operation as soon as VFB is below 0.54V regardless of the setting on the MODE_PLLIN pin. Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s TRACK pin. As mentioned above, the TRACK pin has a control range from 0 to 0.6V. The master’s TRACK pin slew rate is directly equal to the master’s output slew rate in Volts/Time. The equation: MR • 60.4k = RTB SR where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus RTB is equal the 60.4k. RTA is derived from equation: RTA = 0.6V V V VFB + FB − TRACK 60.4k RFB RTB where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since RTB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then RTA is equal to RFB with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 6. In ratiometric tracking, a different slew rate maybe desired for the slave regulator. RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then RTB = 76.8k. Solve for RTA to equal to 49.9k. Each of the TRACK pins will have the 1.3µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 60.4k is used then a 6.04k can be used to reduce the TRACK pin offset to a negligible value. Power Good The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a ±7.5% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. Stability Compensation The module has already been internally compensated for all output voltages. Table 4 is provided for most application requirements. LTpowerCAD is available for other control loop optimization. Run Enable The RUN pins have an enable threshold of 1.4V maximum, typically 1.25V with 150mV of hysteresis. They control the turn-on of each of the channels. These pins can be pulled up to VIN for 5V operation, or a 5V Zener diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5V input for enabling the channels. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tie together and controlled from a single control. See the Typical Application circuits in Figure 28. The RUN pin can also be left floating. The RUN pin has a 1µA pull-up current source that increases by an additional 4.5µA during ramp-up once above the on/off threshold. 4628fd 17 LTM4628 Applications Information INTVCC and EXTVCC The LTM4628 module has an internal 5V low dropout regulator that is derived from the input voltage. This regulator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 70mA, and typically uses ~30mA for powering the device at the maximum frequency. EXTVCC allows an external 5V supply to power the LTM4628 and reduce power dissipation from the internal low dropout 5V regulator. The power loss savings can be calculated by: inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance Z can be calculated: ZL = 2πfL, EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this 5V input to EXTVCC also to maintain a 5V gate drive level. VIN has to be sequenced on before EXTVCC, and EXTVCC must be sequenced off before VIN. where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: ZC = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount the power loss. Differential Remote Sense Amplifier Temperature Diode Monitoring An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either VOUTS1 or VOUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the VOUTS pins. Review the parallel schematics in Figure 31 and review Figure 2. The LTM4628 has an on board 1N4148 silicon diode at the TEMP pin that can be used to monitor temperature. The diode is mounted very close to internal power switches. The forward voltage of a silicon diode is temperature dependent based on the following equation: (VIN – 5V) • 30mA = PLOSS SW Pins The SW pins are generally for testing purposes by monitoring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combination is used, called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board ⎛ V ⎞ ID = IS • e ⎜ D ⎟ ⎝ η • VT ⎠ or I VD = η • VT • ln D IS where ID is the diode current, VD is the diode voltage, η is the ideality factor (typically close to 1.0) and IS (saturation current) is a process dependent parameter. VT can be broken out to: VT = k•T q where T is the diode junction temperature in Kelvin, q is the electron charge and k is Boltzmann’s constant. VT is approximately 26mV at room temperature (298K) and scales linearly with Kelvin temperature. It is this linear 4628fd 18 LTM4628 Applications Information temperature relationship that makes diodes suitable temperature sensors. The IS term in the equation above is the extrapolated current through a diode junction when the diode has zero volts across the terminals. The IS term varies from process to process, varies with temperature, and by definition must always be less than ID. Combining all of the constants into one term: KD = η•k q The below equations show that when currents are a decade apart the VD difference is 60mV; therefore the 10µA current source error will affect the diode forward voltage at temperature. kT/q = 26mV where KD = 8.62−5, and knowing ln(ID/IS) is always positive because ID is always greater than IS, leaves us with the equation that: I VD = T(KELVIN) • KD • ln D IS where VD appears to increase with temperature. It is common knowledge that a silicon diode biased with a current source has an approximate –2mV/°C temperature relationship (Figure 8), which is at odds with the equation. In fact, the IS term increases with temperature, reducing the ln(ID/IS) absolute value yielding an approximate –2mV/°C composite diode voltage slope. 1.4 It is important that the bias current source be accurate and powered from a high impedance source. This is because the forward voltage drop is also a function of the current through the diode. VD1 – VD2 = kT/q ln(ID1)/(ID2) where VD1 – VD2 is the difference in the diode forward voltage with the ID1 and ID2 current difference. Several 1N4148 diodes were tested with 100µA of current and Figure 9 shows the results. The 100µA current source provided the best repeatability for each diode. The tested diodes are very close to –2.2mV/°C to –2.4mV/°C slope while each are biased with 100µA through a 120k pull-up resistor to 12V. The Figure 9 graph can be used to calibrate and measure LTM4628 internal temperature by measuring the diode VD value. 0.8 ID = 10µA 0.7 1N4148 DIODE VOLTAGE (VD) DIODE VOLTAGE (VD) 1.2 1.0 0.8 0.6 0.4 0.2 0 –273 0.6 0.5 0.4 0.3 0.2 0.1 –173 –73 27 127 TEMPERATURE (°C) 227 4628 F08 Figure 8. Silicon Diode Voltage VD vs Temperature 0 –100 –50 0 50 100 TEMPERATURE (°C) 150 200 4628 F09 Figure 9. The 1N4148 Diode Voltage VD vs Temperature 4628fd 19 LTM4628 Applications Information Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD 51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board defined by JESD 51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below: 1 θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2 θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3 θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4 θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. A graphical representation of the aforementioned thermal resistances is given in Figure 10; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package. 4628fd 20 LTM4628 Applications Information JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD) CASE (TOP)-TO-AMBIENT RESISTANCE JUNCTION-TO-CASE (TOP) RESISTANCE JUNCTION JUNCTION-TO-BOARD RESISTANCE AMBIENT JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD (BOTTOM) RESISTANCE RESISTANCE BOARD-TO-AMBIENT RESISTANCE 4628 F10 µMODULE DEVICE Figure 10. Graphical Representation of JESD 51-12 Thermal Coefficients As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule package—as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within the LTM4628, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity— but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4628 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a softwaredefined JEDEC environment consistent with JESD 51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4628 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulate conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields a set of derating curves provided in other sections of this data sheet. After these laboratory tests have been performed the θJB and θBA are summed together to correlate quite well with the LTM4628 model with no airflow or heat sinking in a properly defined chamber. This θJB + θBA value is shown in the Pin Configuration section and should accurately equal the θJA value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. 4628fd 21 LTM4628 Applications Information The 1.0V and 3.3V power loss curves in Figures 11 and 12 can be used in coordination with the load current derating curves in Figures 13 to 24 for calculating an approximate θJA thermal resistance for the LTM4628 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with multiplicative factors according to the ambient temperature. The approximate factors are: 1.35 for 115°C and 1.4 for 120°C. The derating curves are plotted with VOUT1 and VOUT2 in parallel single output operation starting at 16A and the ambient temperature at 40°C. The output voltages are 1.0V, and 3.3V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 115°C to 120°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much temperature rise can be allowed. As an example, in Figure 14 the load current is derated to ~12A at ~80°C with no air or heat sink and the power loss for the 12V to 1.0V at 12A output is about 3.65W. The 3.65W loss is calculated with the ~2.7W room temperature loss from the 12V to 1.0V power loss curve at 12A, and the 1.35 multiplying factor at 120°C junction. If the 80°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 40°C divided by 3.65W equals a 10.9°C/W θJA thermal resistance. Table 2 specifies a 9.5°C/W to 10°C/W value which is very close. Table 2 and Table 3 provide equivalent thermal resistances for 1.0V and 3.3V outputs with and without airflow and heat sinking. The derived thermal resistances in Tables 2 and 3 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. The no-airflow θJA values have some variation from 9.5°C/W to 11°C/W depending on the 115°C to 120°C holding junction temperature. All other airflow thermal resistance values are more accurate. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. The BGA heat sinks are listed in Table 3. 4628fd 22 LTM4628 Applications Information 8 24V TO 1V 12V TO 1V 5V TO 1V 5 24V TO 3.3V POWER LOSS 12V TO 3.3V POWER LOSS 5V TO 3.3V POWER LOSS 7 CH1 AND CH2 COMBINED LOAD CURRENT 6 POWER LOSS (W) POWER LOSS (W) 6 4 3 2 5 4 3 2 1 2 4 6 8 10 12 14 0 16 0 2 4 4628 F11 Figure 11. 1V Power Loss 12 10 8 6 4 2 0 0 20 40 60 80 100 16 14 10 8 6 4 2 20 40 60 80 10 8 6 4 2 0 16 100 120 6 4 2 20 40 60 80 100 Figure 15. 24V to 1V Derating Curves, No Heat Sink 16 16 10 8 6 4 2 0 20 40 60 80 4628 F17 60 80 100 120 100 Figure 18. 24V to 1V Derating Curves with BGA Heat Sink 4628 F13 0 LFM 200 LFM 400 LFM 14 12 10 8 6 4 2 0 4628 F15 12 0 40 0 20 40 60 80 120 100 AMBIENT TEMPERATURE (°C) 0 LFM 200 LFM 400 LFM 14 20 Figure 13. 5V to 1V Derating Curves, No Heat Sink 120 120 Figure 16. 5V to 1V Derating Curves, with BGA Heat Sink 16 4628 F16 0 LFM 200 LFM 400 LFM 14 12 10 8 6 4 2 0 0 20 40 60 80 120 100 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) Figure 17. 12V to 1V Derating with BGA Heat Sink 4628 F12 8 0 0 AMBIENT TEMPERATURE (°C) 10 4628 F14 0 LFM 200 LFM 400 LFM 0 12 AMBIENT TEMPERATURE (°C) 12 0 14 12 0 120 CH1 AND CH2 COMBINED LOAD CURRENT CH1 AND CH2 COMBINED LOAD CURRENT Figure 14. 12V to 1V Derating Curves, No Heat Sink 14 12 0 LFM 200 LFM 400 LFM AMBIENT TEMPERATURE (°C) 16 10 Figure 12. 3.3V Power Loss CH1 AND CH2 COMBINED LOAD CURRENT CH1 AND CH2 CMBINED LOAD CURRENT 0 LFM 200 LFM 400 LFM 14 8 0 LFM 200 LFM 400 LFM 14 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 16 6 CH1 AND CH2 COMBINED LOAD CURRENT 0 CH1 AND CH2 COMBINED LOAD CURRENT 0 1 16 4628 F18 4628 F19 Figure 19. 5V to 3.3V Derating Curves, No Heat Sink 4628fd 23 LTM4628 0 LFM 200 LFM 400 LFM 14 12 10 8 6 4 2 0 0 20 40 60 80 16 14 12 10 8 6 4 2 0 120 100 0 LFM 200 LFM 400 LFM 20 0 AMBIENT TEMPERATURE (°C) 4628 F20 CH1 AND CH2 COMBINED LOAD CURRENT CH1 AND CH2 COMBINED LOAD CURRENT 10 8 6 4 2 0 20 40 80 0 LFM 200 LFM 400 LFM 14 12 10 8 6 4 2 0 120 100 0 20 60 80 120 100 40 60 80 100 120 AMBIENT TEMPERATURE (°C) 4628 F21 12 0 60 Figure 22. 5V to 3.3V Derating Curves with Heat Sink Figure 21. 24V to 3.3V Derating Curves, No Heat Sink 0 LFM 200 LFM 400 LFM 14 40 16 AMBIENT TEMPERATURE (°C) Figure 20. 12V to 3.3V Derating Curves, No Heat Sink 16 CH1 AND CH2 COMBINED LOAD CURRENT 16 CH1 AND CH2 COMBINED LOAD CURRENT CH1 AND CH2 COMBINED LOAD CURRENT Applications Information 16 4628 F22 0 LFM 200 LFM 400 LFM 14 12 10 8 6 4 2 0 0 20 40 60 80 120 100 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) 4628 F23 Figure 23. 12V to 3.3V Derating Curves, with Heat Sink 4628 F24 Figure 24. 24V to 3.3V Derating Curves with Heat Sink 4628fd 24 LTM4628 Applications Information Table 2. 1.0V Output DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W) Figures 13, 14, 15 5, 12, 24 Figure 11 0 None 9.5 to 11 Figures 13, 14, 15 5, 12, 24 Figure 11 200 None 6.4 Figures 13, 14, 15 5, 12, 24 Figure 11 400 None 5.6 Figures 16, 17, 18 5, 12, 24 Figure 11 0 BGA Heat Sink 9.0 to 10.5 Figures 16, 17, 18 5, 12, 24 Figure 11 200 BGA Heat Sink 6.5 Figures 16, 17, 18 5, 12, 24 Figure 11 400 BGA Heat Sink 4.8 DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W) Figures 19, 20, 21 5, 12, 24 Figure 12 0 None 9.5 to 11 Figures 19, 20, 21 5, 12, 24 Figure 12 200 None 6.75 Figures 19, 20, 21 5, 12, 24 Figure 12 400 None 6.4 Table 3. 3.3V Output Figures 22, 23, 24 5, 12, 24 Figure 12 0 BGA Heat Sink 9.0 to 10.5 Figures 22, 23, 24 5, 12, 24 Figure 12 200 BGA Heat Sink 6.3 Figures 22, 23, 24 5, 12, 24 Figure 12 400 BGA Heat Sink 4.8 HEAT SINK MANUFACTURER PART NUMBER WEBSITE Aavid Thermalloy 375424B00034G www.aavid.com 4628fd 25 LTM4628 Applications Information Table 4 Output Voltage Response vs Component Matrix (Refer to Figure 28) 0A to 4A Load Step Typical Measured Values COUT1 AND COUT2 CERAMIC VENDORS VALUE PART NUMBER COUT1 AND COUT2 BULK VENDORS VALUE AVX 10µF 35V 1812DD106KAT Sanyo POSCAP 470µF 2R5 Murata 22µF 16V GRM43ER61C226KE01 Sanyo POSCAP 470µF 6.3V TDK 100µF 6.3V C4532X5R0J107MZ Murata 100µF 6.3V GRM32ER60J107M AVX 100µF 6.3V 18126D107MAT VOUT (V) CIN (CERAMIC) CIN (BULK)* COUT1 (CERAMIC) COUT2 (BULK) 1 22µF × 3 47µF 100µF 470µF 1 22µF × 3 47µF 100µF × 4 1.2 22µF × 3 47µF 100µF 1.2 22µF × 3 47µF 100µF × 4 1.5 22µF × 3 47µF 100µF 1.5 22µF × 3 47µF 100µF × 4 1.8 22µF × 3 47µF 100µF 1.8 22µF × 3 47µF 100µF × 4 CFF (pF) 47 470µF 47 PART NUMBER CIN (BULK) PART NUMBER VENDORS 2R5TPD470M5 47µF 35V 35SVPD47M Sanyo Oscon VIN (V) DROOP (mV) 5,12 60 6TPD470M P-P Deviation RECOVERY (mV) TIME (µs) 120 30 LOAD STEP (A/µs) RFB (kΩ) Freq. (kHz) 4 90.9 400 5,12 50 100 20 4 90.9 400 5,12 60 120 30 4 60.4 500 5,12 55 110 20 4 60.4 500 5,12 60 120 30 4 40.2 500 47 5,12 66 120 20 4 40.2 500 5,12 60 120 30 4 30.1 500 47 5,12 65 130 20 4 30.1 500 470µF 470µF 2.5 22µF × 3 47µF 100µF × 4 5,12 70 140 30 4 19.1 500 2.5 22µF × 3 47µF 100µF 470µF 5,12 70 140 30 4 19.1 500 3.3 22µF × 3 47µF 100µF 470µF 5,12 80 160 30 4 13.3 700 3.3 22µF × 3 47µF 100µF 5 22µF × 3 47µF 100µF 47 220µF 47 5,12 100 200 30 4 13.3 700 47 12 125 200 30 4 8.25 750 * Bulk capacitance is optional if V IN has very low input impedance. 4628fd 26 LTM4628 Applications Information Figures 25 and 26 show thermal images of the LTM4628 in LGA package with or without BGA heat sink and no air flow or 200LFM air flow. These images equate to a paralleled 3.3V output at 16A design operating at 92% efficiency from 12V input. Figure 25a.12VIN to 3.3VOUT, 16A, No Heat Sink, No Air Flow Figure 25b.12VIN to 3.3VOUT, 16A, No Heat Sink, 200LFM Figure 25 Figure 26a. 12VIN to 3.3VOUT,16A, with Heat Sink, No Air Flow Figure 26b. 12VIN to 3.3VOUT,16A, with Heat Sink, 200LFM Figure 26 4628fd 27 LTM4628 Applications Information Safety Considerations • Place a dedicated power ground layer underneath the unit. The LTM4628 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The device does support thermal shutdown and over current protection. A temperature diode is provided for monitoring internal temperature. • To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. • Do not put via directly on the pad, unless they are capped or plated over. • Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit. Layout Checklist/Example The high integration of LTM4628 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. • For parallel modules, tie the VOUT, VFB, and COMP pins together. Use an internal layer to closely connect these pins together. The TRACK pin can be tied a common capacitor for regulator soft-start. • Use large PCB copper areas for high current paths, including VIN, GND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress. • Bring out test points on the signal pins for monitoring. Figure 27 gives a good example of the recommended layout. LGA and BGA PCB layouts are identical with the exception of circle pads for BGA (see Package Description). • Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize high frequency noise. CIN1 CIN2 VIN M L K GND GND J H G COUT1 SGND F COUT2 E D C B A 1 2 3 4 5 6 7 8 9 GND VOUT1 CNTRL 10 11 12 VOUT2 CNTRL 4628 F27 Figure 27. Recommended PCB Layout (LGA Shown, for BGA Use Circle Pads) 4628fd 28 LTM4628 Typical Applications INTVCC C10 4.7µF R2 10k PGOOD1 MODE_PLLIN 7V TO 16V INTERMEDIATE BUS R1 10k CIN1 22µF 25V D1 5.1V ZENER CIN2 22µF 25V CIN3 22µF 25V R6 120k EXTVCC PGOOD1 VOUT1 TEMP VOUTS1 RUN1 SW1 RUN2 VFB1 TRACK1 TRACK1 C5 0.1µF CLKOUT INTVCC VIN C9 0.1µF VFB2 LTM4628 TRACK2 TRACK2 COUT1 100µF 6.3V fSET COMP2 PHASMD VOUTS2 VOUT2 R4 100k SW2 R8 60.4k CFF 100pF 1.2V COMP1 GND DIFFP INTVCC PGOOD2 DIFFOUT DIFFN 1.5V AT 8A R6 40.2k 1.2V AT 8A C4 100µF 6.3V 10k SGND COUT2 470µF 6.3V C7 470µF 6.3V PGOOD2 4628 F28 Figure 28. 7VIN to 16VIN, 1.5V and 1.2V Outputs INTVCC C10 4.7µF PGOOD1 7V TO 16V INTERMEDIATE BUS R1 10k C3 22µF 25V D1 5.1V ZENER R2 5k MODE_PLLIN C11 22µF 25V C2 22µF 25V C1 22µF 25V R6 120k TRACK1 CLKOUT INTVCC VIN VOUT1 TEMP VOUTS1 RUN1 SW1 RUN2 VFB1 TRACK1 VFB2 LTM4628 TRACK2 C9 0.1µF EXTVCC PGOOD1 COMP1 fSET COMP2 PHASMD VOUTS2 SW2 PGOOD2 SGND GND DIFFP DIFFN + C8 470µF 6.3V C4 100µF 6.3V + C7 470µF 6.3V R5 40.2k VOUT2 R4 100k C6 100µF 6.3V PGOOD1 1.5V AT 16A DIFFOUT 4628 F29 Figure 29. Two Phases, 1.5V at 16A Design 4628fd 29 LTM4628 Typical Applications INTVCC C10 4.7µF R2 10k PGOOD1 5V TO 16V INTERMEDIATE BUS D1 5.1V ZENER MODE_PLLIN R1 10k C3 22µF 25V C2 22µF 25V C1 22µF 25V R6 120k CLKOUT INTVCC EXTVCC PGOOD1 VOUT1 VIN TEMP VOUTS1 RUN1 SW1 RUN2 VFB1 TRACK1 C5 0.1µF R9 60.4k 1.2V R7 90.9k VFB2 LTM4628 TRACK2 C6 100µF 6.3V R8 90.9k COMP1 fSET COMP2 PHASMD VOUTS2 VOUT2 R4 100k SW2 PGOOD2 GND DIFFP DIFFN 1.2V AT 8A C8 470µF 6.3V R5 60.4k 1V AT 8A INTVCC 10k SGND + C4 100µF 6.3V + C7 470µF 6.3V PGOOD2 DIFFOUT 4628 F30 Figure 30. 1.2V and 1V Output Tracking 4628fd 30 LTM4628 typical applications INTVCC CLK1 7V TO 16V INTERMEDIATE BUS R1 10k RUN C3 22µF 25V MODE_PLLIN C2 22µF 25V C1 22µF 25V R6 10k R2 5k PGOOD1 EXTVCC PGOOD1 VIN TRACK1 D1 5.1V ZENER CLKOUT INTVCC C10 4.7µF VOUT1 TEMP VOUTS1 RUN1 RUN2 SW1 VFB1 TRACK1 VFB2 LTM4628 TRACK2 COMP2 PHASMD VOUTS2 PGOOD2 GND DIFFP DIFFN C4 100µF 6.3V + C7 470µF 6.3V COMP SW2 SGND C8 470µF 6.3V R5 60.4k VOUT2 R4 100k + VFB COMP1 fSET C6 100µF 6.3V PGOOD1 DIFFOUT 1.2V AT 32A C16 4.7µF CLK1 MODE_PLLIN 7V TO 16V INTERMEDIATE BUS C12 22µF 25V C15 22µF 25V C5 22µF 25V R9 10k CLKOUT INTVCC EXTVCC PGOOD1 VIN RUN1 TRACK1 VOUT1 TEMP VOUTS1 RUN1 SW1 RUN2 VFB1 TRACK1 VFB2 LTM4628 TRACK2 C19 0.22µF PGOOD1 COMP2 PHASMD VOUTS2 SW2 PGOOD2 SGND GND DIFFP DIFFN DIFFOUT C14 470µF 6.3V C17 100µF 6.3V + C18 470µF 6.3V COMP VOUT2 R10 100k + VFB COMP1 fSET C13 100µF 6.3V PGOOD1 4628 F31 INTVCC Figure 31. 4-Phase, 1.2V at 32A 4628fd 31 LTM4628 package description Table 5. LTM4628 Component Pinout PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VOUT1 B1 VOUT1 C1 VOUT1 D1 GND E1 GND F1 GND A2 VOUT1 B2 VOUT1 C2 VOUT1 D2 GND E2 GND F2 GND A3 VOUT1 B3 VOUT1 C3 VOUT1 D3 GND E3 GND F3 GND A4 VOUT1 B4 VOUT1 C4 VOUT1 D4 GND E4 GND F4 MODE_PLLIN A5 VOUT1 B5 VOUT1 C5 VOUT1S D5 VFB1 E5 TRACK1 F5 RUN1 A6 GND B6 GND C6 fSET D6 SGND E6 COMP1 F6 SGND A7 GND B7 GND C7 SGND D7 VFB2 E7 COMP2 F7 SGND A8 VOUT2 B8 VOUT2 C8 VOUT2S D8 TRACK2 E8 DIFFP F8 DIFFOUT A9 VOUT2 B9 VOUT2 C9 VOUT2 D9 GND E9 DIFFN F9 RUN2 A10 VOUT2 B10 VOUT2 C10 VOUT2 D10 GND E10 GND F10 GND A11 VOUT2 B11 VOUT2 C11 VOUT2 D11 GND E11 GND F11 GND A12 VOUT2 B12 VOUT2 C12 VOUT2 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 SW1 H2 GND J2 VIN K2 VIN L2 VIN M2 VIN G3 GND H3 GND J3 VIN K3 VIN L3 VIN M3 VIN G4 PHASMD H4 GND J4 VIN K4 VIN L4 VIN M4 VIN G5 CLKOUT H5 GND J5 GND K5 GND L5 VIN M5 VIN G6 SGND H6 GND J6 TEMP K6 GND L6 VIN M6 VIN G7 SGND H7 GND J7 EXTVCC K7 GND L7 VIN M7 VIN G8 PGOOD2 H8 INTVCC J8 GND K8 GND L8 VIN M8 VIN G9 PGOOD1 H9 GND J9 VIN K9 VIN L9 VIN M9 VIN G10 GND H10 GND J10 VIN K10 VIN L10 VIN M10 VIN G11 SW2 H11 GND J11 VIN K11 VIN L11 VIN M11 VIN G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND Package Photos 15mm 4.32mm 15mm 15mm LGA 4.92mm 15mm BGA 4628fd 32 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 PACKAGE TOP VIEW 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 4 0.6350 0.0000 0.6350 PAD 1 CORNER 15 BSC 1.9050 X 15 BSC Y DETAIL B 4.22 – 4.42 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE LAND DESIGNATION PER JESD MO-222, SPP-010 SYMBOL TOLERANCE aaa 0.15 bbb 0.10 eee 0.05 6. THE TOTAL NUMBER OF PADS: 144 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 12 11 TRAY PIN 1 BEVEL COMPONENT PIN “A1” PADS SEE NOTES 1.27 BSC 13.97 BSC 0.12 – 0.28 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 DETAIL A 0.27 – 0.37 SUBSTRATE eee S X Y DETAIL B 0.630 ±0.025 SQ. 143x aaa Z 3.95 – 4.05 MOLD CAP Z 5.7150 4.4450 4.4450 5.7150 6.9850 (Reference LTC DWG # 05-08-1843 Rev Ø) bbb Z aaa Z 6.9850 LGA Package 144-Lead (15mm × 15mm × 4.32mm) 10 7 6 5 LTMXXXXXX µModule PACKAGE BOTTOM VIEW 8 13.97 BSC 4 3 2 LGA 144 0709 REV Ø 1 DETAIL A PACKAGE IN TRAY LOADING ORIENTATION 9 3x, C (0.22 x45°) A B C D E F G H J K L M DIA 0.630 PAD 1 LTM4628 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. LGA Package 144-Lead (15mm × 15mm × 4.32mm) (Reference LTC DWG # 05-08-1843 Rev Ø) 4628fd 33 aaa Z 0.630 ±0.025 Ø 144x 0.0 E PACKAGE TOP VIEW 3.1750 3.1750 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 4 0.6350 0.0000 0.6350 PIN “A1” CORNER 1.9050 Y 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 X D aaa Z SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee H1 SUBSTRATE NOM 4.92 0.60 4.32 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.32 4.00 MAX 5.12 0.70 4.42 0.90 0.66 NOTES DETAIL B PACKAGE SIDE VIEW 0.37 4.05 0.15 0.10 0.20 0.30 0.15 TOTAL NUMBER OF BALLS: 144 0.27 3.95 MIN 4.72 0.50 4.22 0.60 0.60 b1 DIMENSIONS ddd M Z X Y eee M Z DETAIL A Øb (144 PLACES) DETAIL B H2 MOLD CAP ccc Z A1 A2 A (Reference LTC DWG # 05-08-1921 Rev Ø) // bbb Z 34 Z BGA Package 144-Lead (15mm × 15mm × 4.92mm) Z e b 11 10 9 7 G 6 e 5 PACKAGE BOTTOM VIEW 8 4 3 2 1 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 TRAY PIN 1 BEVEL BGA 144 0312 REV Ø PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX µModule 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu 5. PRIMARY DATUM -Z- IS SEATING PLANE BALL DESIGNATION PER JESD MS-028 AND JEP95 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN “A1” 3 SEE NOTES F b 12 DETAIL A A B C D E F G H J K L M PIN 1 LTM4628 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. BGA Package 144-Lead (15mm × 15mm × 4.92mm) (Reference LTC DWG # 05-08-1921 Rev Ø) 4628fd 6.9850 5.7150 4.4450 4.4450 5.7150 6.9850 LTM4628 Revision History REV DATE DESCRIPTION PAGE NUMBER A 06/11 Updated Typical Application Efficiency graph Updated Pin Configuration 3, 4 Updated Pin Functions section 7, 8 Updated Decoupling Requirements table 9 Updated Figure 3 13 Updated Figures 29 and 31 C D 7/11 8/12 11/12 2 Updated Electrical Characteristics Various text updated in Applications Information section B 1 11 to 22 30, 32 Changed Typical value of RFBHI1, RFBHI2 to 60.4kΩ 3 Updated Decoupling Requirements table 9 Updated Pin Configuration to add the BGA package. 2 Added VD1 – VD2 formula. 19 Updated the Pin Configuration section. 2 4628fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTM4628 Typical Application 5V C10 4.7µF R2 10k PGOOD1 24V C8 10µF 35V R1 10k MODE_PLLIN CLKOUT INTVCC C3 10µF 35V D1 5.1V ZENER C2 10µF 35V C1 10µF 35V R6 240k VOUTS1 RUN1 SW1 RUN2 VFB1 INTVCC C9 0.1µF R8 13.3k COMP1 fSET COMP2 PHASMD VOUTS2 VOUT2 SW2 SGND GND DIFFP DIFFN R6 8.25k 3.3V AT 8A 3.3V 10k PGOOD2 DIFFOUT COUT2 470µF 6.3V COUT1 100µF 6.3V VFB2 LTM4628 TRACK2 TRACK2 5V AT 8A VOUT1 TEMP TRACK1 TRACK1 C5 0.1µF EXTVCC PGOOD1 VIN C4 100µF 6.3V C7 470µF 6.3V PGOOD2 4628 F32 Figure 32. 24VIN, 5V and 3.3V Outputs Related Parts PART NUMBER DESCRIPTION COMMENTS LTM4619 Dual 26VIN, 4A DC/DC µModule Regulator 4.5V ≤ VIN ≤ 26.5V; 0.8V ≤ VOUT ≤ 5V LTM4615 Triple Low VIN, 4A DC/DC µModule Regulator 2.375 ≤ VIN ≤ 5.5V; Two 4A and One 1.5A Output LTM4616 Dual 8A, Low VIN, DC/DC µModule Regulator 2.7V ≤ VIN ≤ 5.5V; 0.6V ≤ VOUT ≤ 5V LTM4614 Dual 4A, Low VIN, DC/DC µModule Regulator 2.375V ≤ VIN ≤ 5.5V; 0.8V ≤ VOUT ≤ 5V LTM4627 15A DC/DC µModule Regulator 4.5V ≤ VIN ≤ 20V; 0.6V ≤ VOUT ≤ 5V 4628fd 36 Linear Technology Corporation LT 1112 REV D • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2010