L6234 ® THREE PHASE MOTOR DRIVER SUPPLY VOLTAGE FROM 7 TO 52V 5A PEAK CURRENT RDS ON 0.3Ω TYP. VALUE AT 25°C CROSS CONDUCTION PROTECTION TTL COMPATIBLE DRIVER OPERATING FREQUENCY TO 50KHz THERMAL SHUTDOWN INTRINSIC FAST FREE WHEELING DIODES INPUT AND ENABLE FUNCTION FOR EVERY HALF BRIDGE 10V EXTERNAL REFERENCE AVAILABLE DESCRIPTION The L6234 is a triple half bridge to drive a brushless motor. It is realized in Multipower BCD technology which combines isolated DMOS power transistors with CMOS and Bipolar circuits on the same chip. By using mixed technology it has been possible to optimize the logic circuitry and the power stage to achieve the best possible performance. The output DMOS transistors can sustain a very high current due to the fact that the DMOS structure is not affected by the second breakdown ef- POWER DIP (16+2+2) PowerSO20 ORDERING NUMBERS: L6234 (POWER DIP 16+2+2) L6234PD (PowerSO20) fect, the RMS maximum current is practically limited by the dissipation capability of the package. All the logic inputs are TTL, CMOS and µP compatible. Each channel is controlled by two separate logic input. L6234 is available in 20 pin POWER DIP package (16+2+2) and in PowerSO20. PIN CONNECTION (Top view) OUT1 1 20 OUT2 IN1 2 19 IN2 GND 1 20 GND SENSE1 2 19 SENSE2 EN2 3 18 VBOOT EN1 3 18 EN2 VS 4 17 SENSE1 IN2 4 17 Vcp GND 5 16 GND OUT2 5 16 VREF GND OUT1 6 15 OUT3 IN1 7 14 IN3 EN1 8 13 EN3 VS 9 12 VS 11 GND GND VS EN3 IN3 OUT3 6 15 7 14 8 13 SENSE2 VBOOT 9 12 VCP 10 11 VREF GND 10 D94IN129A D98IN848 POWER DIP (16+2+2) August 2003 PowerSO20 1/10 L6234 BLOCK DIAGRAM 0.22µF 10nF VCP 1µF VREF VBOOT 1N4148 VREF= 10V CHARGE PUMP Vs 7 to 52V IN1 TH1 0.1 µF OUT1 EN1 TL1 IN2 TH2 OUT2 EN2 TL2 SENSE1 THERMAL PROTECTION IN3 TH3 OUT3 EN3 TL3 SENSE2 RSENSE GND D95IN309A 2/10 100µF L6234 THERMAL DATA Symbol DIP16+2+2 PowerSO20 Unit Thermal Resistance, Junction to Pin 12 – °C/W Rth j-amb1 Thermal Resistance, Junction to Ambient (see Thermal Characteristics) 40 – °C/W Rth j-amb2 Thermal Resistance, Junction to Ambient (see Thermal Characteristics) 50 – °C/W Rth j-case Thermal Resistance Junction-case – 1.5 °C/W Rth j-pin Parameter THERMAL CHARACTERISTICS Rth j-pins DIP16+2+2. The thermal resistance is referred to the thermal path from the dissipating region on the top surface of the silicon chip, to the points along the four central pins of the package, at a distance of 1.5 mm away from the stand-offs. Rth j-amb1 If a dissipating surface, thick at least 35 µm, and with a surface similar or bigger than the one shown, is created making use of the printed circuit. Such heatsinking surface is considered on the bottom side of an horizontal PCB (worst case). Rth j-amb2 If the power dissipating pins (the four central ones), as well as the others, have a minimum thermal connection with the external world (very thin strips only) so that the dissipation takes place through still air and through the PCB itself. It is the same situation of point above, without any heatsinking surface created on purpose on the board. Additional data on the PowerDip and the PowerSO20 package can be found in: Application Note AN467: Thermal Characteristics of the PowerDip 20,24 Packages Soldered on 1,2,3 oz. Copper PCB Application Note AN668: A New High Power IC Surface Mount Package: PowerSO20 Power IC Packaging from Insertion to Surface Mounting. Figure 1: Printed Heatsink 3/10 L6234 ABSOLUTE MAXIMUM RATINGS Symbol VS Power Supply Voltage Parameter Value 52 Unit V VIN,VEN Input Enable Voltage – 0.3 to 7 V Ipeak Pulsed Output Current (note 1) 5 A VSENSE Sensing Voltage (DC Voltage) -1 to 4 V 62 V Vb VOD fC VREF Bootstrap Peak Voltage Differential Output Voltage (between any of the 3 OUT pins) 60 V Commutation Frequency 50 KHz Reference Voltage Ptot Total Power Dissipation L6234PD Tamb = 70°C Ptot Total Power Dissipation L6234 Tamb = 70°C Tstg, Tj Storage and Junction Temperature Range 12 V 2.3 W 1.6 (*) W -40 to 150 °C Note 1: Pulse width limited only by junction temperature and the transient thermal impedance (*) Mounted on board with minimized copper area RECOMMENDED OPERATING CONDITIONS Symbol VS Parameter Supply Voltage Value Unit 7 to 42 V VOD Peak to Peak Differential Voltage (between any of the 3 OUT pins) 52 V Iout DC Output Current Power SO20 (Tamb = 25°C) 4 A DC Output Current Power DIP (Tamb = 25°C) with infinite heatsink VSENSE Tj 2.8 A Sensing Voltage (pulsed tw < 300nsec) -4 to 4 V Sensing Voltage (DC) -1 to 1 V -40 to 125 °C Junction Temperature Range PIN FUNCTIONS Powerdip PowerSO20 Name 1 20 10 6 5 15 OUT 1 OUT 2 OUT 3 2 19 9 7 4 14 IN 1 IN 2 IN 3 Logic input of channels 1/2/3. A logic HIGH level (when the corresponding EN pin is HIGH) switches ON the upper DMOS Power Transistor, while a logic LOW switches ON the corresponding low side DMOS Power. 3 18 8 8 3 13 EN 1 EN 2 EN 3 Enable of the channels 1/2/3. A logic LOW level on this pin switches off both power DMOS of the related channel. 4,7 9, 12 Vs 14 19 SENSE2 A resistance Rsense connected to this pin provides feedback for motor current control for the bridge 3. 17 2 SENSE1 A resistance Rsense connected to this pin provides feedback for motor current control for the bridges 1 and 2. 11 16 Vref Internal Voltage Reference. A capacitor connected from this pin to GND increases the stability of the Power DMOS drive circuit. 12 17 Vcp Bootstrap Oscillator. Oscillator output for the external charge pump. 13 18 VBOOT Overvoltage input to drive the upper DMOS 5,6 15,16 1,10 11,20 GND Common Ground Terminal. In Powerdip and SO packages these pins are used to dissipate the heat forward the PCB. 4/10 Function Output of the channels 1/2/3. Power Supply Voltage. L6234 ELECTRICAL CHARACTERISTICS (Vs = 42V ; Tj = 25°C unless otherwise specified) Symbol Parameter VS Supply Voltage Vref Reference Voltage IS Quiescent Supply Current TS Thermal Shutdown TD Dead Time Protection Test Condition Min. Typ. 7 Max. Unit 52 V 10 V 6.5 mA 150 °C 300 ns OUTPUT DMOS TRANSISTOR Symbol IDSS RDS (ON) Parameter Test Condition Min. Typ. Leakage Current ON Resistance Max. Unit 1 mA Ω 0.3 SOURCE DRAIN DIODE Symbol Parameter VSD Forward ON Voltage TRR Reverse Recovery Time Tpr Forward Recovery Time Test Condition Min. Typ. Max. Unit ISD = 4A; EN = LOW 1.2 V IF = 4A 900 ns 200 ns LOGIC LEVELS Symbol Parameter Test Condition Min. VINL, VENL Input LOW Voltage -0.3 VINH, VENH Input HIGH Voltage 2 IINL, IENL Input LOW Current VIN,VEN = L IINH, IENH Input HIGH Current VIN,VEN = H CIRCUIT DESCRIPTION L6234 is a triple half bridge designed to drive brushless DC motors. Each half bridge has 2 power DMOS transistors with RdsON = 0.3Ω. The 3 half bridges can be controlled independently by means of the 3 inputs IN1, IN2, IN3 and the 3 inputs EN1, EN2, and Typ. 30 Max. Unit 0.8 V 7 V -10 µA µA EN3. An external connection to the 3 common low side DMOS sources is provided to connect a sensing resistor for constant current chopping application. The driving stage and the logic stage are designed to work from 7V to 52V. 5/10 L6234 Figure 1. Quiescent Current vs. Supply Voltage. Figure 2. Normalized Quiescent Current vs. switching frequency. Iq [m A ] Iq/(Iq@500Hz) 10 1.75 9 Tj = 130°C T j = -4 0 °C Tj = 25°C 8 1.5 T j = 25 °C 7 6 Tj = -40°C T j = 1 00 °C 1.25 5 T j = 1 30 °C 4 3 1 2 1 0 0 8 16 24 V s [V ] 32 40 0.75 48 Figure 3. Typical RDS (ON) vs. Supply Voltage. R D S (O N ) [ Ω ] 0 .7 0 10 20 30 fsw [kHz] 40 50 60 Figure 4. Source Drain Forward ON voltage vs. Junction Temperature. VSD [V] 2 0 .6 1.75 T j = 1 3 0 °C 1.5 0 .5 1.25 0 .4 T j = 2 5 °C 1 0 .3 0.75 T j= - 4 0 ° C 0 .2 0.5 Iout=4A 0 .1 0 Io u t = 4 A 0 8 16 0.25 24 32 V s [V ] 40 0 -50 48 -25 0 25 50 Tj [°C ] 75 100 125 150 Figure 6. Reference Voltage vs. Supply Voltage. Figure 5. Typical Diode Forward ON characteristics IS D [A ] Vref [V ] 5 12 T j = 25 °C 10 4 D M O S (O N ) D M O S (O FF) 8 3 6 2 4 T j = 2 5°C 1 2 0 0 6/10 0.5 1 V S D [V ] 1.5 2 0 0 10 20 30 V s [V ] 40 50 L6234 Figure 7. Reference Voltage vs. Junction Temperature. Figure 8. PowerSO-20 Transient Thermal Resistance V re f [V ] 11 V s = 5 2V 10 V s = 2 4V 9 8 V s = 1 0V 7 6 Vs = 7V 5 4 3 2 1 0 -50 -25 0 25 50 T j [°C ] 75 1 00 1 25 1 50 Figure 9. PowerSO-20 Thermal Resistance (Mounted on Aluminium substrate) Figure 10. PowerSO-20 Thermal Resistance (Mounted on FR4 monolayer substrate) Figure 11. PowerSO-20: with external heatsink Figure 12. Thermal Impedance of PowerSO-20 and standard SO20 7/10 L6234 DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.6 0.1 0.142 0.3 a2 0.004 0.012 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 D (1) 15.8 16 0.622 0.630 0.386 D1 9.4 9.8 0.370 E 13.9 14.5 0.547 e 1.27 e3 E1 (1) 0.570 0.450 11.1 E2 0.429 0.437 2.9 0.114 E3 5.8 6.2 0.228 0.244 G 0 0.1 0.000 0.004 H 15.5 15.9 0.610 h L 0.626 1.1 0.8 JEDEC MO-166 0.043 1.1 N Weight: 1.9gr 0.050 11.43 10.9 OUTLINE AND MECHANICAL DATA MAX. 0.031 0.043 8˚ (typ.) S 8˚ (max.) T 10 0.394 PowerSO20 (1) “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions: “E”, “G” and “a3”. N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane -C- S SEATING PLANE L G E2 E1 BOTTOM VIEW C (COPLANARITY) T E3 1 h x 45 10 PSO20MEC D1 0056635 8/10 L6234 mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.10 0.280 I 5.10 0.201 L OUTLINE AND MECHANICAL DATA 3.30 0.130 Powerdip 20 Z 1.27 0.050 9/10 L6234 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 10/10