LINER LTC1654CGN Dual 14-bit rail-to-rail dac in 16-lead ssop package Datasheet

Final Electrical Specifications
LTC1654
Dual 14-Bit Rail-to-Rail DAC
in 16-Lead SSOP Package
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FEATURES
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April 2000
DESCRIPTIO
The LTC®1654 is a dual, rail-to-rail voltage output, 14-bit
digital-to-analog converter (DAC). It is available in a
16-lead narrow SSOP package, making it the smallest dual
14-bit DAC available. It includes output buffer amplifiers
and a flexible serial interface.
14-Bit Monotonic Over Temperature
Individually Programmable Speed/Power:
3.5µs Settling Time at 750µA
8µs Settling Time at 450µA
Maximum Update Rate: 0.9MHz
Smallest Dual 14-Bit DAC: 16-Lead Narrow
SSOP Package
Buffered True Rail-to-Rail Voltage Outputs
3V to 5V Single Supply Operation
User Selectable Gain
Power-On Reset and Clear Function
Schmitt Trigger On Clock Input Allows Direct
Optocoupler Interface
The LTC1654 has REFHI pins for each DAC that can be
driven up to VCC. The output will swing from 0V to VCC in
gain of 1 configuration or VCC/2 in gain of 1/2 configuration. It operates from a single 2.7V to 5.5V supply.
The LTC1654 has two programmable speeds: a FAST and
SLOW mode with ±1LSB settling times of 3.5µs or 8µs
respectively and supply currents of 750µA and 450µA in
the two modes. The LTC1654 also has shutdown capability, power-on reset and clear function to 0V.
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APPLICATIO S
, LTC and LT are registered trademarks of Linear Technology Corporation.
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Digital Calibration
Industrial Process Control
Automatic Test Equipment
Offset/Gain Adjustment
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BLOCK DIAGRA
CS/LD
SCK
REFHI B
CONTROL
LOGIC
INPUT
LATCH
SDI
DAC
REGISTER
+
DAC B
VOUT B
–
32-BIT
SHIFT
REGISTER
X1/X1/2 B
REFHI A
INPUT
LATCH
DAC
REGISTER
+
DAC A
VOUT A
–
SDO
CLR
POWER-ON
RESET
X1/X1/2 A
REFLO B
REFLO A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1654 BD
1
LTC1654
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AXI U
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
VCC to GND .............................................. – 0.5V to 7.5V
TTL Input Voltage, REFHI,
REFLO, X1/X1/2 ........................................ – 0.5V to 7.5V
VOUT, SDO .................................. – 0.5V to (VCC + 0.5V)
Operating Temperature Range
LTC1654C ............................................. 0°C to 70°C
LTC1654I ........................................ – 40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
TOP VIEW
X1/X1/2 B
1
16 VCC
CLR
2
15 VOUT B
SCK
3
14 REFHI B
SDI
4
13 REFLO B
CS/LD
5
12 AGND
DGND
6
11 REFLO A
SDO
7
10 REFHI A
X1/X1/2 A
8
9
LTC1654CGN
LTC1654IGN
GN PART MARKING
VOUT A
1654
1654I
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/ W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V
(VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
Monotonicity
DNL
Differential Nonlinearity
●
14
●
14
Guaranteed Monotonic (Note 2)
●
INL
Integral Nonlinearity
Integral Nonlinearity (Note 2)
●
ZSE
Zero Scale Error
C Grade
I Grade
●
●
VOS
Offset Error
Measured at Code 50, C Grade
Measured at Code 50, I Grade
●
●
VOSTC
Offset Error Tempco
Bits
Bits
0
±1
LSB
±4
LSB
6.5
9.0
mV
mV
±6.5
±9.0
mV
mV
±15
Gain Error
µV/°C
±15
●
Gain Error Drift
5
LSB
ppm/°C
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
●
5.5
V
ICC
Supply Current (SLOW/FAST)
2.7V ≤ VCC ≤ 5.5V (Note 5) SLOW
2.7V ≤ VCC ≤ 5.5V (Note 5) FAST
2.7V ≤ VCC ≤ 3.3V (Note 5) SLOW
2.7V ≤ VCC ≤ 3.3V (Note 5) FAST
In Shutdown (Note 5)
●
●
●
●
●
2.7
450
750
250
450
7
800
1300
500
900
30
µA
µA
µA
µA
µA
Short-Circuit Current Low
VOUT Shorted to GND
●
70
120
mA
Short-Circuit Current High
VOUT Shorted to VCC
●
80
120
mA
Output Impedance to GND
Input Code = 0
●
40
200
Ω
Output Line Regulation
Input Code = 16383, VCC = 2.7V to 5.5V,
VREF = 2.048V
●
2.25
mV/V
Op Amp DC Performance
2
LTC1654
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VCC = 2.7V to 5.5V, VOUT A, VOUT B unloaded, REFHI A, REFHI B = 4.096V
(VCC = 5V), REFHI A, REFHI B = 2.048V (VCC = 2.7V), REFLO = 0V, X1/X1/2 = 0V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Performance
Voltage Output Slew Rate
(Note 3) SLOW
(Note 3) FAST
Voltage Output Settling Time
(Note 4) to ±1LSB, SLOW
(Note 4) to ±1LSB, FAST
Digital Feedthrough
(Note 8)
Midscale Glitch Impulse
DAC Switch Between 8000 and 7FFF
20
nV•s
Output Noise Voltage Density
at 1kHz, SLOW
at 1kHz, FAST
540
320
nV/√Hz
nV/√Hz
VIH
Digital Input High Voltage
VCC = 5V
●
VIL
Digital Input Low Voltage
VCC = 5V
●
VOH
Digital Output High Voltage
VCC = 5V, IOUT = – 1mA, DOUT Only
●
VOL
Digital Output Low Voltage
VCC = 5V, IOUT = 1mA, DOUT Only
●
VIH
Digital Input High Voltage
VCC = 3V
●
VIL
Digital Input Low Voltage
VCC = 3V
●
VOH
Digital Output High Voltage
VCC = 3V, IOUT = – 1mA, DOUT Only
●
VOL
Digital Output Low Voltage
VCC = 3V, IOUT = 1mA, DOUT Only
●
0.4
V
ILEAK
Digital Input Leakage
VIN = GND to VCC
●
±10
µA
CIN
Digital Input Capacitance
(Note 6)
10
pF
●
●
0.20
1.25
V/µs
V/µs
µs
µs
8.0
3.5
1
nV•s
Digital I/O
2.4
V
0.8
VCC – 0.75
V
V
0.4
2.4
V
V
0.8
VCC – 0.75
V
V
Reference Input
Reference Input Resistance
REFHI to REFLO
●
30
Reference Input Range
(Notes 6, 7)
●
0
Reference Input Current
In Shutdown
●
60
kΩ
VCC
V
1
µA
Switching Characteristics (VCC = 4.5V to 5.5V)
t1
SDI Valid to SCK Setup
t2
SDI Valid to SCK Hold
(Note 6)
●
0
ns
t3
SCK High Time
(Note 6)
●
15
ns
t4
SCK Low Time
(Note 6)
●
15
ns
t5
CS/LD Pulse Width
(Note 6)
●
15
ns
t6
LSB SCK to CS/LD
(Note 6)
●
10
ns
t7
CS/LD Low to SCK
(Note 6)
●
10
ns
t8
SD0 Output Delay
CLOAD = 100pF
●
5
t9
SCK Low to CS/LD Low
(Note 6)
●
10
ns
●
30
ns
100
ns
Switching Characteristics (VCC = 2.7V to 5.5V)
t1
SDI Valid to SCK Setup
t2
SDI Valid to SCK Hold
●
45
ns
(Note 6)
●
0
ns
t3
t4
SCK High Time
(Note 6)
●
20
ns
SCK Low Time
(Note 6)
●
20
ns
t5
CS/LD Pulse Width
(Note 6)
●
20
ns
t6
LSB SCK to CS/LD
(Note 6)
●
15
ns
t7
CS/LD Low to SCK
(Note 6)
●
15
t8
SDO Output Delay
CLOAD = 100pF
●
5
t9
SCK Low to CS/LD Low
(Note 6)
●
15
ns
150
ns
ns
3
LTC1654
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity is defined from code 50 to code 16383 (full scale).
See Applications Information.
Note 3: 100pF Load Capacitor
Note 4: DAC switched between code 200 and code 16383.
Note 5: Digital inputs at 0V or VCC.
Note 6: Guaranteed by design.
Note 7: VOUT can only swing from (GND +VOS) to (VCC –VOS)
when output is unloaded. See Applications Information.
Note 8: CS/LD = 0, VOUT = 4.096 and data is being clocked in.
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PI FU CTIO S
signal is enabled, so the data can be clocked in. When
CS/LD is pulled high, the control/address bits are
decoded.
X1/X1/2 B, X1/X1/2 A (Pins 1, 8): The Gain of 1 or Gain of
1/2 Pin. When this pin is tied to VOUT, the output will swing
up to REFHI/2 and when this pin is tied to REFLO, the
output will swing up to REFHI. These pins should not be
left floating.
DGND/AGND (Pins 6, 12): Digital and Analog Grounds.
CLR (Pin 2): The Asynchronous Clear Input.
SDO (Pin 7): The output of the shift register that becomes
valid on the rising edge of the serial clock.
SCK (Pin 3): The TTL Level Input for the Serial Interface
Clock.
VOUT A/B (Pins 9, 15): The Buffered DAC Outputs.
REFHI A/B (Pins 10, 14): The Reference High Inputs of the
LTC1654. There is a gain of 1 from this pin to the output
in a gain of 1 configuration. In a gain of 1/2 configuration,
there is a gain of 1/2 from this pin to VOUT.
SDI (Pin 4): The TTL Level Input for the Serial Interface
Data. Data on the SDI pin is latched into the shift register
on the rising edge of the serial clock. The LTC1654 requires a 24-bit word. The first 8 bits are control/address
followed by 16 data bits. The last two of the 16 data bits are
don’t cares. If daisy-chaining is desired, then a 32-bit data
word can be used with the first 8 being don’t cares and the
following 24 bits as above.
REFLO A/B (Pins 11, 13): The Reference Low Inputs of the
LTC1654.
VCC (Pin 16): The Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V.
Requires a 0.1µF bypass capacitor to ground.
CS/LD (Pin 5): The TTL Level Input for the Serial Interface
Enable and Load Control. When CS/LD is low, the SCK
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TI I G DIAGRA S
t2
t6
t1
t4
t3
t7
SCK
t9
SDI
X
X
C3
B0
X
X
t5
CS/LD
t8
SDO
X
(PREVIOUS
WORD)
4
X
C3
X
X
X
CURRENT WORD
1654 TD01
C3
SDI
C2
2
C1
3
C0
4
A3
5
X
1
X
2
X
3
X
4
X
5
X
X
X
X
X
SDO
1
SDI
SCK
CS/LD
2
X
X
3
X
X
4
X
X
5
X
X
32-Bit Update (Can Daisy-Chain)
SDI
SCK
CS/LD
6
6
32-Bit Update (Without Daisy-Chain)
1
SCK
CS/LD
24-Bit Update (Without Daisy-Chain)
C3
X
X
9
C3
8
C3
9
X
7
X
8
A1
7
X
X
7
A2
6
A0
10
C2
C2
9
10
C0
C0
C1
12
C1
11
11
13
A3
A3
12
A2
A2
14
A0
A1
17
B13
B13
17
B13
B12
B12
18
19
B11
B11
18
B10
B10
20
B9
B9
21
B8
B8
22
B7
B7
23
24
B6
B6
24
B6
22
B0
23
B7
21
B1
22
B8
20
B2
21
B9
19
B3
20
B10
B4
19
B11
17
B5
18
B12
16
B6
PREVIOUS WORD
A0
16
A1
15
15
B7
16
A0
14
B8
15
A1
13
B9
14
A2
B10
13
A3
B11
12
C0
B12
11
C1
B13
10
C2
8
X
25
B5
B5
25
B5
23
X
26
B4
B4
26
B4
24
B3
B3
27
B3
27
B2
B2
28
B2
28
B1
B1
29
B1
29
X
X
B0
31
X
31
B0
30
B0
30
X
X
32
X
32
1654 TD02
CURRENT
WORD
X
LTC1654
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TI I G DIAGRA S
5
LTC1654
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OPERATIO
Serial Interface
The data on the SDI input is loaded into the shift register
on the rising edge of SCK. The MSB is loaded first. The
Clock is disabled internally when CS/LD is high. Note:
SCK must be low before CS/LD is pulled low to avoid an
extra internal clock pulse.
If no daisy-chaining is required, the input word can be
24-bit wide, as shown in the timing diagrams. The 8 MSBs,
which are loaded first, are the control and address bits
followed by a 16-bit data word. The last two LSBs in the
data word are don’t cares. The input word can be a stream
of three 8-bit wide segments as shown in the “24-Bit
Update” timing diagram.
2. Load and update DAC A in SLOW mode. Power down
DAC B. Perform the following sequence for the control,
address and DATA bits:
Step 1: Set DAC A in SLOW mode
CS/LD
CS/LD
clock in 0110 0000 XXXXXXXX XXXXXXXX;
Step 2: Load and update DAC A with DATA
CS/LD
clock in 0011 0000 + DATA; CS/LD
Step 3: Power down DAC B
CS/LD
CS/LD
clock in 0100 0001 XXXXXXXX XXXXXXXX;
If daisy-chaining is required or if the input needs to be
written in two 16-bit wide segments, then the input word
can be 32 bits wide and the top 8 bits (MSBs) are don’t
cares. The remaining 24 bits are control/address and
data. This is also shown in the timing diagrams. The
buffered output of the internal 32-bit shift register is
available on the SDO pin, which swings from GND to VCC.
3. Power down both DACs at the same time. Perform the
following sequence for the control, address and DATA
bits:
Multiple LTC1654s may be daisy-chained together by
connecting the SDO pin to the SDI pin of the next IC. The
SCK and CS/LD signals remain common to all ICs in the
daisy-chain. The serial data is clocked to all of the chips,
then the CS/LD signal is pulled high to update all DACs
simultaneously.
Voltage Output
Table 1 shows the truth table for the control/address bits.
When the supplies are first applied, the LTC1654 uses
SLOW mode, the outputs are set at 0V, and zeros are
loaded into the 32-bit input shift register. Three examples
are given to illustrate the DAC’s operation:
1. Load and update DAC A in FAST mode. Leave DAC B
unchanged. Perform the following sequence for the
control, address and DATA bits:
Step 1: Set DAC A in FAST mode
CS/LD
CS/LD
clock in 0101 0000 XXXXXXXX XXXXXXXX;
Step 2: Load and update DAC A with DATA
CS/LD
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clock in 0011 0000 + DATA; CS/LD
Step 1: Power down both DACs simultaneously
CS/LD
CS/LD
clock in 0100 1111 XXXXXXXX XXXXXXXX;
The LTC1654 comes complete with rail-to-rail voltage
output buffer amplifiers. These amplifiers will swing to
within a few millivolts of either supply rail when unloaded
and to within a 300mV of either supply rail when sinking
or sourcing 5mA.
There are two GAIN configuration modes for the LTC1654:
a) GAIN of 1: (X1/X1/2 tied to REFLO)
VOUT = (VREFHI – VREFLO)(SDI/16384) + VREFLO
b) GAIN of 1/2: (X1/X1/2 tied to VOUT)
VOUT = (1/2)(VREFHI – VREFLO)(SDI/16384) + VREFLO
The LTC 1654 has two SPEED modes: A FAST mode and
a SLOW mode. When operating in the FAST mode, the
output amplifiers will settle in 3.5µs (typ) to 14 bits on a
4V output swing. In the SLOW mode, they will settle in
8µs. The total supply current is 750µA in the FAST mode
and 450µA in the SLOW mode.
LTC1654
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OPERATION
Power Down
Each DAC can also be independently powered down to less
than 5µA/DAC of supply current. The reference pin also
goes into a high impedance state when the DAC is powered
down and the reference current will drop to below 0.1µA.
The amplifiers’ output stage is also three-stated but the
VOUT pins still have the internal gain-setting resistors
connected to them resulting in an effective resistance from
VOUT to REFLO. This resistance is typically 90k when the
X1/X1/2 pin is tied to VOUT and 36k when X1/X1/2 is tied to
REFLO. Because of this resistance, VOUT will go to VREFLO
when the DAC is powered down and VOUT is unloaded.
Table 1.
CONTROL
ADDRESS (n)
C3 C2 C1 C0
A3 A2 A1 A0
Load Input Register n
0
0
0
0
DAC A
1
Update (Power-Up) DAC Register n
0
0
0
1
DAC B
0
Load Input Register n, Update (Power-Up) All
0
0
1
0
Reserved (Do Not Use)
1
1
Load and Update n
0
0
1
1
Reserved (Do Not Use)
1
0
0
Power Down n
0
1
0
0
Reserved (Do Not Use)
1
0
1
Fast n (Speed States are Maintained Even If DAC is
Put in Power-Down Mode)
0
1
0
1
Reserved (Do Not Use)
0
1
1
0
Reserved (Do Not Use)
1
1
0
Slow n (Default State is Slow When Supplies are
Powered Up)
0
1
1
1
Reserved (Do Not Use)
1
0
0
0
Reserved (Do Not Use)
1
0
0
1
Reserved (Do Not Use)
1
0
1
0
Reserved (Do Not Use)
1
0
1
1
Reserved (Do Not Use)
1
1
0
0
Reserved (Do Not Use)
1
1
0
1
Reserved (Do Not Use)
1
1
1
0
Reserved (Do Not Use)
1
1
1
1
Both DACs
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
Reserved (Do Not Use)
1
0
0
0
Reserved (Do Not Use)
1
0
0
1
Reserved (Do Not Use)
1
0
1
0
Reserved (Do Not Use)
1
0
1
1
Reserved (Do Not Use)
1
1
0
0
Reserved (Do Not Use)
1
1
0
1
Reserved (Do Not Use)
1
1
1
0
Reserved (Do Not Use)
1
1
1
1
No Operation
INPUT WORD
CONTROL
C3
C2
C1 C0
ADDRESS
A3
A2
A1
DATA (14 + 2 DUMMY LSBs)
A0
D13 D12 D11 D10 D9
D8 D7
D6 D5 D4
D3 D2
D1 D0
X
X
1654 TABLE
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LTC1654
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APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
(FSE) is positive, the output for the highest codes limits at
VCC as shown in Figure 2c. No full-scale limiting can occur
if VREF is less than (VCC – FSE).
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC . If VREF = VCC and the DAC full-scale error
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(c)
VREF = VCC
OUTPUT
VOLTAGE
0
8192
INPUT CODE
(a)
16383
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1654 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
8
LTC1654
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DEFI ITIO S
Resolution (n): Resolution is defined as the number of
digital input bits (n). It is also the number of DAC output
states (2n) that divide the full-scale range. Resolution does
not imply linearity.
Full-Scale Voltage (VFS): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (VOS): Normally, DAC offset is the
voltage at the output when the DAC is loaded with all zeros.
The DAC can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below 0V. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
Zero-Scale Error (ZSE): The output voltage when the
DAC is loaded with all zeros. Since this is a single supply
part, this value cannot be less than 0V.
Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the
end points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:
INL = [VOUT – VOS – (VFS – VOS)(code/16383)]/LSB
VOUT = The output voltage of the DAC measured at the
given input code
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal one LSB
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
DAC CODE
1654 F01
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corresponds to the maximum offset specification:
VOS = VOUT – [(Code)(VFS)/(2n – 1)]
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
DNL = (∆VOUT – LSB)/LSB
∆V OUT = The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
nV • s.
LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/16383
Nominal LSBs:
LTC1654 LSB = 4.09575V/16383 = 250µV
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LTC1654
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TYPICAL APPLICATION
Dual 14-Bit Voltage Output DAC
2.7V TO 5.5V
0.1µF
LTC1654
1
2
3
µP
4
5
6
7
8
X1/X1/2 B
CLR
VCC
VOUT B
SCK
REFHI B
SDI
REFLO B
CS/LD
AGND
DGND
REFLO A
SDO
REFHI A
X1/X1/2 A
VOUT A
16
15
13
12
11
10
9
1654 TA01
10
OUTPUT B: 0V TO VCC
14
OUTPUT A: 0V TO VCC
LTC1654
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
16 15 14 13 12 11 10 9
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.007 – 0.0098
(0.178 – 0.249)
0.009
(0.229)
REF
0.053 – 0.068
(1.351 – 1.727)
2 3
4
5 6
7
8
0.004 – 0.0098
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
GN16 (SSOP) 1098
11
LTC1654
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1257
Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V,
Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V
5V to 15V Single Supply, Complete VOUT DAC in
SO-8 Package
LTC1446/LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V
Output Swings from GND to REF. REF Input
Can Be Tied to VCC
LTC1450/LTC1450L
Single 12-Bit VOUT DACs with Parallel Interface
LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1451
Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V,
Internal 2.048V Reference Brought Out to Pin
5V, Low Power Complete VOUT DAC in SO-8 Package
LTC1452
Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V
Low Power, Multiplying VOUT DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
LTC1453
Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V
3V, Low Power, Complete VOUT DAC in SO-8 Package
LTC1454/LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1456
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,
Full Scale: 4.095V, VCC: 4.5V to 5.5V
Low Power, Complete VOUT DAC in SO-8
Package with Clear Pin
LTC1458/LTC1458L
Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1658
14-Bit Rail-to-Rail Micropower DAC in MSOP, VCC: 2.7V to 5.5V
Output Swings from GND to REF. REF Input
Can Be Tied to VCC
LTC1659
Single Rail-to-Rail 12-Bit VOUT DAC in 8-Pin MSOP, VCC: 2.7V to 5.5V
Low Power, Multiplying VOUT DAC in MS8 Package.
Output Swings from GND to REF. REF Input Can Be
Tied to VCC.
LT1460
Micropower Precision Reference
Low Cost, 10ppm Drift
LT1461
Precision Voltage Reference
Ultralow Drift 3ppm/°C, Initial Accuracy: 0.04%
LT1634
Micropower Precision Reference
Low Drift 10ppm/°C, Initial Accuracy: 0.05%
References
12
Linear Technology Corporation
1654i LT/TP 0400 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 2000
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