IPD50N06S3-15 OptiMOS®-T Power-Transistor Product Summary V DS 55 V R DS(on),max 15 mΩ ID 50 A Features • N-channel - Normal Level - Enhancement mode • Automotive AEC Q101 qualified PG-TO252-3-11 • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green package (RoHS compliant) • 100% Avalanche tested Type Package Marking IPD50N06S3-15 PG-TO252-3-11 3N0615 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current1) ID Conditions T C=25 °C, V GS=10 V T C=100 °C, V GS=10 V2) Value 50 Unit A 35 Pulsed drain current2) I D,pulse T C=25 °C 200 Avalanche energy, single pulse2) E AS I D=25 A 130 mJ Avalanche current, single pulse I AS 50 A Gate source voltage3) V GS ±20 V Power dissipation P tot 65 W Operating and storage temperature T j, T stg -55 ... +175 °C T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 1.2 55/175/56 page 1 2009-05-20 IPD50N06S3-15 Parameter Symbol Values Conditions Unit min. typ. max. - - 2.3 minimal footprint - - 62 6 cm2 cooling area4) - - 40 Thermal characteristics2) Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D= 1 mA 55 - - Gate threshold voltage V GS(th) V DS=V GS, I D=30 µA 2.1 3.0 4 Zero gate voltage drain current I DSS V DS=55 V, V GS=0 V, T j=25 °C - 0.01 1 - 1 100 V DS=55 V, V GS=0 V, T j=125 °C2) V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 1 100 nA Drain-source on-state resistance RDS(on) V GS=10 V, I D=25 A - 13 15 mΩ Rev. 1.2 page 2 2009-05-20 IPD50N06S3-15 Parameter Symbol Values Conditions Unit min. typ. max. - 2980 3400 - 450 675 Dynamic characteristics2) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 430 645 Turn-on delay time t d(on) - 24 - Rise time tr - 59 - Turn-off delay time t d(off) - 24 - Fall time tf - 67 - Gate to source charge Q gs - 24 32 Gate to drain charge Q gd - 10 15 Gate charge total Qg - 43 50 Gate plateau voltage V plateau - 7.5 - V - - 50 A - - 200 - 0.9 1.3 V - 20 - ns - 25 - nC V GS=0 V, V DS=25 V, f =1 MHz V DD=27.5 V, V GS=10 V, I D=50 A, R G=18 Ω pF ns Gate Charge Characteristics2) V DD=11 V, I D=50 A, V GS=0 to 10 V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD Reverse recovery time2) t rr Reverse recovery charge2) Q rr T C=25 °C V GS=0 V, I F=50 A, T j=25 °C V R=27.5 V, I F=I S, di F/dt =100 A/µs 1) Current is limited by bondwire; with an R thJC = 2.0 K/W the chip is able to carry 52 A at 25°C. For detailed information see Application Note ANPS071E. 2) Defined by design. Not subject to production test. 3) Qualified at -5V and +20V 4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.2 page 3 2009-05-20 IPD50N06S3-15 1 Power dissipation 2 Drain current P tot = f(T C); V GS ≥ 6 V I D = f(T C); V GS ≥ 6 V 70 60 60 50 50 40 I D [A] P tot [W] 40 30 30 20 20 10 10 0 0 0 50 100 150 200 0 50 T C [°C] 100 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 1000 101 0.5 0 1 µs 10 100 0.1 Z thJC [K/W] 10 µs I D [A] 100 µs 1 ms 10-1 0.05 0.01 10 10-2 single pulse 10-3 1 0.1 1 10 100 10-6 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.2 10-7 page 4 2009-05-20 IPD50N06S3-15 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C R DS(on) = f(I D); T j = 25 °C parameter: V GS parameter: V GS 100 200 20 V 5V 12 V 6V 9V 8V 7V 90 160 80 10 V 70 R DS(on) [mΩ] I D [A] 120 9V 80 8V 40 60 50 40 7V 30 6V 20 10 V 5V 0 10 0 2 4 6 8 0 10 20 40 V DS [V] 60 80 100 120 140 180 I D [A] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = 6 V R DS(on) = f(T j); I D = 50 A; V GS = 10 V parameter: T j 200 24 150 20 I D [A] 25 °C 100 175 °C R DS(on) [mΩ] -55 °C 50 12 0 8 0 2 4 6 8 10 V GS [V] Rev. 1.2 16 -60 -20 20 60 100 T j [°C] page 5 2009-05-20 IPD50N06S3-15 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: I D 104 4 3.5 Ciss 300µA Coss 30µA C [pF] V GS(th) [V] 3 2.5 Crss 103 2 1.5 102 1 -60 -20 20 60 100 140 0 180 5 10 T j [°C] 15 25 V DS [V] 11 Typical forward diode characteristicis 12 Typ. avalanche characteristics IF = f(VSD) I AV = f(t AV) parameter: T j parameter: T j(start) 100 103 100°C 150°C 2 I F [A] I AV [A] 10 101 175 °C 25 °C 0.6 0.8 100 25°C 10 1 0 0.2 0.4 1 1.2 1.4 V SD [V] Rev. 1.2 20 0.1 1 10 100 1000 t AV [µs] page 6 2009-05-20 IPD50N06S3-15 13 Typical avalanche Energy 14 Drain-source breakdown voltage E AS = f(T j) V BR(DSS) = f(T j); I D = 1 mA parameter: I D 65 280 12.5 A 240 60 V BR(DSS) [V] E AS [mJ] 200 160 25 A 120 80 55 50 50 A 40 45 0 0 50 100 150 -60 200 -20 20 60 100 140 180 T j [°C] T j [°C] 15 Typ. gate charge 16 Gate charge waveforms V GS = f(Q gate); I D = 50 A pulsed parameter: V DD 12 V GS 11 V 44 V Qg 10 V GS [V] 8 V plateau 6 V g s(th) 4 2 Q g (th) Q sw Q gs 0 0 10 20 30 40 50 60 70 Q gate Q gd 80 Q gate [nC] Rev. 1.2 page 7 2009-05-20 IPD50N06S3-15 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2009 All Rights Reserved. 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Rev. 1.2 page 8 2009-05-20 IPD50N06S3-15 Revision History Version Changes Date Data Sheet version 1.1 Removal of feature: ultra low 04.10.2007 Rdson Data Sheet version 1.1 Implementation of avalanche 04.10.2007 current single pulse Data Sheet version 1.1 04.10.2007 Update of package drawing Data Sheet version 1.1 Update of avalanche diagram 12 07.11.2007 and 13 Data Sheet version 1.1 implementation of footnote 2 for 07.11.2007 Eas specification Data Sheet version 1.2 Correction of marking and update 20.05.2009 of disclaimer Rev. 1.2 page 9 2009-05-20