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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Description
The M16C/6NT group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These singlechip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency.
With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature
a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications.
Being equipped with two CAN (Controller Area Network) modules, the microcomputer is suited to drive
automotive and industrial control systems. The CAN modules comply with the 2.0B specification.
Features
• Memory capacity ................................. ROM 128K/256K bytes
RAM 5K/10K bytes
• Shortest instruction execution time ...... 62.5 ns (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
100 ns (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
• Supply voltage ..................................... 4.2 to 5.5V (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
4.2 to 5.5V (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
• Low power consumption ...................... TBD (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
TBD (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
• Interrupts ............................................. 29 internal and 9 external interrupt sources, 4 software
interrupt sources; 7 priority levels (including key input interrupt)
• Multifunction 16-bit timer ..................... 5 output timers + 6 input timers
• Serial I/O ............................................. 4 channels (3 for UART or clock synchronous, 1 for clock synchronous)
• DMAC ................................................. 2 channels (trigger: 23 sources)
• CAN module ........................................ 2 channels, 2.0B active
Specifications written in this
manual are believed to be ac• A-D converter ...................................... 10 bits X 26 analog inputs
curate, but are not guaranteed
• D-A converter ...................................... 8 bits X 2 analog outputs
to be entirely free of error.
• CRC calculation circuit ........................ 1 circuit
Specifications in this manual
• Watchdog timer ................................... 1 15-bit timer
may be changed for functional
• Programmable I/O ............................... 87 lines
or performance improvements.
• Input port ............................................. 1 line (P85 shared with NMI pin) Please make sure your manual
is the latest edition.
• Chip select output ................................ 4 lines
• Memory expansion .............................. Available (to a maximum of 1M bytes)
• Clock generating circuit ....................... 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Automotive and industrial control systems
------Table of Contents-----Description ...................................................... 1
Memory .......................................................... 9
Central Processing Unit (CPU) ...................... 18
Processor Mode ............................................ 21
Protection ..................................................... 32
Reset ............................................................ 33
Clock Generating Circuit ............................... 38
Interrupts ...................................................... 52
DMAC ........................................................... 72
WDT ............................................................. 79
Timer ............................................................ 81
Serial I/O ..................................................... 111
- UART0-2 .............................................. 127
- SIO3 ..................................................... 141
A-D Converter .............................................. 144
D-A Converter .............................................. 154
CRC Calculation Circuit ................................ 156
CAN module ................................................ 158
Programmable I/O Ports .............................. 178
Usage Precaution ........................................ 188
Electrical Characteristics (Vcc = 5 V) .......... 190
Flash Memory Description ........................... 206
CPU Rewrite Mode ....................................... 209
Parallel I/O Mode ......................................... 224
Standard Serial I/O Mode ............................. 239
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Pin Configuration
Figure 1-1 shows the pin configuration (top view).
P10/D8
P11/D9
P12/D10
P13/D11
P14/D12
P15/D13/INT3
P16/D14/INT4
P17/D15/INT5
P20/AN20/A0/(D0/-)
P21/AN21/A1/(D1/D0)
P22/AN22/A2/(D2/D1)
P23/AN23/A3/(D3/D2)
P24/AN24/A4/(D4/D3)
P25/AN25/A5/(D5/D4)
P26/AN26/A6/(D6/D5)
P27/AN27/A7/(D7/D6)
Vss
P30/A8(/-/D7)
Vcc
P31/A9
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
P40/A16
P41/A17
P42/A18
P43/A19
PIN CONFIGURATION (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P07/AN07/D7
P06/AN06/D6
P05/AN05/D5
P04/AN04/D4
P03/AN03/D3
P02/AN02/D2
P01/AN01/D1
P00/AN00/D0
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVcc
P97/ADTRG
81
82
83
84
85
86
87
88
89
90
91
92
93
M16C/6N Group
94
95
96
97
98
99
100
2 3
4 5
P44/CS0
P45/CS1
P46/CS2
P47/CS3
P50/WRL/WR
P51/WRH/BHE
P52/RD
P53/BCLK
P54/HLDA
P55/HOLD
P56/ALE
P57/RDY/CLKOUT
P60/CTS0/RTS0
P61/CLK0
P62/RxD0
P63/TXD0
P64/CTS1/RTS1/CTS0/CLKS1
P65/CLK1
P66/RxD1
P67/TXD1
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P96/ANEX1/CTX0
P95/ANEX0/CRX0
P94/DA1/TB4IN
P93/DA0/TB3IN
P92/TB2IN/SOUT3
P91/TB1IN/SIN3
P90/TB0IN/CLK3
BYTE
CNVss
P87/XCIN
P86/XCOUT
RESET
XOUT
VSS
XIN
VCC
P85/NMI
P84/INT2
P83/INT1
P82/INT0
P81/TA4IN/U
P80/TA4OUT/U
P77/TA3IN/CRX1
P76/TA3OUT/CTX1
P75/TA2IN/W
P74/TA2OUT/W
P73/CTS2/RTS2/TA1IN/V
P72/CLK2/TA1OUT/V
P71/RxD2/SCL/TA0IN/TB5IN
P70/TXD2/SDA/TA0OUT
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Package: 100P6S-A
Figure 1-1. Pin configuration (top view)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Block Diagram
Figure 1-2 is a block diagram of the M16C/6N group.
Block diagram of the M16C/6N group
8
I/O ports
Port P0
8
8
Port P1
8
Port P2
Port P3
Clock synchronous SI/O
(8 bits X 3 channels)
(8 bits X 1 channel)
CRC arithmetic circuit (CCITT)
(Polynomial : X16+X12+X5+1)
CAN module
(2 channels)
M16C/60 series16-bit CPU core
Registers
Program counter
ROM
(Note 1)
PC
Vector table
RAM
(Note 1)
INTB
8
R0H
R0L
R0H
R0L
R1H
R1L
R1H
R1L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
Memory
Stack pointer
ISP
USP
FLG
Note 1: Memory sizes depend on MCU type.
Figure 1-2. Block diagram of M16C/6N group
3
Multiplier
8
SB
Port P10
D-A converter
(8 bits x 2 outputs)
UART/clock synchronous SI/O
7
(2 channels)
XIN-XOUT
XCIN-XCOUT
Port P9
DMAC
(10 bits X 26 inputs)
Port P85
(15 bits)
System clock generator
A-D converter
Port P6
Port P8
Watchdog timer
Port P5
8
8
Timer
Port P4
8
Port P7
Internal peripheral functions
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Performance Outline
Table 1-1 is a performance outline of the M16C/6N group.
Table 1-1. Performance outline of M16C/6N group
Item
Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
62.5 ns (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
100ns (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
Memory
ROM
128K to 256K byte
capacity
RAM
5K to 10K byte
I/O ports
P0 to P10 (except P85)
8 bit x 10, 7 bit x 1
Input port
P85
1 bit x 1
Multifunction
TA0, TA1, TA2, TA3, TA4
16 bit x 5
timer
TB0, TB1, TB2, TB3, TB4, TB5
16 bit x 6
Serial I/O
UART0, UART1, UART2
(UART or clock synchronous) x 3
SI/O3
Clock synchronous
A-D converter
10 bits x (8 + 8 + 8 + 2) inputs
D-A converter
8 bits x 2 channels
CRC calculation circuit
CRC-CCITT
DMAC
2 channels (trigger: 23 sources)
CAN module
2 channels, 2.0B active
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
29 internal and 9 external sources, 4 software sources,
7 priority levels
Clock generating circuit
2 built-in clock generation circuits (built-in feedback
resistor, and external ceramic or quartz oscillator)
Supply voltage
4.2 to 5.5V (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
4.2 to 5.5V (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
Power consumption
TBD (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
TBD (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
I/O
I/O withstand voltage
5V
characteristics Output current
5mA
Operating ambient temperature
–40 to 85oC
Device configuration
CMOS high performance silicon gate
Package
100-pin plastic mold QFP
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
ROM Size
(Byte)
External
ROM
M306N0FGTFP
256K
128K
M306N0MCT-XXXFP
96K
64K
32K
Mask ROM version
One-time PROM version
EPROM version
Flash version
External ROM version
Figure 1-3. ROM expansion
Table 1-2. M16C/6N group
Apr. 1998
Type No
ROM size
RAM size
Package type
M306N0MCT-XXXFP
128K byte
5K byte
100P6S-A
Mask ROM version
M306N0FGTFP
256K byte
10K byte
100P6S-A
Flash 5V version
5
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Type No.
M306N0 M C T – XXX FP
Package type:
FP : Package
100P6S-A
ROM No.
Omitted for Flash version
Temperature Range
T : Automotive 85oC version
ROM capacity:
1 : 8K bytes
2 : 16K bytes
3 : 24K bytes
4 : 32K bytes
5 : 40K bytes
6 : 48K bytes
7 : 56K bytes
8 : 64K bytes
9 : 80K bytes
A : 96K bytes
C : 128K bytes
G : 256K bytes
Memory type:
M : Mask ROM version
F : Flash ROM version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/6N Group
M16C Family
Figure 1-4. Type No., memory size, and package
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Description
Table 1-3. Pin Description of M16C/6N group (1)
Pin name
Signal name
Function
I/O type
VCC, VSS
Power supply
input
CNVSS
CNVSS
Input
This pin switches between processor modes. Connect it to the
VSS pin to operate in single-chip or memory expansion mode.
Connect it to the VCC pin to operate in microprocessor mode.
RESET
Reset input
Input
A “L” on this input resets the microcomputer.
XIN
Clock input
Input
XOUT
Clock output
Output
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
XOUT pin open.
BYTE
External data
bus width
select input
Input
AVCC
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VCC.
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS.
VREF
Reference
voltage input
Input
This pin is a reference voltage input for the A-D converter.
P00 to P07
I/O port P0
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When set for input, the user can specify in units of four
bits via software whether or not they are tied to a pull-up resistor.
Pins in this port also function as A-D converter input pins.
Input/output
When set as a separate bus, these pins input and output data (D0–D7).
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as external interrupt pins as selected by software.
Input/output
When set as a separate bus, these pins input and output data (D8–D15).
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins.
A0 to A7
Output
These pins output 8 low-order address bits (A0–A7).
A0/D0 to
A7/D7
Input/output
If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D0–D7) and output 8 low-order address bits
(A0–A7) separated in time by multiplexing.
A0, A1/D0
to A7/D6
Output
Input/output
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D0–D6) and output address (A1–A7) separated
in time by multiplexing. They also output address (A0).
Input/output
This is an 8-bit I/O port equivalent to P0.
A8 to A15
Output
These pins output 8 middle-order address bits (A8–A15).
A8/D7,
A9 to A15
Input/output
Output
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D7) and output address (A8) separated in time
by multiplexing. They also output address (A9–A15).
Input/output
This is an 8-bit I/O port equivalent to P0.
Output
Output
These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip
select signals used to specify an access space. A16–A19 are 4 highorder address bits.
D0 to D7
P10 to P17
I/O port P1
D8 to D15
P20 to P27
P30 to P37
P40 to P47
CS0 to CS3,
A16 to A19
I/O port P2
I/O port P3
I/O port P4
Supply 4.0 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. When
operating in single-chip mode,connect this pin to VSS.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Description
Table 1-4. Pin Description of M16C/6N group (2)
Pin name
I/O type
Function
Input/output
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
Output
Output
Output
Output
Output
Input
ALE,
RDY
Output
Input
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is L and to the odd addresses when the WRH
signal is L . Data is read when RD is L .
WR, BHE, and RD selected
Data is written when WR is L . Data is read when RD is L . Odd
addresses are accessed when BHE is L . Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is L , the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a L
level. ALE is used to latch the address. While the input level of the
RDY pin is L , the microcomputer is in the ready state. BCLK outputs
a clock with the same cycle as the internal clock φ.
P50 to P57
Signal name
I/O port P5
P60 to P67
I/O port P6
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as UART0 and UART1 I/O pins as selected by software.
P70 to P77
I/O port P7
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as timer A0 - A3, timer B5, UART2 I/O or CAN1 transmit/receive data
pins as selected by software.
P80 to P84,
P86,
I/O port P8
Input/output
Input/output
P80 to P84, P86 and P87 are I/O ports with the same functions as P0.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P86 and P87 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P86 (XCOUT
pin) and P87 (XCIN pin). P85 is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from H to L . The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.
Input/output
P87,
P85
Input port P85
Input
P90 to P97
I/O port P9
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as SI/O3 I/O pins, Timer B0 - B4 input pins, D-A converter output pins,
A-D converter extended input pins, A-D trigger input pins or CAN0
transmit/receive data pins as selected by software.
P100 to P107
I/O port P10
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins. Furthermore, P104- P107 also function as
input pins for the key input interrupt function.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M16C/6N group accommodates several units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also
included are peripheral units such as CAN module, timers, serial I/O, D-A converter, DMAC, CRC calculation
circuit, A-D converter, and I/O ports.
Each unit is explained in the following.
Memory
Figure 2-1 depicts the memory map of the M16C/6N group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. ROM is located from FFFFF16 down. For example, in the M306N0MCTXXXFP, there is 128K byte of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts
such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting addresses of the interrupt
routines are stored here. The address of the vector table for timer interrupts, etc., can be set as desired using
the internal register (INTB). See the section on interrupts for details.
RAM is located from 0040016 up. For example, in the M306N0MCT-XXXFP, 5K bytes of internal RAM are
mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack
used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, CAN controller and timers, etc. Figure 2-2 to 2-9 are
locations of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and
cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or
the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be
implemented as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the space is reserved and cannot be used.
For example, in the M306N0MCT-XXXFP, the following space cannot be used.
• The space between 0180016 and 03FFF16 (Memory expansion and microprocessor modes)
• The space between D000016 and DFFFF16 (Memory expansion mode)
0000016
SFR area
FFE0016
0040016
Internal RAM area
Special page
vector table
XXXXX16
Internal reserved
area (Note 1)
0400016
External area
D000016
FFFDC16
Undefined instruction
FFFFF16
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
Overflow
Internal reserved
area (Note 2)
YYYYY16
Internal ROM area
FFFFF16
Type No.
M306N0MC
M306N0FG
Address XXXXX16 Address YYYYY16
017FF16
02BFF16
E000016
C000016
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Figure 2-1. Memory map
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
000016
004016
000116
004116
000216
004216
000316
000416
000516
000616
000716
000816
000916
000A16
004316
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Chip select control register (CSR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
004416
004516
004616
004716
004816
004916
000B16
000C16
Oscillation stop detection register (CM2)
000D16
000E16
000F16
004A16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
004B16
004C16
001016
001116
004D16
Address match interrupt register 0 (RMAD0)
004E16
001216
001316
004F16
001416
001516
005016
Address match interrupt register 1 (RMAD1)
005116
001616
005216
001716
005316
001816
005416
001916
005516
001A16
005616
001B16
005716
001C16
005816
001D16
005916
001E16
005A16
001F16
005B16
002016
002116
005C16
DMA0 source pointer (SAR0)
005D16
002216
005E16
002316
005F16
002416
002516
006016
DMA0 destination pointer (DAR0)
006116
002616
006216
002716
006316
002816
DMA0 transfer counter (TCR0)
006516
002A16
006616
002B16
006716
DMA0 control register (DM0CON)
006816
002D16
006916
002E16
006A16
002F16
006B16
003016
003116
006D16
006E16
003316
006F16
003416
007116
007216
003716
007316
DMA1 transfer counter (TCR1)
CAN0 Slot 1: Message Identifier / DLC
007416
003916
007516
003A16
007616
003B16
003C16
CAN0 Slot 0: Time Stamp
007016
DMA1 destination pointer (DAR1)
003616
003816
CAN0 Slot 0: Data Field
006C16
DMA1 source pointer (SAR1)
003216
003516
CAN0 Slot 0: Message Identifier / DLC
006416
002916
002C16
CAN0/1 Wake Up interrupt control register (C01WKPIC)
CAN0 receive successful interrupt control register (C0RECIC)
CAN0 transmit successful interrupt control register (C0TRMIC)
INT3 interrupt control register (INT3IC)
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
CAN1 receive successful interrupt control register (C1RECIC)
INT5 interrupt control register (INT5IC)
CAN1 transmit successful interrupt control register (C1TRMIC)
SIO3 interrupt control register (S3IC)
INT4 interrupt control register (INT4IC)
Bus collision detection interrupt control register (BCNIC)
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
CAN0/1 error interrupt control register (C01ERRIC)
A-D conversion interrupt control register (ADIC)
Key input interrupt control register (KUPIC)
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
007716
DMA1 control register (DM1CON)
007816
003D16
007916
003E16
007A16
003F16
007B16
CAN0 Slot 1: Data Field
007C16
007D16
007E16
CAN0 Slot 1: Time Stamp
007F16
Figure 2-2. Location of peripheral unit control registers (1)
10
U
de nd
ve er
lo
pm
en
t
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
008016
00C016
008116
008216
00C116
CAN0 Slot 2: Message Identifier / DLC
00C216
008316
00C316
008416
00C416
008516
00C516
008616
00C616
008716
00C716
008816
008916
00C816
CAN0 Slot 2: Data Field
00C916
008A16
00CA16
008B16
00CB16
008C16
00CC16
008D16
008E16
00CE16
00CF16
009016
00D016
009116
00D216
00D316
009416
00D416
009516
00D516
009616
00D616
009716
00D716
009816
00D916
00DA16
009B16
00DB16
009C16
00DC16
009D16
00DE16
00DF16
00A016
00E016
00A116
00E216
00E316
00A416
00E416
00A516
00E516
00A616
00E616
00A716
00E716
00A816
00E916
00EA16
00AB16
00EB16
00AC16
00EC16
00AD16
00EE16
00EF16
00B016
00F016
CAN0 Slot 5: Message Identifier / DLC
00F216
00B316
00F316
00B416
00F416
00B516
00F516
00B616
00F616
00B716
00F716
00B816
CAN0 Slot 9: Message Identifier / DLC
00F816
CAN0 Slot 5: Data Field
00F916
00BA16
00FA16
00BB16
00FB16
00BC16
00FC16
00BD16
00BE16
CAN0 Slot 8: Time Stamp
00F116
00B116
00B916
CAN0 Slot 8: Data Field
00ED16
CAN0 Slot 4: Time Stamp
00AF16
00B216
CAN0 Slot 8: Message Identifier / DLC
00E816
CAN0 Slot 4: Data Field
00AA16
00AE16
CAN0 Slot 7: Time Stamp
00E116
CAN0 Slot 4: Message Identifier / DLC
00A316
00A916
CAN0 Slot 7: Data Field
00DD16
CAN0 Slot 3: Time Stamp
009F16
00A216
CAN0 Slot 7: Message Identifier / DLC
00D816
CAN0 Slot 3: Data Field
009A16
009E16
CAN0 Slot 6: Time Stamp
00D116
CAN0 Slot 3: Message Identifier / DLC
009316
009916
CAN0 Slot 6: Data Field
00CD16
CAN0 Slot 2: Time Stamp
008F16
009216
CAN0 Slot 6: Message Identifier / DLC
CAN0 Slot 9: Data Field
00FD16
CAN0 Slot 5: Time Stamp
00FE16
00BF16
CAN0 Slot 9: Time Stamp
00FF16
Figure 2-3. Location of peripheral unit control registers (2)
11
U
de nd
ve er
lo
pm
en
t
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
010016
014016
010116
010216
014116
CAN0 Slot 10: Message Identifier / DLC
014216
010316
014316
010416
014416
010516
014516
010616
014616
010716
014716
010816
010916
014816
CAN0 Slot 10: Data Field
014916
010A16
014A16
010B16
014B16
010C16
014C16
010D16
010E16
014E16
014F16
011016
015016
011116
015216
015316
011416
015416
011516
015516
011616
015616
011716
015716
011816
015916
015A16
011B16
015B16
011C16
015C16
011D16
015E16
015F16
012016
016016
012116
016116
CAN0 Slot 12: Message Identifier / DLC
016316
012416
016416
012516
016516
012616
016616
012716
016716
012816
CAN0 local mask A (C0LMAR)
016916
016A16
012B16
016B16
012C16
016C16
012D16
016D16
CAN0 Slot 12: Time Stamp
CAN0 local mask B (C0LMBR)
016E16
012F16
016F16
013016
017016
013116
013216
CAN0 global mask (C0GMR)
016816
CAN0 Slot 12: Data Field
012A16
012E16
CAN0 Slot 15: Time Stamp
016216
012316
012916
CAN0 Slot 15: Data Field
015D16
CAN0 Slot 11: Time Stamp
011F16
012216
CAN0 Slot 15: Message Identifier / DLC
015816
CAN0 Slot 11: Data Field
011A16
011E16
CAN0 Slot 14: Time Stamp
015116
CAN0 Slot 11: Message Identifier / DLC
011316
011916
CAN0 Slot 14: Data Field
014D16
CAN0 Slot 10: Time Stamp
010F16
011216
CAN0 Slot 14: Message Identifier / DLC
017116
CAN0 Slot 13: Message Identifier / DLC
017216
013316
017316
013416
017416
013516
017516
013616
017616
013716
017716
013816
013916
CAN0 Slot 13: Data Field
01B916
013A16
01BA16
013B16
01BB16
013C16
01BC16
01BD16
013D16
013E16
CAN0 Slot 13: Time Stamp
01BE16
013F16
01BF16
Figure 2-4. Location of peripheral unit control registers (3)
12
U
de nd
ve er
lo
pm
en
t
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
01C016
Timer B3,4,5 count start flag (TBSR)
020016
01C116
01C216
020116
Timer A1-1 register (TA11)
020216
01C316
01C416
020316
Timer A2-1 register (TA21)
020416
01C516
01C616
020516
Timer A4-1 register (TA41)
020616
01C716
01C816
01C916
01CA16
01CB16
01CC16
01CD16
020716
Three-phase PWM control register 0 (INVC0)
Three-phase PWM control register 1 (INVC1)
Three-phase output buffer register 0 (IDB0)
Three-phase output buffer register 1 (IDB1)
Dead time timer (DTT)
Timer B2 interrupt occurrence frequency set counter (ICTB2)
020816
020916
020A16
020B16
020C16
020D16
01CE16
020E16
01CF16
01D016
020F16
Timer B3 register (TB3)
021016
01D116
01D216
021116
Timer B4 register (TB4)
021216
01D316
01D416
Timer B5 register (TB5)
021416
021516
01D616
021616
01D716
021716
01D816
021816
01D916
021916
01DA16
01DC16
01DD16
01DE16
01DF16
01E016
021A16
Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)
Interrupt cause select register 0 (IFSR0)
Interrupt cause select register 1 (IFSR1)
SI/O3 transmit/receive register (S3TRR)
01E316
021C16
021D16
021E16
022016
022116
SI/O3 control register (S3C)
SI/O3 bit rate generator (S3BRG)
022216
022316
022416
01E516
022516
01E616
022616
01E716
022716
01E816
022816
01E916
022916
01EA16
022A16
01EB16
022B16
01EC16
022C16
01ED16
022D16
01EE16
022E16
01EF16
022F16
01F016
023016
01F116
023116
01F216
023216
01F316
023316
01F416
023416
01F516
023516
01F716
01F816
01F916
01FA16
UART2
UART2
UART2
UART2
UART2
special mode register 2 (U2SMR2)
special mode register (U2SMR)
transmit/receive mode register (U2MR)
bit rate generator (U2BRG)
transmit buffer register (U2TB)
023616
01FD16
01FE16
CAN0 ExtID register (C0IDR)
CAN0 configuration register (C0CONR)
CAN0 REC register (C0RECR)
CAN0 TEC register (C0TECR)
CAN0 time stamp register (C0STR)
CAN1 message control register 0 (C1MCTL0)
CAN1 message control register 1 (C1MCTL1)
CAN1 message control register 2 (C1MCTL2)
CAN1 message control register 3 (C1MCTL3)
CAN1 message control register 4 (C1MCTL4)
CAN1 message control register 5 (C1MCTL5)
CAN1 message control register 6 (C1MCTL6)
CAN1 message control register 7 (C1MCTL7)
CAN1 message control register 8 (C1MCTL8)
CAN1 message control register 9 (C1MCTL9)
CAN1 message control register 10 (C1MCTL10)
CAN1 message control register 11 (C1MCTL11)
CAN1 message control register 12 (C1MCTL12)
CAN1 message control register 13 (C1MCTL13)
CAN1 message control register 14 (C1MCTL14)
CAN1 message control register 15 (C1MCTL15)
CAN1 control register (C1CTLR)
CAN1 status register (C1STR)
CAN1 slot status register (C1SSTR)
CAN1 slot interrupt control register (C1SICR)
023716
023816
CAN1 ExtID register (C1IDR)
023916
023A16
01FB16
01FC16
CAN0 slot interrupt control register (C0SICR)
021F16
01E416
01F616
CAN0 slot status register (C0SSTR)
021B16
01E116
01E216
CAN0 status register (C0STR)
021316
01D516
01DB16
CAN0 message control register 0 (C0MCTL0)
CAN0 message control register 1 (C0MCTL1)
CAN0 message control register 2 (C0MCTL2)
CAN0 message control register 3 (C0MCTL3)
CAN0 message control register 4 (C0MCTL4)
CAN0 message control register 5 (C0MCTL5)
CAN0 message control register 6 (C0MCTL6)
CAN0 message control register 7 (C0MCTL7)
CAN0 message control register 8 (C0MCTL8)
CAN0 message control register 9 (C0MCTL9)
CAN0 message control register 10 (C0MCTL10)
CAN0 message control register 11 (C0MCTL11)
CAN0 message control register 12 (C0MCTL12)
CAN0 message control register 13 (C0MCTL13)
CAN0 message control register 14 (C0MCTL14)
CAN0 message control register 15 (C0MCTL15)
CAN0 control register (C0CTLR)
CAN1 configuration register (C1CONR)
023B16
UART2 transmit/receive mode register 0 (U2C0)
UART2 transmit/receive mode register 1 (U2C1)
UART2 receive buffer register (U2RB)
023C16
023D16
023E16
01FF16
CAN1 REC register (C1RECR)
CAN1 TEC register (C1TECR)
CAN1 time stamp register (C1STR)
023F16
Figure 2-5. Location of peripheral unit control registers (4)
13
U
de nd
ve er
lo
pm
en
t
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
024016
028016
024116
024216
028116
CAN0 acceptance filter support register (C0AFS)
028216
024316
024416
CAN1 acceptance filter support register (C1AFS)
028416
024516
028516
024616
028616
024716
028716
024816
028816
024916
028916
024A16
028A16
024B16
028B16
024C16
028C16
024D16
028D16
024E16
028E16
024F16
028F16
025016
029016
025116
029116
025216
029216
025316
029316
025416
029416
025516
029516
025616
029616
025716
029716
025816
029816
025916
029916
025A16
029A16
025B16
029B16
025C16
029C16
025D16
025E16
025F16
029E16
02A216
026416
02A416
026516
02A516
026616
02A616
026716
02A716
026816
02A916
02AA16
026B16
02AB16
026C16
02AC16
026D16
CAN1 Slot 4: Message Identifier / DLC
CAN1 Slot 4: Data Field
02AD16
CAN1 Slot 0: Time Stamp
02AE16
026F16
02AF16
027016
02B016
027116
CAN1 Slot 4: Time Stamp
02B116
CAN1 Slot 1: Message Identifier / DLC
02B216
027316
02B316
027416
02B416
027516
02B516
027616
02B616
027716
02B716
027816
CAN1 Slot 5: Message Identifier / DLC
02B816
CAN1 Slot 1: Data Field
02B916
027A16
02BA16
027B16
02BB16
027C16
02BC16
027D16
027E16
CAN1 Slot 3: Time Stamp
02A816
CAN1 Slot 0: Data Field
026A16
027916
CAN1 Slot 3: Data Field
02A116
CAN1 Slot 0: Message Identifier / DLC
02A316
027216
CAN1 Slot 3: Message Identifier / DLC
02A016
026316
026E16
CAN1 Slot 2: Time Stamp
029F16
026116
026916
CAN1 Slot 2: Data Field
029D16
Peripheral function clock select register (PCLKR)
CAN0/1 clock select register (C01CLKR)
026016
026216
CAN1 Slot 2: Message Identifier / DLC
028316
CAN1 Slot 5: Data Field
02BD16
CAN1 Slot 1: Time Stamp
02BE16
027F16
CAN1 Slot 5: Time Stamp
02BF16
Figure 2-6. Location of peripheral unit control registers (5)
14
U
de nd
ve er
lo
pm
en
t
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
02C016
030016
02C116
02C216
030116
CAN1 Slot 6: Message Identifier / DLC
030216
02C316
030316
02C416
030416
02C516
030516
02C616
030616
02C716
030716
02C816
02C916
030816
CAN1 Slot 6: Data Field
030916
02CA16
030A16
02CB16
030B16
02CC16
030C16
02CD16
02CE16
030E16
030F16
02D016
031016
02D116
031216
031316
02D416
031416
02D516
031516
02D616
031616
02D716
031716
02D816
031916
031A16
02DB16
031B16
02DC16
031C16
02DD16
031E16
031F16
02E016
032016
02E116
032216
032316
02E416
032416
02E516
032516
02E616
032616
02E716
032716
02E816
032916
032A16
02EB16
032B16
02EC16
032C16
02ED16
032E16
032F16
02F016
033016
02F116
033216
033316
02F416
033416
02F516
033516
02F616
033616
02F716
033716
02F816
CAN1 Slot 13: Message Identifier / DLC
033816
CAN1 Slot 9: Data Field
033916
02FA16
033A16
02FB16
033B16
02FC16
033C16
02FD16
02FE16
CAN1 Slot 12: Time Stamp
033116
CAN1 Slot 9: Message Identifier / DLC
02F316
02F916
CAN1 Slot 12: Data Field
032D16
CAN1 Slot 8: Time Stamp
02EF16
02F216
CAN1 Slot 12: Message Identifier / DLC
032816
CAN1 Slot 8: Data Field
02EA16
02EE16
CAN1 Slot 11: Time Stamp
032116
CAN1 Slot 8: Message Identifier / DLC
02E316
02E916
CAN1 Slot 11: Data Field
031D16
CAN1 Slot 7: Time Stamp
02DF16
02E216
CAN1 Slot 11: Message Identifier / DLC
031816
CAN1 Slot 7: Data Field
02DA16
02DE16
CAN1 Slot 10: Time Stamp
031116
CAN1 Slot 7: Message Identifier / DLC
02D316
02D916
CAN1 Slot 10: Data Field
030D16
CAN1 Slot 6: Time Stamp
02CF16
02D216
CAN1 Slot 10: Message Identifier / DLC
CAN1 Slot 13: Data Field
033D16
CAN1 Slot 9: Time Stamp
033E16
02FF16
CAN1 Slot 13: Time Stamp
033F16
Figure 2-7. Location of peripheral unit control registers (6)
15
U
de nd
ve er
lo
pm
en
t
Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
034016
038016
034116
038116
034216
CAN1 Slot 14: Message Identifier / DLC
038216
034316
038316
034416
038416
034516
038516
034616
038616
034716
038716
034816
034916
038816
CAN1 Slot 14: Data Field
038A16
034B16
038B16
034C16
038C16
034D16
038D16
CAN1 Slot 14: Time Stamp
038E16
034F16
038F16
035016
039016
035116
039116
035216
CAN1 Slot 15: Message Identifier / DLC
039216
035316
039316
035416
039416
035516
039516
035616
039616
035716
039716
035816
035916
039816
CAN1 Slot 15: Data Field
039916
035A16
039A16
035B16
039B16
035C16
039C16
035D16
035E16
039D16
CAN1 Slot 15: Time Stamp
03A016
03A116
036216
03A216
036316
03A316
036416
03A416
036516
03A516
CAN1 local mask A (C1LMAR)
03A616
036716
03A716
036816
03A816
036916
03A916
036A16
03AA16
036B16
036C16
Timer A2 (TA2)
Timer A3 (TA3)
Timer A4 (TA4)
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
Timer
Timer
Timer
Timer
Timer
Timer
Timer
Timer
A0
A1
A2
A3
A4
B0
B1
B2
mode
mode
mode
mode
mode
mode
mode
mode
register
register
register
register
register
register
register
register
(TA0MR)
(TA1MR)
(TA2MR)
(TA3MR)
(TA4MR)
(TB0MR)
(TB1MR)
(TB2MR)
039F16
CAN1 global mask (C1GMR)
036116
036616
Timer A1 (TA1)
039E16
035F16
036016
Timer A0 (TA0)
038916
034A16
034E16
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
UART1 transmit buffer register (U1TB)
03AB16
CAN1 local mask B (C1LMBR)
03AC16
036D16
03AD16
036E16
03AE16
036F16
03AF16
037016
03B016
037116
03B116
037216
03B216
037316
03B316
037416
03B416
037516
03B516
037616
03B616
037716
03B716
037816
03B816
037916
03B916
037A16
03BA16
037B16
03BB16
037C16
03BC16
037D16
03BD16
037E16
03BE16
037F16
03BF16
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Flash memory control register 2 (FMCR2)
Flash memory control register (FMCR)
DMA0 cause select register (DM0SL)
DMA1 cause select register (DM1SL)
CRC data register (CRCD)
CRC input register (CRCIN)
Figure 2-8. Location of peripheral unit control registers (7)
16
U
de nd
ve er
lo
pm
en
t
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
03C016
A-D register 0 (AD0)
03C116
03C216
A-D register 1 (AD1)
03C316
03C416
A-D register 2 (AD2)
03C516
03C616
A-D register 3 (AD3)
03C716
03C816
A-D register 4 (AD4)
03C916
03CA16
A-D register 5 (AD5)
03CB16
03CC16
A-D register 6 (AD6)
03CD16
03CE16
A-D register 7 (AD7)
03CF16
03D016
03D116
03D216
03D316
03D416
A-D control register 2 (ADCON2)
03D516
03D616
03D716
03D816
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
03D916
03DA16
D-A register 1 (DA1)
03DB16
03DC16
D-A control register (DACON)
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 (P6)
Port P7 (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 (P8)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
03F516
03F616
Port P10 direction register (PD10)
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
Port control register (PCR)
Figure 2-9. Location of peripheral unit control registers (8)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPUControl
Bus
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 3-1. Seven of these registers (R0, R1, R2, R3, A0, A1,
and FB) come in two sets; therefore, these registers have two register banks.
b15
R0(Note)
b8 b7
b15
R1(Note)
b0
L
H
b8 b7
H
b19
b0
L
b0
Program counter
PC
Data
registers
b15
b0
b19
R2(Note)
INTB
b15
b15
b0
Interrupt table
register
b0
User stack pointer
USP
R3(Note)
b15
b15
b0
b0
Interrupt stack
pointer
ISP
A0(Note)
b15
b0
Address
registers
b15
b0
Static base
register
SB
A1(Note)
b15
FB(Note)
b0
L
H
b15
b0
b0
FLG
Frame base
registers
IPL
Flag register
U
I O B S Z D C
Note: These registers consist of two register banks.
Figure 3-1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can be
used as 32-bit data registers (R2R0/R3R1).
(2) Address rgisters (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus
CPUControl
(3) Frame base register (FB)
The frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
The program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
The interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt
vector table.
(6) Stack pointer (USP/ISP)
Stack pointers come in two types: the user stack pointer (USP) and the interrupt stack pointer (ISP), each
configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
The static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
The flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 3-2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation results in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation results in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation results in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPUControl
Bus
• Bit 7: Stack pointer select flag (U flag)
The interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has a priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
b15
b0
IPL
U
I
O B S Z D C
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 3-2. Flag register (FLG)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus ControlMode
Processor
Processor Mode
(1) Processor Mode Types
One of three processor modes can be selected: single-chip mode, memory expansion mode and microprocessor mode. The functions of some pins, the memory map and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is
selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 3-3 shows the processor mode register 0 and 1.
Figure 3-4 shows the memory maps applicable for each of the modes when memory area dose not be
expanded (normal mode).
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor
Mode
Bus Control
Processor mode register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PM0
Address
000416
Bit symbol
When reset
0016 (Note 2)
Bit name
Function
Processor mode bit
b1 b0
PM02
R/W mode select bit
0 : RD,BHE,WR
1 : RD,WRH,WRL
PM03
Software reset bit
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
PM04
Multiplexed bus space
select bit
b5 b4
PM06
Port P40 to P43 function
select bit (Note 3)
0 : Address output
1 : Port function
(Address is not output)
PM07
BCLK output disable bit
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
PM00
PM01
PM05
0
0
1
1
0
0
1
1
0:
1:
0:
1:
0
1
0
1
:
:
:
:
R W
Single-chip mode
Memory expansion mode
Inhibited
Microprocessor mode
Multiplexed bus is not used
Allocated to CS2 space
Allocated to CS1 space
Allocated to entire space (Note4)
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when
reset is 0316. (PM00 and PM01 both are set to “1”.)
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8bit width.The processor operates using the separate bus after reset is revoked, so the entire
space multiplexed bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so
only 256 bytes can be used in each chip select.
Processor mode register 1 (Note 1)
b7
b6
0
b5
b4
b3
b2
b1
b0
0
Symbol
PM1
Address
000516
Bit symbol
When reset
00000XX02
Bit name
Function
Reserved bit
R W
Must always be set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
PM13
Internal reserved area
expansion bit (Note 2)
PM14
Memory area
expansion bit (Note 3)
PM15
Reserved bit
PM17
0: The same internal reserved
area as that of M16C/60 and
M16C/61 group
1: Expands the internal RAM area
and internal ROM area to 23 K
bytes and to 256K bytes
respectively. (Note 2)
b5 b4
0 0 : Normal mode
(Do not expand)
0 1 : Inhibited
1 0 : Memory area expansion
mode 1
1 1 : Memory area expansion
mode 2
Must always be set to “0”
0 : No wait state
1 : Wait state inserted
Wait bit
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: Be sure to set this bit to 0 except products whose RAM size and ROM size exceed 15K bytes
and 192K bytes respectively.
Set this bit to "1" for M306N0FG.
Specify E0000 16 or a subsequent address, which becomes an internal ROM area if PM13 is set
to “0” at the time reset is revoked, for the reset vector table of user program.
Note 3: With the processor running in memory expansion mode or in microprocessor mode, setting this
bit provides the means of expanding the external memory area. (Normal mode: up to 1M byte,
expansion mode 1: up to 1.2 M bytes, expansion mode 2: up to 4M bytes)
For details, see “Memory space expansion functions”.
Figure 3-3. Processor mode register 0 and 1
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus ControlMode
Processor
Single-chip mode
Memory expansion mode
Microprocessor mode
0000016
SFR area
SFR area
SFR area
Internal
RAM area
Internal
RAM area
Internal
RAM area
Internally
reserved area
Internally
reserved area
External
area
External
area
0040016
XXXXX16
0400016
Inhibited
D000016
Internally
reserved area
YYYYY16
Internal
ROM area
Internal
ROM area
FFFFF16
Type No.
M306N0MC
M306N0FG
Address XXXXX16 Address YYYYY16
017FF16
02BFF16
E000016
C000016
Figure 3-4. Memory maps in each processor mode
23
External area : Accessing this area allows the user to
access a device connected externally
to the microcomputer.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Settings
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus
settings.
Table 3-1 shows the factors used to change the bus settings.
Table 3-1. Factors for switching bus settings
Bus setting
Switching external address bus width
Switching external data bus width
Switching between separate and multiplex bus
Switching factor
Bit 6 of processor mode register 0
BYTE pin
Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes
address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to
“1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to
P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to “0”, the
external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.)
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16 bits
and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin =
“H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8.
D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are
mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before accessing the multiplex bus, always set the CSi wait bit of the chip select control register to “0”.
In microprocessor mode, multiplexed bus for the entire space cannot be selected.
In memory expansion mode, when multiplexed bus for the entire space is selected, address bus range
is 256 bytes in each chip select.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Control
Bus Settings
Table 3-2. Pin functions for each processor mode
Processor mode
Single-chip
mode
Memory expansion mode/microprocessor modes
Memory
expansion mode
External bus type
Multiplexed bus and
separate bus
separate bus
Multiplexed
bus (Note 1)
Multiplexed bus
space select bit
01 , 10
00
11 (Note 2)
Data bus width
BYTE pin level
8 bits
= H
16 bits
= L
8 bits
= H
16 bits
= L
8 bita
= H
P00 to P07
I/O port
Data bus
Data bus
Data bus
Data bus
I/O port
P10 to P17
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port
P20
I/O port
Address bus
Address bus
/data bus(Note 3)
Address bus
Address bus
Address bus
/data bus
P21 to P27
I/O port
Address bus
Address bus
Address bus
/data bus(Note 3) /data bus(Note 3)
Address bus
Address bus
/data bus
P30
I/O port
Address bus
Address bus
I/O port
P31 to P37
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
P40 to P43
Port P40 to P43
function select bit = 1
I/O port
I/O port
I/O port
/O port
I/O port
I/O port
P40 to P43
Port P40 to P43
function select bit = 0
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
P44 to P47
I/O port
CS (chip select) or programmable I/O port
(For details, refer to Bus control )
P50 to P53
I/O port
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to Bus control )
P54
I/O port
HLDA
HLDA
HLDA
HLDA
HLDA
P55
I/O port
HOLD
HOLD
HOLD
HOLD
HOLD
P56
I/O port
ALE
ALE
ALE
ALE
ALE
P57
I/O port
RDY
RDY
RDY
RDY
RDY
Address bus
Address bus
/data bus(Note 3)
Note 1: In memory expansion mode, do not select a 16-bit multiplex bus.
Note 2: In microprocessor mode, multiplexed bus for the entire space cannot be selected.
In memory expansion mode, when multiplexed bus for the entire space is selected, address bus range is 256 bytes
in each chip select.
Note 3: Address bus when in separate bus mode.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function
as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
Both the address and data bus retain their previous states when internal ROM or RAM is accessed.
Also, when a change is made from single-chip mode to memory expansion mode, the value of the
address bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been cancelled. CS1 to CS3 function as input ports. Figure 3-5 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 3-3
shows the external memory areas specified using the chip select signal.
Table 3-3. External areas specified by the chip select signals
Chip select
Special address range
Memory expansion mode
Microprocessor mode
CS0
3000016 to CFFFF16 (640K)
3000016 to FFFFF16 (832K)
CS1
2800016 to 2FFFF16 (32K)
2800016 to 2FFFF16 (32K)
CS2
0800016 to 27FFF16 (128K)
0800016 to 27FFF16 (128K)
CS3
0400016 to 07FFF16 (16K)
0400016 to 07FFF16 (16K)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Chip select control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CSR
Address
000816
Bit name
Bit symbol
CS0
CS1
CS0 output enable bit
CS1 output enable bit
CS2
CS2 output enable bit
CS3
CS3 output enable bit
CS0W
CS0 wait bit
CS1W
CS1 wait bit
CS2W
CS2 wait bit
CS3W
CS3 wait bit
When reset
0116
Function
RW
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
Figure 3-5. Chip select control register
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE pin
= “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 3-4 and 3-5 show the operation of these signals.
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
Table 3-4. Operation of RD, WRL, and WRH signals
Data bus width
16-bit
(BYTE = L )
RD
L
H
H
H
WRL
H
L
H
L
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRH
H
H
L
L
Table 3-5. Operation of RD, WR, and BHE signals
Data bus width
16-bit
(BYTE = L )
8-bit
(BYTE = H )
RD
H
L
H
L
H
L
H
L
WR
L
H
L
H
L
H
L
H
BHE
L
L
H
H
L
L
Not used
Not used
A0
H
H
L
L
L
L
H/L
H/L
27
Status of external data bus
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “L”
When BYTE pin = “H”
ALE
ALE
D0/A0 to D7/A7
A8 to A19
Address
A0
Data (Note 1)
D0/A1 to D7/A8
Address
Address
Data (Note 1)
Address (Note 2)
A9 to A19
Address
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 3-6. ALE sigal and address/data bus
(5) Ready signal
The ready signal facilitates access of external devices that require a long time for access. As shown in
Figure 3-7, inputting “L” to the RDY pin at the falling edge of BCLK causes the microcomputer to enter the
ready state. Inputting “H” to the RDY pin at the falling edge of BCLK cancels the ready state. Table 3-6
shows the microcomputer status in the ready state. Figure 3-7 shows the example of the RD signal being
extended using the RDY signal.
Ready is valid when accessing the external area during the bus cycle in which the software wait is applied.
Table 3-6. Microcomputer status in ready state (Note)
Item
Status
Oscillation
On
R/W signal, address bus, data bus, CS
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
Maintain status when ready signal received
On
Note: The ready signal cannot be received immediately prior to a software wait.
BCLK
RD
: Wait using ready function
CSi
: Wait using software
(i = 0 to 3)
RDY
tsu (RDY – BCLK)
Figure 3-7. Example of RD signal extended by RDY signal
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 3-7 shows
the microcomputer status in the hold state.
Table 3-7. Microcomputer status in hold state
Item
Status
Oscillation
ON
R/W signal, address bus, data bus, CS, BHE
Programmable I/O ports
P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
Floating
Floating
Maintains status when hold signal is received
HLDA
Internal peripheral circuits
ALE signal
Output “L”
ON (but watchdog timer stops)
Undefined
(7) BCLK output
The output of the internal clock φ can be selected using bit 7 of the processor mode register 0 (address
000416) (Note). The output is floating when bit 7 is set to “1”.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(8) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, bits 4 to 7 of the chip select control register are invalid and a
wait is applied to all external memory areas (two or three BCLK cycles). However, this is not necessary if the
oscillation frequency is less than 3MHz.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for each
of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register correspond
to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one BCLK
cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default to “0”
after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
the corresponding bits of the chip select control register must be set to “0” if using the multiplex bus to
access the external memory area.
Table 3-8 shows the software wait and bus cycles. Figure 3-8 shows example bus timing when using
software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 3-8. Software waits and bus cycles
Area
Wait bit
Bits 4 to 7 of chip select
control register
Invalid
Invalid
2 BCLK cycles
0
Invalid
1 BCLK cycle
1
Invalid
2 BCLK cycles
Separate bus
0
1
1 BCLK cycle
Separate bus
0
0
2 BCLK cycles
Separate bus
1
0 (Note)
2 BCLK cycles
Multiplex bus
0
0 (Note)
3 BCLK cycles
Multiplex bus
1
0 (Note)
3 BCLK cycles
Bus status
SFR
Internal
ROM/RAM
External
memory
area
Note: Always set to "0".
30
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
< Separate bus (no wait) >
Bus cycle
BCLK
Write signal
Read signal
Output
Data bus
Address bus
Address
Input
Address
Chip select
< Separate bus (with wait) >
Bus cycle
BCLK
Write signal
Read signal
Input
Output
Data bus
Address bus
Address
Address
Chip select
< Multiplexed bus >
Bus cycle
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus
Address
Address
Address
Data output
Chip select
Figure 3-8. Typical bus timings using software wait
31
Address
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 3-9 shows the protect register. The values in the processor mode
register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0
(address 000616), system clock control register 1 (address 000716), peripheral function clock select register
(address 025E16), CAN0/1 clock select register (address 025F16), serial I/O 3 control register (01E216), port
P7 direction register (address 03EF16) and port P9 direction register (address 03F316) can only be changed
when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to
port P7 or port P9.
If, after “1” (write-enabled) has been written to the port P7 or port P9 direction registers write-enable bit (bit 2
at address 000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited).
However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode
register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been
written to an address. The program must therefore be written to return these bits to “0”.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Address
000A16
When reset
XXXXX0002
Bit symbol
Bit name
Function
PRC0
Enables writing to the system clock
control registers 0 and 1 (addresses
000616 and 000716), oscillation stop
detection register (address 000C16),
peripheral function clock select register (address 025E16), and CAN0/1
clock select register (address 025F16)
0 : Write-inhibited
1 : Write-enabled
PRC1
Enables writing to processor mode
registers 0 and 1 (addresses 000416
and 000516)
0 : Write-inhibited
1 : Write-enabled
PRC2
Enables writing to port P7/9 direction
register (address 03F316 and 03EF16)
and SI/O3 control register (address
01E216) (Note)
0 : Write-inhibited
1 : Write-enabled
R W
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Note: Writing a value to an address after 1 is written to this bit returns the bit
to 0 . Other bits do not automatically return to 0 and they must therefore
be reset by the program.
Figure 3-9. Protect register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles of f(XIN). When the reset pin level is then returned to the
“H” level while main clock is stable, the reset status is released and program execution resumes from the
address in the reset vector table.
Figure 4-1 shows the example reset circuit. Figure 4-2 shows the reset sequence.
5V
4.0V
VCC
RESET
0V
5V
VCC
RESET
0.8V
0V
Example when VCC = 5V.
Figure 4-1. Example reset circuit
XIN
More than 20 cycles are needed
Microprocessor
mode BYTE = “H”
RESET
BCLK
24cycles
BCLK
Content of reset vector
Address
FFFFC16
FFFFD16
FFFFE16
RD
WR
CS0
Microprocessor
mode BYTE = “L”
Address
Content of reset vector
FFFFC16
FFFFE16
RD
WR
CS0
Single chip
mode
Address
FFFFC16
Content of reset vector
FFFFE16
Figure 4-2. Reset sequence
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Table 4-1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 4-3, 4-4 and 4-5
show the internal status of the microcomputer immediately after the reset is released.
Table 4-1. Pin status when RESET pin level is “L”
Status
Pin name
CNVSS = VCC
CNVSS = VSS
BYTE = VSS
BYTE = VCC
P0
Input port (floating)
Data input (floating)
Data input (floating)
P1
Input port (floating)
Data input (floating)
Input port (floating)
P2, P3, P40 to P43
Input port (floating)
Address output (undefined)
Address output (undefined)
P44
Input port (floating)
CS0 output ( H level is output)
CS0 output ( H level is output)
P45 to P47
Input port (floating)
Input port (floating)
(pull-up resistor is on)
Input port (floating)
(pull-up resistor is on)
P50
Input port (floating)
WR output ( H level is output)
WR output ( H level is output)
P51
Input port (floating)
BHE output (undefined)
BHE output (undefined)
P52
Input port (floating)
RD output ( H level is output)
RD output ( H level is output)
P53
Input port (floating)
BCLK output
BCLK output
P54
Input port (floating)
HLDA output (The output value HLDA output (The output value
depends on the input to the
depends on the input to the
HOLD pin)
HOLD pin)
P55
Input port (floating)
HOLD input (floating)
HOLD input (floating)
P56
Input port (floating)
ALE output ( L level is output)
ALE output ( L level is output)
P57
Input port (floating)
RDY input (floating)
RDY input (floating)
Input port (floating)
Input port (floating)
P6, P7, P80 to P84,
P86, P87, P9, P10 Input port (floating)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(1) Processor mode register 0 (Note)
(2) Processor mode register 1
(3) System clock control register 0
(4) System clock control register 1
(5) Chip select control register
Address match interrupt
(6)
enable register
(7) Protect register
0016
(28) UART2 receive interrupt control register
(005016)···
? 0 0 0
(000516)··· 0 0 0 0 ?
0
(29) UART0 transmit interrupt control register
(005116)···
? 0 0 0
(000616)··· 0 1 0 0 1 0 0 0
(30) UART0 receive interrupt control register
(005216)···
? 0 0 0
(000716)··· 0 0 1 0 0 0 0 0
(31) UART1 transmit interrupt control register
(005316)···
? 0 0 0
(000816)··· 0 0 0 0 0 0 0 1
(32) UART1 receive interrupt control register
(005416)···
? 0 0 0
(000916)···
0 0
(33) Timer A0 interrupt control register
(005516)···
? 0 0 0
0 0 0
(34) Timer A1 interrupt control register
(005616)···
? 0 0 0
(000F16)··· 0 0 0 ? ? ? ? ?
(35) Timer A2 interrupt control register
(005716)···
? 0 0 0
(001016)···
0016
(36) Timer A3 interrupt control register
(005816)···
? 0 0 0
0016
(37) Timer A4 interrupt control register
(005916)···
? 0 0 0
(38) Timer B0 interrupt control register
(005A16)···
? 0 0 0
(000416)···
(000A16)···
(8) Watchdog timer control register
(9) Address match interrupt register 0
(001116)···
(001216)···
0 0 0 0
(001416)···
0016
(39) Timer B1 interrupt control register
(005B16)···
? 0 0 0
(001516)···
0016
(40) Timer B2 interrupt control register
(005C16)···
? 0 0 0
0 0 0 0
(41) INT0 interrupt control register
(005D16)···
0 0 ? 0 0 0
(11) DMA0 control register
(002C16)··· 0 0 0 0 0 ? 0 0
(42) INT1 interrupt control register
(005E16)···
0 0 ? 0 0 0
(12) DMA1 control register
(003C16)··· 0 0 0 0 0 ? 0 0
(43) INT2 interrupt control register
(005F16)···
0 0 ? 0 0 0
(13) CAN0/1 wake up interrupt
control register
(14) CAN0 receive successful interrupt
control register
(15) CAN0 transmit successful interrupt
control register
(004116)···
? 0 0 0
(44) Timer B3,4,5 count start flag
(01C0 16)···
0016
(004216)···
? 0 0 0
(45) Three-phase PWM control register 0
(01C8 16)···
0016
(004316)···
? 0 0 0
(46) Three-phase PWM control register 1
(01C9 16)···
0016
(16) INT3 interrupt control register
(004416)···
0 0 ? 0 0 0
(47) Three-phase output buffer register 0
(01CA 16)···
0016
(17) Timer B5 interrupt control register
(004516)···
? 0 0 0
(48) Three-phase output buffer register 1
(01CB 16)···
0016
(18) Timer B4 interrupt control register
(004616)···
? 0 0 0
(49) Timer B3 mode register
(01DB 16)··· 0 0 ?
0 0 0 0
(19) Timer B3 interrupt control register
(004716)···
? 0 0 0
(50) Timer B4 mode register
(01DC 16)··· 0 0 ?
0 0 0 0
(004816)···
0 0 ? 0 0 0
(51) Timer B5 mode register
(01DD 16)··· 0 0 ?
0 0 0 0
(10) Address match interrupt register 1
(001616)···
CAN1 receive successful interrupt
(20) control register
CAN1 transmit successful interrupt
(21)
control register
(22) Bus collision detection interrupt
control register
(004916)···
0 0 ? 0 0 0
(52) Interrupt cause select register0
(01DE16)···
(004A16)···
? 0 0 0
(53) Interrupt cause select register1
(01DF 16)···
0016
(23) DMA0 interrupt control register
(004B16)···
? 0 0 0
(54) SI/O3 control register
(01E216)···
4016
(24) DMA1 interrupt control register
(004C16)···
? 0 0 0
(55) UART2 special mode register
(01F716)···
0016
? 0 0 0
(56) UART2 transmit/receive mode register
(01F816)···
0016
(004E16)···
? 0 0 0
(57) UART2 transmit/receive control register 0 (01FC16)··· 0 0 0 0 1 0 0 0
(004F16)···
? 0 0 0
(58) UART2 transmit/receive control register 1 (01FD16)··· 0 0 0 0 0 0 1 0
(25) CAN0/1 state/error interrupt
control register
A-D conversion interrupt
(26) control register
(27) UART2 transmit interrupt
control register
(004D16)···
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
Figure 4-3. Device's internal status after a reset is cleared
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(020016)...
0016
(60)CAN0 message control register 1
(020116)...
0016
(61)CAN0 message control register 2
(020216)...
0016
(62)CAN0 message control register 3
(020316)...
0016
(63)CAN0 message control register 4
(020416)...
0016
(64)CAN0 message control register 5
(020516)...
0016
(020616)...
0016
(020716)...
0016
(67)CAN0 message control register 8
(020816)...
0016
(68)CAN0 message control register 9
(020916)...
0016
(69)CAN0 message control register 10
(020A16)...
0016
(70)CAN0 message control register 11
(020B16)...
0016
(71)CAN0 message control register 12
(020C16)...
0016
(020D16)...
0016
(020E16)...
0016
(74)CAN0 message control register 15
(020F16)...
0016
(75)CAN0 control register
(021016)... 0 0 0 0 0 0 0 1
(59)CAN0 message control register 0
(65)CAN0 message control register 6
(66)CAN0 message control register 7
(72)CAN0 message control register 13
(73)CAN0 message control register 14
(76)CAN0 status register
(021116)...
0016
(021216)...
0016
(84)CAN1 message control register 0
(022016)...
0016
(85)CAN1 message control register 1
(022116)...
0016
(86)CAN1 message control register 2
(022216)...
0016
(87)CAN1 message control register 3
(022316)...
0016
(88)CAN1 message control register 4
(022416)...
0016
(89)CAN1 message control register 5
(022516)...
0016
(90)CAN1 message control register 6
(022616)...
0016
(91)CAN1 message control register 7
(022716)...
0016
(92)CAN1 message control register 8
(022816)...
0016
(93)CAN1 message control register 9
(022916)...
0016
(94)CAN1 message control register 10
(022A16)...
0016
(95)CAN1 message control register 11
(022B16)...
0016
(96)CAN1 message control register 12
(022C16)...
0016
(97)CAN1 message control register 13
(022D16)...
0016
(98)CAN1 message control register 14
(022E16)...
0016
(99)CAN1 message control register 15
(022F16)...
0016
(100)CAN1 control register
(023016)... 0 0 0 0 0 0 0 1
(101)CAN1 status register
(021316)... 0 0 0 0 0 0 0 1
(021416)...
0016
(021516)...
0016
(021616)...
0016
(021716)...
0016
(021816)...
0016
(021916)...
0016
(021A16)...
XX16
(021B16)...
XX16
(021C16)...
0016
(82)CAN0 TEC register
(021D16)...
0016
(83)CAN0 time stamp register
(021E16)...
0016
(77)CAN0 slot status register
(78)CAN0 interrupt control register
(79)CAN0 ExtID register
(80)CAN0 configuration register
(81)CAN0 REC register
(023116)...
0016
(023216)...
0016
(023316)... 0 0 0 0 0 0 0 1
(023416)...
0016
(023516)...
0016
(023616)...
0016
(023716)...
0016
(023816)...
0016
(023916)...
0016
(023A16)...
XX16
(023B16)...
XX16
(106)CAN1 REC register
(023C16)...
0016
(107)CAN1 TEC register
(023D16)...
0016
(108)CAN1 time stamp register
(023E16)...
0016
(102)CAN1 slot status register
(103)CAN1 interrupt control register
(104)CAN1 ExtID register
(105)CAN1 configuration register
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Figure 4-4. Device's internal status after a reset is cleared
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(109) Peripheral function clock select register (025E16)...
(110) CAN0/1 clock select register
(025F16)...
(111) Count start flag
(038016)...
(112) Clock prescaler reset flag
(038116)... 0
0016
0 0
0016
(136) A-D control register 0
(03D616)... 0 0 0 0 0 ? ? ?
(137) A-D control register 1
(03D716)...
0016
(138) D-A control register
(03DC16)...
0016
(139) Port P0 direction register
(03E216)...
0016
(113) One-shot start flag
(038216)... 0 0
0 0 0 0 0
(140) Port P1 direction register
(03E316)...
0016
(114) Trigger select flag
(038316)...
0016
(141) Port P2 direction register
(03E616)...
0016
(115) Up-down flag
(038416)...
0016
(142) Port P3 direction register
(03E716)...
0016
(116) Timer A0 mode register
(039616)...
0016
(143) Port P4 direction register
(03EA16)...
0016
(117) Timer A1 mode register
(039716)...
0016
(144) Port P5 direction register
(03EB16)...
0016
(118) Timer A2 mode register
(039816)...
0016
(145) Port P6 direction register
(03EE16)...
0016
(119) Timer A3 mode register
(039916)...
0016
(146) Port P7 direction register
(03EF16)...
0016
(120) Timer A4 mode register
(039A16)...
0016
(147) Port P8 direction register
(03F216)...
(121) Timer B0 mode register
(039B16)... 0 0 ?
0 0 0 0
(148) Port P9 direction register
(03F316)...
0016
(122) Timer B1 mode register
(039C16)... 0 0 ?
0 0 0 0
(149) Port P10 direction register
(03F616)...
0016
(123) Timer B2 mode register
(039D16)... 0 0 ?
0 0 0 0
(150) Pull-up control register 0
(03FC16)...
0016
(124) UART0 transmit/receive mode register
(03A016)...
(151) Pull-up control register 1 (Note)
(03FD16)...
0016
(125) UART0 transmit/receive control register 0(03A416)... 0 0 0 0 1 0 0 0
(152) Pull-up control register 2
(03FE16)...
0016
(126) UART0 transmit/receive control register 1(03A516)... 0 0 0 0 0 0 1 0
(153) Port control register
(03FF16)...
0016
(127) UART1 transmit/receive mode register
(154) Data registers (R0/R1/R2/R3)
000016
(128) UART1 transmit/receive control register 0(03AC16)... 0 0 0 0 1 0 0 0
(155) Address registers (A0/A1)
000016
(129) UART1 transmit/receive control register 1(03AD16)... 0 0 0 0 0 0 1 0
(156) Frame base register (FB)
0000016
(130) UART transmit/receive control register 2 (03B016)...
(157) Interrupt table register (INTB)
000016
(158) User stack pointer (USP)
000016
(159) Interrupt stack pointer (ISP)
000016
(03A816)...
0016
0016
0 0 0 0 0 0 0
0 0
0 0 0 0 0
(131) Flash memory control register 2
(03B616)...
(132) Flash memory control register
(03B716)...
(133) DMA0 cause select register
(03B816)...
0016
(160) Static base register (SB)
000016
(134) DMA1 cause select register
(03BA16)...
0016
(161) Flag register (FLG)
000016
(135) A-D control register 2
(03D416)...
0
0 0 0 0 0 1
0 0 0 0
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset.
Figure 4-5. Device's internal status after a reset is cleared
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 5-1. Main clock and sub clock generating circuits
Main clock generating circuit
Sub clock generating circuit
• CPU’s operating clock source
• CPU’s operating clock source
• Internal peripheral units’
• Timer A/B’s count clock
operating clock source
source
Ceramic or crystal oscillator
Crystal oscillator
XIN, XOUT
XCIN, XCOUT
Available
Available
Oscillating
Stopped
Externally derived clock can be input
Use of clock
Usable oscillator
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
Example of oscillator circuit
Figure 5-1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit,
and the other one using an externally derived clock for input. Figure 5-2 shows some examples of sub clock
circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock
for input. Circuit constants in Figures 5-1 and 5-2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XIN
XOUT
XOUT
Open
(Note)
Rd
Externally derived clock
CIN
Vcc
COUT
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Figure 5-1. Examples of main clock
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Figure 5-2. Examples of sub clock
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
A ring oscillator is built in the microcomputer. You can use it, instead of Xin, as a main clock by setup of the
bit 1 of the oscillation stop detect register. You can use it when for example at such a wait time as executing
confirmation of port value only. At this time, the frequency generated by the ring oscillator is low enough,
compared to Xin, to realize a low power consumption.
Clock Control
Figure 5-3 shows the block diagram of the clock generating circuit.
C01CLKR
C01CLKR
b2
0
0
0
0
1
b6
0
0
0
0
1
b1
0
0
1
1
0
b0
0
1
0
1
0
a
b
c
d
e
fCAN0
b5
0
0
1
1
0
b4
0
1
0
1
0
a
b
c
d
e
fCAN1
fCAN0
fCAN1
Selector
PCLK0=0
XCIN
f2
XCOUT
PCLK0=1
1/32
f8
fC32
CM04
f32
PCLK0=0
f2AD
PCLK0=1
fC
Sub clock
CM10 1
Write signal
PCLK0=0
f8SIO2
Oscillation stop
detection circuit
S Q
XIN
R
f32SIO2
XOUT
a
Main clock
switching
circuit
RESET
Software reset
c d e f
b
Divider
Ring oscillator
CM02
S Q
WAIT instruction
g
CM07=0
fC
CM07=1
Main clock
NMI
Interrupt request
level judgment
output
f2SIO2
PCLK0=1
Internal clock φ
CM05
R
c
b
1/2
a
1/2
e
d
1/2
1/2
f
1/2
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
g
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
CCLKi:Bit i at address 025F16
Details of divider
Figure 5-3. Clock generating circuit
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describe the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
form the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping
the clock reduces the power consumption.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT pin
can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive
capacity of the XOUT pin reduces the power consumption. This bit defaults to “1” when shifting to stop
mode and after a reset.
You can switch over from the main clock to the ring oscillator by changing the value of the main clock
switch bit (bit 5 at address 000C16).
(2) Sub clock
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset. After
oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub clock can be selected as
the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub
clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the XCOUT pin
can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the
drive capacity of the XCOUT pin reduces the power consumption. This bit changes to “1” when shifting to
stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU and the watchdog timer, i.e. the internal clock φ, and is either
the main clock or fc or is derived by dividing the main clock by 2, 4, 8, or 16. After a reset the BCLK is
derived by dividing the main clock by 8 .
When shifting to stop mode, the main clock division select bit (bit 6 at 000616) is set to “1”.
(4) Peripheral function clocks
• f2, f8, f32, f2SIO2, f8SIO2, f32SIO2
The clock for the peripheral devices is derived by dividing the main clock by 2(or no division), 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
As to f2 and f2SIO2, you can select division by 2 or no division by changing the value of the peripheral
function clock select register. Select the mode without division only when Xin is 16 MHz or lower.
• f2AD
This clock is derived by dividing the main clock by 2(or no division) and is used for A-D conversion. You can
select division by 2 or no division by changing the value of the peripheral function clock select register.
• fCAN0 ,fCAN1
These clocks are derived by dividing the main clock by 1, 2, 4, 8 or 16 and they are used for the
corresponding CAN module.
(5) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub clock. It may be selected as the BCLK and for the watchdog
timer.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 5-4 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Address
000616
Bit symbol
CM00
Bit name
Clock output function
select bit
CM01
CM02
CM03
When reset
4816
Function
RW
b1 b0
0 0 : I/O port P57
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
0 : Do not stop f2, f8, f32 in wait mode
WAIT peripheral function
clock stop bit
1 : Stop f2, f8, f32 in wait mode
XCIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
CM04
Port XC select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM05
Main clock (XIN-XOUT)
stop bit (Note 3, 4 and 5)
0 : On
1 : Off
CM06
Main clock division select
bit 0 (Note 2)
0 : CM16 and CM17 valid
1 : Division by 8 mode
CM07
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop
mode and operating with XIN, set this bit to “0”. When main clock oscillation is operating by
itself, set system clock select bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns "H". The built-in feedback resistor remains ON, so XIN turns pulled
up to XOUT ("H") via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” before writing to this bit. The both bits can not be written at
the same time.
System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
0
0 0
0
b0
Symbol
CM1
Address
000716
Bit symbol
CM10
When reset
2016
Bit name
All clock stop control bit
(Note 4)
Function
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
CM15
XIN-XOUT drive capacity
select bit (Note 2)
CM16
Main clock division
select bit 1 (Note 3)
0 : LOW
1 : HIGH
b7 b6
CM17
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”.
If “1”, division mode is fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns "H", and the built-in feedback resistor turns null.
Figure 5-4. Clock control registers 0 and 1
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 5-5 shows the CAN0/1 clock select register and Figure 5-6 shows the peripheral function clock
select register.
CAN0/1 clock select register (Note 1, Note 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C01CLKR
Bit symbol
CCLK0
Address
025F16
Bit name
Function
0 0 0: No division mode
0 0 1: Division by 2 mode
0 1 0: Division by 4 mode
0 1 1: Division by 8 mode
1 0 0: Division by 16 mode
Reserved bit
Always set to "0"
CAN1 Clock select bit
0 0 0: No division mode
0 0 1: Division by 2 mode
0 1 0: Division by 4 mode
0 1 1: Division by 8 mode
1 0 0: Division by 16 mode
Reserved bit
Always set to "0"
CCLK2
RW
b2 b1 b0
CAN0 Clock select bit
CCLK1
CCLK3
When reset
0016
b6 b5 b4
CCLK4
CCLK5
CCLK6
CCLK7
Note1: Set bit 0 of the protect register (address 000A16) to "1" before writing in this register.
Note2: Change the register value only when the CAN module is in Reset/Initialization mode
(the bit 0 of the CAN Control Register (address 021016 and 023016) is"1").
Figure 5-5. CAN0/1 clock select register
Peripheral function clock select register (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PCLKR
Bit symbol
Address
025E16
When reset
XXXXXX0016
Bit name
Function
PCLK0
TimerA, TimerB, A-D
converter function clock
0: division by 2 mode
1: division by 1 mode (Note 2)
PCLK1
UART0-2, SIO3 function
clock
0: division by 2 mode
1: division by 1 mode (Note 2)
R W
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are "0".
Note1: Set bit 0 of the protect register (address 000A16) to "1" before writing in this register.
Note 2: Do not set "1" when XIN is more than 16 MHz
Figure 5-6. Peripheral function clock select register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fc
to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains
above 2V.
Because the oscillation of BCLK, f2 to f32, fc, fc32, fcAN0, fcAN1 and fAD2 stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 5-2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled.
When shifting to stop mode, the main clock division select bit 0 (bit 6 at 000616) is set to “1”.
Table 5-2. Port status during stop mode
Pin
Memory expansion mode
Microprocessor mode
Single-chip mode
Address bus, data bus, CS0 to CS3
Retains status before stop mode
RD, WR, BHE, WRL, WRH
“H”
HLDA, BCLK
ALE
Port
CLKOUT
When fc selected
When f8, f32 selected
“H”
“H”
Retains status before stop mode Retains status before stop mode
Valid only in single-chip mode “H”
Valid only in single-chip mode Retains status before stop mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
Generating Circuit
Wait Mode
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer may be stopped under certain conditions.
Refer to the section describing the watchdog timer. Writing “1” to the WAIT peripheral function clock stop bit
and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing
power consumption to be reduced. Table 5-3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts using as BCLK the clock that had been selected when the WAIT instruction was
executed.
Table 5-3. Port status during wait mode
Pin
Memory expansion mode
Microprocessor mode
Address bus, data bus, CS0 to CS3
Retains status before wait mode
RD, WR, BHE, WRL, WRH
“H”
HLDA
“H”
BCLK
ALE
Port
CLKOUT
Single-chip mode
“H” (Note)
“H”
Retains status before wait mode Retains status before wait mode
When fC selected
Valid only in single-chip mode Does not stop
When f8, f32 selected Valid only in single-chip mode Does not stop when the WAIT
peripheral function clock stop
bit is “0”.
When the WAIT peripheral
function clock stop bit is “1”,
the status immediately prior
to entering wait mode is maintained.
Note: BCLK is "H" only when the watchdog timer is stopped. Refer to the watchdog timer section for more
information
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status
Transition of
BCLK
Clock Generating
Circuit
Status Transition Of BCLK
Power consumption can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 5-4 shows the operating modes corresponding to the settings of system clock control registers
0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. Note that oscillation of the main clock must have
stabilized before transferring from this mode to another mode.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is used as BCLK.
(6) Low-speed mode
fC is used as BCLK. Note that oscillation of both the main and sub clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub clock
starts. Therefore, the program must be written to wait until this clock has stabilized immediately after
powering up and after stop mode is cancelled.
(7) Low power consumption mode
fC is the BCLK and the main clock is stopped.
(8) Ring oscillator mode
What the ring oscillator generates is the BCLK. You can use it by dividing it by 2, 4, 8 or 16, and also no
division is possible.
Table 5-4. Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
0
1
Invalid
1
0
Invalid
Invalid
1
0
Invalid
1
0
Invalid
Invalid
0
0
0
0
0
1
1
0
0
1
0
0
Invalid
Invalid
0
0
0
0
0
0
1
Invalid
Invalid
Invalid
Invalid
Invalid
1
1
45
Operating mode of BCLK
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Low-speed mode
Low power consumption mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
Power Control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(1) Normal operation mode
• High-speed mode
Divide-by 1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide by-4 divide-by-8 or divide-by-16 frequency of the main clock becomes the BCLK.
The CPU operates according to the internal clock selected. Each peripheral function operates
according to its assigned clock.
• Low-speed mode
fc becomes the BCLK. The CPU operates according to the fc clock selected. The fc clock is
supplied by the secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fc
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate
are those with the sub-clock selected as the count source.
• Ring oscillator mode
The ring oscillator replaces XIN. No-division-, divide-by-2-, 4-, 8- or 16 mode can be selected by
changing the values in CM06, CM16 and CM17. The higher the division ratio is, the lower power
consumption. The clock driver of XIN can be stopped by changing the value of the main clock stop bit
to "0" when the CPU operates using the ring oscillator. Through this the power consumption will be
still lower.
(2) Wait mode
The CPU operation is stopped. The oscillator does not stop.
(3) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in reducing power consumption.
Figure 5-7 shows the state transition of power control modes.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
Transition of stop mode, wait mode
Reset
CM21 = 1
Medium-speed mode
(Divided-by-8 mode)
Ring oscillator
mode
Interrupt
CM21 = 0
CM05 = 0
CM04 = 1
WAIT
instruction
CM10 = 1
High-speed/mediumspeed/low-speed/low
power dissipation mode
Stop mode
Wait mode
Interrupt
All oscillators stopped
CPU operation stopped
Normal mode
Transition of normal mode
Medium-speed mode (divided-by-8 mode)
BCLK : f(XIN)/8
CM07 = 0
CM06 = 1
CM05 = 0
CM04 = 1
Main clock is oscillating
Sub clock is oscillating
High-speed mode
BCLK : f(XIN)
CM07 = 0 CM06 = 0
CM17 = 0 CM16 = 0
Medium-speed mode (divided-by-4)
BCLK : f(XIN)/4
CM07 = 0
CM17 = 1
CM06 = 0
CM16 = 0
CM05 = 0 : Main clock is oscillating
CM04 = 0 : Sub clock is stopped
Note 1: Switch clocks after oscillation of both
is sufficiently stable.
Note 2: Change CM06 after changing CM17
and CM16.
Medium-speed mode (divided-by-2)
BCLK : f(XIN)/
CM07 = 0 2 CM06 = 0
CM17 = 0 CM16 = 1
Medium-speed mode (divided-by-4)
BCLK: f(XIN)/4
CM07 = 0 CM06 = 0
CM17 = 1 CM16 = 0
CM07 = 1
BCLK : f(XIN)/16
CM07 = 0 CM06 = 0
CM17 = 1 CM16 = 1
CM05 = 1
CM04 = 1
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is stopped
BCLK : f(XIN)
CM07 = 0 CM06 = 0
CM17 = 0 CM16 = 0
BCLK : f(XCIN)
Medium-speed mode (divided-by-16)
CM05 = 0
CM04 = 0
High-speed mode
Low-speed mode
Medium-speed mode (divided-by-2)
Low power dissipation mode
BCLK : f(XIN)/
CM07 = 0 2CM06 = 0
CM17 = 0 CM16 = 1
BCLK : f(
XCIN)
CM07 = 1
Medium-speed mode (divided-by-16)
BCLK : f(XIN)/1
6CM06 = 0
CM16 = 1
CM07 = 0
CM17 = 1
Figure 5-7. State transition diagram of power control mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Oscillation Stop Detection Function
Oscillation Stop Detection Function
This function is for detecting an abnormal stop of the clock which is caused by open- and/or short circuit of
the Xin oscillation circuit. When it detects an oscillation stop, it generates either an internal reset or an
oscillation stop detection interrupt. The selection depends on the value in the bit 7 of the oscillation stop
detection register (000C16). When an oscillation stop detection interrupt is generated, the ring oscillator which
is built in the microcomputer starts oscillation automatically, which is used as the system clock instead of
Xin. Through this an interrupt operation is enabled.
You can set the function to valid/invalid by changing the value in the bit 0 of the oscillation stop detection
register. The function is valid when the bit is "1". However, the value of the bit after reset release is "0", so the
function is invalid.
Table 5-5. Outline of specification of the oscillation stop detection function
Item
Specification
Clock and Frequency
Xin is 2 Mhz or more.
Condition
The oscillation stop detection bit (bit 0 at 000C16) is "1".
Operation when detected
an oscillation stop
#Generates an internal reset (when the bit 7 at 000C16 is "0")
#Generates an oscillation stop detection interrupt (when the bit 7 at
000C16 is "1")
Write "0" in the oscillation stop detection bit before setup of the stopmode to set the oscillation stop detection function to "invalid". Write
"1" in the bit after stop-mode release.
In the stop-mode
Compulsory discharge when CM20=0
Internal reset
generating cicuit
Charge/discharge
cicuit
Xin
Oscillation stop
detection interrupt
generating circuit
Pulse generation
circuit for clock edge
detection and charge/
discharge control
#
Internal reset
Watchdog timer
interrupt
To the CPU
CM21
Main clock switch control
Ring oscillator
Main clock
To the main clock
prescaler
#: When Xin is supplied, this repeats charge and discharge with pulses by Xin edge detection.
When Xin is not supplied, this continues charging. When the charge exceeds a certain level,
it regards the oscillation as stopped.
Figure 5-8. Structure of the oscillation stop detection circuit
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Oscillation Stop Detection Function
Oscillation stop detection register (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM2
Bit symbol
Address
000C16
When reset
0016
Bit name
Function
CM20
Oscillation stop
detection bit
0: The function is invalid.
1: The function is valid.
CM21
Main clock switch bit
0: Select Xin (Ring oscillator is stopped.)
1: Select ring oscillator.
CM22
Oscillation stop
detection status (Note 2)
0: No meaning
1: An oscillation stop is detected.
CM23
Clock monitor bit (Note 3)
0: Xin is in operation.
1: Xin is stopped.
CM24
Reserved bit
Always set to "0"
Operation select bit
(when an oscillation stop
is detected)
0: Internal reset on stop detectio
1: Start ring oscillator
RW
CM25
CM26
CM27
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: This bit is valid only in an execution program for the oscillation stop detection interrupt. Use this bit for the purpose of cause judgment(oscillation stop detection- or
watchdog timer interrupt) for interrupt execution. You can write in this bit "0" only.
Note 3: This bit is valid only in an execution program for the oscillation stop detection interrupt. Use this bit for the purpose of confirming Xin operation for interrupt execution.
Figure 5-9. Structure of the oscillation stop detection register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Oscillation Stop Detection Function
Oscillation stop detection bit (CM20)
You can start the oscillation stop detection by setting this bit to "1". The detection is not executed when this
bit is set to "0" or in reset status. Be sure to set this bit to "0" before setting for the stop-mode. Set this bit
again to "1" after release from stop-mode. This is because it is necessary to cancel the oscillation stop
detection function due to a certain period of unstable oscillation after release from stop-mode. Set this bit to
"0" also before setting the main clock stop bit (bit 5 at 000616) to "1".
Do not set this bit to "1" if the frequency of Xin is lower than 2 MHz.
Main clock switch bit (CM21)
You can use the ring oscillator as a system clock by setting this bit to "1". When this bit is "0", the ring
oscillator is not in operation. For more explanation, see the section of the clock generating circuit.
Oscillation stop detection status (CM22)
You can see the status of the oscillation stop detection. When this bit is "1", an oscillation stop is detected.
For usage of this bit, see the explanation on CM27.
Clock monitor bit (CM23)
You can see the operation status of the Xin clock. When this bit is "1", Xin is operating correctly. You can
check the operation status of Xin when an oscillation stop detection interrupt is generated.
Operation select (when an oscillation stop is detected) bit (CM27)
(1) Operation when internal reset is selected (CM27 is set to "0".)
An internal reset is generated when an abnormal stop of Xin is detected. The microcomputer stops in reset
status and does not operate further.
Note: Release from this status is only possible through an external reset. However, in case of a defect Xin
clock, further operation cannot be compensated.
See Table 5-6 for status of each port after an internal reset is generated.
(2) Operation when oscillation stop detection interrupt is selected (CM27 is set to "1".)
An oscillation stop detection interrupt is generated when an abnormal stop of Xin is detected. The ring
oscillator starts operation instead of the Xin clock which stopped abnormally. The operation goes further
with the supply from the ring oscillator. For the oscillation stop detection interrupt judgment on the interrupt
condition is necessary, because this interrupt shares the vector table with watchdog timer interrupt. Use the
oscillation stop detection status (CM22) for the judgment. Figure 5-10 shows the flow of the judgment.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Oscillation Stop Detection Function
Table 5-6. Port status after an internal reset is generated
Pin name
Pin Status
Microprocessor mode/Memory expansion mode
BYTE = VSS
BYTE = Vcc
Single-chip mode
P0
Input port (floating)
Data input (floating)
Data input (floating)
P1
Input port (floating)
Data input (floating)
Input port (floating)
P2, P3, P40 to P43
Input port (floating)
Address output (undefined)
Address output (undefined)
P44
Input port (floating)
CS0 output ("H" level output) CS0 output ("H" level output)
P45 to P47
Input port (floating)
Input port (floating)
Input port (floating)
(Pull-up resistance is ON.)
(Pull-up resistance is ON.)
P50
Input port (floating)
WR output ("H" level output) WR output ("H" level output)
P51
Input port (floating)
BHE output (undefined)
P52
Input port (floating)
RD output ("H" level output) RD output ("H" level output)
P53
Input port (floating)
BCLK output
P54
Input port (floating)
P55
Input port (floating)
HLDA output (Output value HLDA output (Output value
depends on HOLD pin input.) depends on HOLD pin put.)
HOLD input (floating)
HOLD input (floating)
P56
Input port (floating)
ALE output ("L" level output) ALE output ("L" level output)
P57
Input port (floating)
RDY input (floating)
RDY input (floating)
Input port (floating)
Input port (floating)
Input port (floating)
P6, P7, P80 to P84
BHE output (undefined)
BCLK output
P86, P87, P9, P10
Oscillation stop detection interrupt
or watchdog timer interrupt
is generated
Read CM22
CM22 = 1 ?
NO
YES
Jump to the execution program
for oscillation stop detection interrupt
Jump to the execution program
for watchdog timer interrupt
Figure 5-10. Flow of the judgment
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Overview of Interrupt
Type of Interrupts
Figure 6-1 lists the types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
INT instruction
Reset
Interrupt
_______
NMI
________
DBC
Special
Watchdog timer/Oscillation Stop
Single step
Hardware
Peripheral I/O (Note)
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 6-1. Classification of interrupts
• Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag)
or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set
to "1". The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and
executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral
interrupt I/O interrupts, so executing the INT instruction allows executing the same interrupt routine
that a peripheral I/O interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the
stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0"
and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning
from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt
request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make
a shift.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Hardware Interrupts
Hardware interrupts are classified into two types - special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
Reset occurs if an "L" is input to the RESET pin.
• NMI interrupt
An NMI interrupt occurs if an "L" is input to the NMI pin.
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt/Oscillation stop detection interrupt
Generated by the watchdog timer or upon oscillation stop detection.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated
by the address match interrupt register is executed with the address match interrupt enable bit set to
"1". If an address other than the first address of the instruction in the address match interrupt register
is no address match interrupt occurs. For address match interrupt, see 2. 11 Address match
interrupt.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral
functions are dependent on classes of products, so the interrupt factors too are dependent on
classes of products. The interrupt vector table is the same as the one for software interrupt numbers
0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• Key-input interrupt
A key-input interrupt occurs if an "L" is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1, UART2/NACK, CAN0, CAN1, SI/O3, and SI/O4 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1, UART2/ACK, CAN0, CAN1, SI/O3, and SI/O4 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates.
• Timer B0 interrupt through timer B5 interrupt
These are interrupts that timer B generates.
• INT0 interrupt through timer INT5 interrupt
An INT interrupt occurs if either a rising edge or a falling edge or both edges are input to the INT pin.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 6. 2 shows the format for
specifying the address.
Two types of interrupt vector tables are available __ fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
MSB
LSB
Vector address + 0
Low address
Vector address + 1
Mid address
Vector address + 2
0000
High address
Vector address + 3
0000
0000
Figure 6-2. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 6. 1 shows the interrupts assigned to the fixed vector tables
and addresses of vector tables.
Table 6-1. Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Vector table addresses
Remarks
Address (L) to address (H)
Undefined instruction
FFFDC16 to FFFDF16
Interrupt on UND instruction
Overflow
BRK instruction
FFFE016 to FFFE316
FFFE416 to FFFE716
Interrupt on INTO instruction
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
Address match
FFFE816 to FFFEB16
There is an address-matching interrupt enable bit
Single step (Note)
FFFEC16 to FFFEF16
Do not use
Watchdog timer
FFFF0 16 to FFFF316
Oscillation stop detection
________
DBC (Note)
FFFF416 to FFFF716
Do not use
_______
NMI
FFFF816 to FFFFB16
External interrupt by input to NMI pin
Reset
FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user's setting. Indicate the
first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the
INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes.
Set the first address of the interrupt routine in each vector table. Table 6-2 shows the interrupts assigned
to the variable vector tables and addresses of vector tables.
Table 6-2. Interrupt assigned to the variable vector tables and addresses of vector tables
Software interrupt number
Vector table address
Interrupt source
Address (L) to address (H)
Software interrupt number 0
+0 to +3 (Note 1)
BRK instr.
Software interrupt number 1
+4 to +7 (Note 1)
CAN0,1 Wake Up
Software interrupt number 2
+8 to +11 (Note 1)
CAN0 reception
Software interrupt number 3
+12 to +15 (Note 1)
CAN0 transmission
Software interrupt number 4
+16 to +19 (Note 1)
INT3
Software interrupt number 5
+20 to +23 (Note 1)
Timer B5
Software interrupt number 6
+24 to +27 (Note 1)
Timer B4
Software interrupt number 7
+28 to +31 (Note 1)
Timer B3
Software interrupt number 8
+32 to +35 (Note 1,2)
CAN1 reception, INT5
Software interrupt number 9
+36 to +39 (Note 1,2)
CAN1 transm., INT4, S I/O3
Software interrupt number 10
+40 to +43 (Note 1)
Bus collision detection
Software interrupt number 11
+44 to +47 (Note 1)
DMA0
Software interrupt number 12
+48 to +51 (Note 1)
DMA1
Software interrupt number 13
+52 to +55 (Note 1)
CAN0,1 Error int.
Software interrupt number 14
+56 to +59 (Note 1,2)
A-D Conv., Key input int.
Software interrupt number 15
+60 to +63 (Note 1,3)
UART2 transmission
Software interrupt number 16
+64 to +67 (Note 1,3)
UART2 reception
Software interrupt number 17
+68 to +71 (Note 1)
UART0 transmission
Software interrupt number 18
+72 to +75 (Note 1)
UART0 reception
Software interrupt number 19
+76 to +79 (Note 1)
UART1 transmission
Software interrupt number 20
+80 to +83 (Note 1)
UART1 reception
Software interrupt number 21
+84 to +87 (Note 1)
Timer A0
Software interrupt number 22
+88 to +91 (Note 1)
Timer A1
Software interrupt number 23
+92 to +95 (Note 1)
Timer A2
Software interrupt number 24
+96 to +99 (Note 1)
Timer A3
Software interrupt number 25
+100 to +103 (Note 1)
Timer A4
Software interrupt number 26
+104 to +107 (Note 1)
Timer B0
Software interrupt number 27
+108 to +111 (Note 1)
Timer B1
Software interrupt number 28
+112 to +115 (Note 1)
Timer B2
Software interrupt number 29
+116 to +119 (Note 1)
INT0
Software interrupt number 30
+120 to +123 (Note 1)
INT1
Software interrupt number 31
+124 to +127 (Note 1)
INT2
Software interrupt number 32
+128 to +131 (Note 1)
to
Software interrupt number 63
to
+252 to +255 (Note 1)
Software interrupt
Note 1: Address relative to address in interrupt table register (INTB).
Note 2: It is selected by interrupt request cause select registers (IFSR0/1).
Note 3: When IIC mode is selected, NACK and ACK interrupts are selected.
56
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Cannot be masked I flag
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Control
Descriptions are given here regarding how to enable or disable interrupts and how to set the priority to be
accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority selection bit,
or processor interrupt priority level(IPL). Whethre an interrupt request is present or absent is indicated by
the interrupt request bit. The interrupt request bit and the interrupt priority level selection bie are located in
the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located
in the flag register (FLG).
Figure 6-3 shows the memory map of the interrupt control registers.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt control register (Note 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C01WKUPIC,
C0RECIC, C0TRMIC
TBiIC(i=3 to 5)
BCNIC
DMiIC(i=0, 1)
C01ERRIC, KUPIC
ADIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
Bit symbol
ILVL0
Address
004116
004216, 004316
004516 to 004716
004A16
004B16, 004C16
004D16, 004E 16
004E16
005116, 005316, 004F16
0052 16, 005416, 005016
005516 to 005916
005A16 to 005C16
Bit name
Interrupt priority level
select bit
ILVL2
IR
Function
Interrupt request bit
R
W
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
ILVL1
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
(Note1)
Nothing is assigned.
In an attempt to write to these bits, write 0 . The value, if read, turns
out to be 0 .
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
Address
INTiIC(i=3)
004416
C1RECIC/INT5IC
(Note 3) 004816
C1TRMIC/S3IC/INT4IC (Note 3) 004916
INTiIC(i=0 to 2)
005D16
to 005F16
Bit symbol
ILVL0
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
Interrupt request bit
Polarity select bit
Reserved bit
When reset
XX00X0002
XX00X0002
XX00X0002
XX00X0002
Function
R
W
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
(Note1)
0 : Selects falling edge
1 : Selects rising edge
Always set to 0
Nothing is assigned.
In an attempt to write to these bits, write 0 . The value, if read, turns
out to be 0 .
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Note 3: Use IFSR0/ISFR1 (address 1DE/1DF) for interrupt request cause selection.
Figure 6-3. Interrupt control registers
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag
to "1" enables all maskable interrupts; setting to "0" disables all maskable interrupts. This flag is set to "0"
after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1".)
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Table
6-3 shows the settings of interrupt priority levels and Table 6-4 shows the interrupt levels enabled,
according to the consist of the IPL.
The following are conditions under which an interrupt is accepted.
•interrupt enable flag (I flag) = 1
•interrupt request bit = 1
•interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 6-3. Settings of interrupt priority
levels
Interrupt priority
level select bit
Interrupt priority
level
Table 6-3. Interrupt levels enabled according
to the contents of the IPL
Priority
order
IPL
b2 b1 b0
Enabled interrupt priority levels
IPL2 IPL1 IPL0
0
0
0
Level 0 (interrupt disabled)
0
0
0
Interrupt levels 1 and above are enabled
0
0
1
Level 1
0
0
1
Interrupt levels 2 and above are enabled
0
1
0
Level 2
0
1
0
Interrupt levels 3 and above are enabled
0
1
1
Level 3
0
1
1
Interrupt levels 4 and above are enabled
1
0
0
Level 4
1
0
0
Interrupt levels 5 and above are enabled
1
0
1
Level 5
1
0
1
Interrupt levels 6 and above are enabled
1
1
0
Level 6
1
1
0
Interrupt levels 7 and above are enabled
1
1
1
Level 7
1
1
1
All maskable interrupts are disabled
Low
High
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the
interrupt is disabled. The program examples are described as follow:
Example 1
INT_SWITCH1:
FCLR
I
;Disable interrupts.
AND.B
#00h, 0055h ;Clear TA0IC int. priority level and int. request bit.
NOP
;Four NOP instructions are required when using HOLD function.
NOP
FSET
I
;Enable interrupts
Example 2
INT_SWITCH2:
FCLR
AND.B
MOV.W
FSET
I
;Disable interrupts.
#00h, 0055h ;Clear TA0IC int. priority level and int. request bit.
MEM, R0
;Dummy read
I
;Enable interrupts
Example 3
INT_SWITCH3:
PUSHC
FLG
;Push Flag register onto stack
FCLR
I
;Disable interrupts.
AND.B
#00h, 0055h ;Clear TA0IC int. priority level and int. request bit.
POPCFLG
;Enable interrupts
The reason why two NOP instructions (four when using the HOLD function) or dummy read is inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, interrupt
request bit is not set sometimes even if the interrupt request for that register has been generated. This will
depend on the instruction. If this creates problems, use the below instructions to change the register.
Instructions: AND, OR, BCLR, BSET
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Sequence
An interrupt sequence __ What are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed __ is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address
0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag)
to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed).
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 6-4 shows the interrupt responce time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Figure 6-4. Interrupt response time
61
Instruction in
interrupt routine
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 6-5.
Table 6-5. Time required for executing the interrupt sequence
Interrupt vector address
Stack pointer (SP) value
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
18 cycles (Note 1)
20 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
20 cycles (Note 1)
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address bus
Address
0000
Interrupt
information
Data bus
R
Indeterminate
SP-2
SP-2
contents
Indeterminate
SP-4
SP-4
contents
vec
vec+2
vec
contents
PC
vec+2
contents
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 6-5. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 6-6 is set in the IPL.
Table 6-6. Relation between interrupts without interrupt priority levels and IPL
Value set in the IPL
Interrupt sources without priority levels
_______
Watchdog timer, NMI
7
Reset
0
Not changed
Other
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC)
are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 6-6 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM
instruction alone can save all the registers ecept the stack pointer (SP).
Address
MSB
Stack area
Address
MSB
LSB
Stack area
LSB
m–4
m–4
Program counter (PCL)
m–3
m–3
Program counter (PCM)
m–2
m–2
Flag register (FLGL)
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
[SP]
Stack pointer
value before
interrupt occurs
Stack status before interrupt request
is acknowledged
Flag register
(FLGH)
Program
counter (PCH)
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 6-6. State of stack before and after acceptance of interrupt request
63
[SP]
New stack
pointer value
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
The operation of saving registers carried out in the interrupt sequence is dependent whether content of the
stack pointer, at the time of acceptance of an interrupt equest, is even or odd. If the counter of the stack
pointer (Notze) is even, the counter of the flag register (FLG) and the content of the program counter (PC)
are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 6-7 shows
the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
Address
Sequence in which order
registers are saved
Stack area
[SP] – 5 (Odd)
[SP] – 4 (Even)
Program counter (PCL)
[SP] – 3(Odd)
Program counter (PCM)
[SP] – 2 (Even)
Flag register (FLGL)
[SP] – 1(Odd)
[SP]
Flag register
(FLGH)
(2) Saved simultaneously,
all 16 bits
Program
counter (PCH)
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
Program counter (PCL)
(3)
[SP] – 3 (Even)
Program counter (PCM)
(4)
[SP] – 2(Odd)
Flag register (FLGL)
[SP] – 1 (Even)
[SP]
Flag register
(FLGH)
Saved simultaneously,
all 8 bits
(1)
Program
counter (PCH)
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 6-7. Operation of saving registers
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspendedd process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar
instruction befoere executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt aqssigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest
priority),watchdog timer interrupt, etc. are regulated by hardware.
Figure 6-8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
_______
________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 6-8. Hardware interrupts priorities
Interrupt Resolution Circuit
When two or more interupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 6-9 shows the circuit that judges the interrupt priority level.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Priority level of each interrupt
Level 0 (initial value)
INT1
Timer B2
High
Timer B0
Timer A3
Timer A1
UART1 reception
UART0 reception
UART2 reception
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer A0
UART1 transmission
Priority of peripheral I/O interrupts
(if priority levels are same)
UART0 transmission
A-D conversion /Key input interrupt
DMA1
Bus collision detection
CAN1 reception, INT5
Timer B4
INT3
CAN0 reception
UART2 transmission
CAN0,1 error
DMA0
CAN1 transm., INT4, Serial I/O3
Timer B3
Timer B5
CAN0 transmission
Low
CAN0,1 Wake up
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Interrupt
request
accepted
Address match
Watchdog timer
DBC
NMI
Reset
Figure 6-9. Maskable interrupts priorities (peripheral I/O interrupts)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INT Interrupt
INT Interrupt
INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity
select bit.
Of interrupt control registers, 004816 is used both as CAN1 receive and external interrupt INT5 input control
register, and 004916 is used as serial I/O3, CAN1 transmit and as external interrupt INT4 input control register.
Use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (01DF16) to specify which interrupt request cause to select. After having set an interrupt request cause, be sure to clear
the corresponding interrupt request bit before enabling an interrupt.
The interrupt control register 004916 has the polarity-switching bit. Be sure to set this bit to "0" when selecting the
serial I/O as the interrupt request cause.
As to external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by
setting "1" in the INTi interrupt polarity switching bit of the interrupt request cause select register (01DF16). To
select both edges, set the polarity switching bit of the correponding interrupt control register to 'falling edge' ("0").
Figures 6-10 and 6-11 show the interrupt request cause select registers 0 and 1.
Interrupt request cause select register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR0
Address
01DE16
Bit name
Bit symbol
When reset
XXXXXX0016
Function
IFSR00
Interrupt request cause
select bit
0 : C1TRMIC
1 : SIO3
IFSR01
Interrupt request cause
select bit
0 : AD Converter
1 : Key On Wake Up
R
W
R
W
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Figure 6-10. Interrupt request cause select register 0
Interrupt request cause select register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR1
Bit symbol
Address
01DF16
Bit name
When reset
0016
Fumction
IFSR10
INT0 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR11
INT1 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR12
INT2 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR13
INT3 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR14
INT4 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR15
INT5 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
IFSR16
Interrupt request cause
select bit
0 : SIO3 / C1TRMIC
1 : INT4
IFSR17
Interrupt request cause
select bit
0 : C1RECIC
1 : INT5
Figure 6-11. Interrupt request cause select register 1
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
NMI
Interrupt
NMI Interrupt
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 6-12 shows the block diagram of the key input interrupt. Note that if an “L”
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Port P104-P107 pull-up
select bit
Pull-up
transistor
Key input interrupt control register
Port P107 direction
register
(address 004E 16)
Port P107 direction register
P107/KI3
Pull-up
transistor
Port P106 direction
register
Interrupt control circuit
P106/KI2
Pull-up
transistor
Port P105 direction
register
P105/KI1
Pull-up
transistor
Port P104 direction
register
P104/KI0
Figure 6-12. Block diagram of key input interrupt
68
Key input interrupt
request
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
InterruptsMatch Interrupt
Address
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt
enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC) for an
address match interrupt varies depending on the instruction being executed.
Figure 6-13 shows the address match interrupt-related registers.
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Bit symbol
Address
000916
Whenreset
XXXXXX002
Bit name
Function
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
Function
Address setting register for address match interrupt
When reset
X0000016
X0000016
Values that can be set R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Figure 6-13. Address match interrupt-related registers
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Precautions for Interrupts
CAN0/1 Wake Up Interrupt
A CAN Wake Up interrupt is generated after one of the CAN buses becomes active. That means the physical
bus turns to a dominant level.
This interrupt can only be used to wake up the CPU from wait mode or stop mode.
The CAN Wake Up interrupt can only be used, if the port(s) are configured as CAN ports. One interrupt signal
is generated for both CAN channels.
Please note that the Wake Up message wiil be lost.
Figure 6-8 shows the principle to generate the corresponding interrupt signal.
CAN0/1 Wake Up int. control register (address 0041 16)
CRX0
Interrupt control circuit
CAN Wake Up
interrupt request
CRX1
Figure 6-14. CAN 0/1 Wake Up interrupt
Precautions for Interrupts
(1) Reading address 0000016
•When the maskable interrupt occurs, CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0".
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to "0".
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
•The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before
setting a value in the stack pointer may become a factor of runaway. Be sure to set a value for the stack
pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupt including the NMI interrupt is prohibited.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(3) The NMI interrupt
•As for the NMI pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor (pull-up) if
unused. Be sure to work on it.
•The NMI pin also serves as P85, which is exclusively for input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time when
the NMI interrupt is input.
•Do not reset the CPU with the input to the NMI pin being in the "L" state.
•Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to the
NMI pin being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned down.
•Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to the
NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved. In this
instance, the CPU is returned to the normal state by a later interrupt.
•Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
•Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0
through INT5 regardless of the CPU operation clock.
•When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 6-15 shows the procedure for changing
the INT interrupt generate factor.
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
Figure 6-15. Switching condition of INT interrupt request
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. Table 7-1 shows the DMAC specifications. Figure 7-1 shows the block
diagram of the DMAC. Figures 7-2 to 7-4 show the registers used by the DMAC.
Table 7-1. DMAC specifications
Item
No. of channels
Transfer memory space
Maximum No. of bytes transferred
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors (Note)
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 byDMA1) or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests
UART2 transmission and reception interrupt requests
Serial I/O3 interrupt request
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer
The DMA enable bit is cleared and transfer ends when an underflow
occurs in the transfer counter
• Repeat transfer
When an underflow occurs in the transfer counter, the value in the transfer counter
reload register is reloaded into the transfer counter and the DMA transfer is repeated
DMA interrupt request generation timing When an underflow occurs in the transfer counter
DMA startup
• Single transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
• Repeat transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
Transfer starts when the DMA is requested after an underflow occurs in the transfer counter
DMA shutdown
• When “0” is written to the DMA enable bit
• When, in single transfer mode, an underflow occurs in the transfer counter
Forward address pointer and
When DMA transfer starts, the value of whichever of the source or destination pointer
reload timing for transfer
that is set up as the forward pointer is reloaded into the forward address pointer. The
counter
value in the transfer counter reload register is reloaded into the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Note: DMA transfer is not effective to any interrupt.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016)
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016)
(addresses 002916, 002816)
DMA0 transfer counter TCR0 (16)
DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
DMA1 forward address pointer (20) (Note)
DMA1 transfer counter reload register TCR1 (16)
(addresses 003916, 003816)
DMA latch high-order bits
DMA1 transfer counter TCR1 (16)
DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 7-1. Block diagram of DMAC
DMA0 request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM0SL
Bit symbol
DSEL0
Address
03B816
When reset
0016
Function
Bit name
DMA request cause
select bit
DSEL1
DSEL2
DSEL3
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4 (DMS=0)
/two edges of INT0 pin (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
Timer B3 (DMS=1)
1 0 0 0 : Timer B1 (DMS=0)
Timer B4 (DMS=1)
1 0 0 1 : Timer B2 (DMS=0)
Timer B5 (DMS=1)
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
DMS
DMA request cause
expansion bit
0 : Normal
1 : Expanded cause
DSR
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Figure 7-2. DMAC register (1)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA1 request cause select register
b7
b6
b5
b4
b3
b2
b1
Symbol
DM1SL
b0
Address
03BA16
Function
Bit name
Bit symbol
DSEL0
When reset
0016
DMA request cause
select bit
DSEL1
DSEL2
DSEL3
R
W
b3 b2 b1 b0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
:
:
:
:
:
:
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3(DMS=0)
/serial I/O3 (DMS=1)
0 1 1 0 : Timer A4 (DMS=0)
0 1 1 1 : Timer B0 (DMS=0)
/two edges of INT1 (DMS=1)
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 receive
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is 0 .
DMS
DMA request cause
expansion bit
0 : Normal
1 : Expanded cause
DSR
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to 1 (When read,
the value of this bit is always 0 )
DMAi control register
b7
b6
b5
b4
b3
b2
b1
Symbol
DMiCON(i=0,1)
b0
Bit symbol
Address
002C16, 003C16
When reset
00000X002
Bit name
Function
DMBIT
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMAS
DMA request bit (Note 1)
0 : DMA not requested
1 : DMA requested
DMAE
DMA enable bit
0 : Disabled
1 : Enabled
DSD
Source address direction
select bit (Note 3)
0 : Fixed
1 : Forward
DAD
Destination address
0 : Fixed
direction select bit (Note 3) 1 : Forward
R
W
(Note 2)
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is 0 .
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to 0 .
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to 1 simultaneously.
Figure 7-3. DMAC register (2)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAi source pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
• Source pointer
Stores the source address
R W
0000016 to FFFFF16
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
DMAi destination pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0
b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
• Destination pointer
Stores the destination address
R W
0000016 to FFFFF16
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0
b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
Function
• Transfer counter
Set a value one less than the transfer count
Figure 7-4. DMAC register (3)
75
When reset
Indeterminate
Indeterminate
Transfer count
specification
000016 to FFFF16
R W
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source and
destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 7-5 shows the example of the transfer cycles for a source read. For convenience, the destination
write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In
reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 75, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source
read cycle and the destination write cycle.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
BCLK
Address
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
CPU use
Source
Source + 1 Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source + 1 Destination
Source
Dummy
cycle
CPU use
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination Dummy
cycle
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 7-5. Example of the transfer cycles for a source read
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 7-2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 7-2. No. of DMAC transfer cycles
Single-chip mode
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Memory expansion mode
Bus width
Access address
Microprocessor mode
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
Even
1
1
1
1
(BYTE= “L”)
Odd
1
1
1
1
8-bit
Even
—
—
1
1
(BYTE = “H”)
Odd
—
—
1
1
16-bit
Even
1
1
1
1
(BYTE = “L”)
Odd
2
2
2
2
8-bit
Even
—
—
2
2
(BYTE = “H”)
Odd
—
—
2
2
Coefficient j, k
Internal memory
Internal ROM/RAM Internal ROM/RAM SFR area
No wait
With wait
1
2
2
External memory
Separate bus Separate bus
No wait
With wait
1
2
78
Multiplex
bus
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the internal clock φ using the prescaler. A
watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the internal clock φ, bit 7 of the watchdog timer control register (address 000F16) selects the
prescaler division ratio (by 16 or by 128). When XCIN is selected as the internal clock φ, the prescaler is set
for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Table 8-1 shows
the periodic table for the watchdog timer.
Table 8-1. Watchdog timer periodic table (XIN = 10MHz, XCIN = 32kHz)
CM07
0
CM06
0
CM17
0
CM16
0
Internal clock φ
10MHz
0
0
0
1
5MHz
0
0
1
0
2.5MHz
0
0
1
1
0.625MHz
0
1
Invalid
Invalid
1.25MHz
1
Invalid
Invalid
Invalid
32kHz
WDC7
0
1
0
1
0
Period
Approx. 52.4ms (Note)
Approx. 419.2ms (Note)
Approx. 104.9ms (Note)
Approx. 838.8ms (Note)
Approx. 209.7ms (Note)
1
0
1
0
1
Invalid
Approx. 1.68s (Note)
Approx. 838.8ms (Note)
Approx. 6.71s (Note)
Approx. 419.2ms (Note)
Approx. 3.35s (Note)
Approx. 2s (Note)
Note: Error is generated by the prescaler.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a
watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 8-1 shows the block diagram of the watchdog timer. Figure 8-2 shows the watchdog timer-related
registers.
Prescaler
1/16
Internal clock
1/128
“CM07 = 0”
“WDC7 = 0”
“CM07 = 0”
“WDC7 = 1”
Watchdog timer
HOLD
“CM07 = 1”
1/2
Write to the watchdog timer
start register
(address 000E16)
Set to
“7FFF16”
RESET
Figure 8-1. Block diagram of watchdog timer
79
Watchdog timer
interrupt request
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer during Wait Mode
The watchdog timer is supplied by the internal clock φ. If the internal clock φ stops, the watchdog timer stops
also. When executing a wait instruction, the internal clock φ stops if no interrupt request is pending or any
interrupt request that is pending is marked (i.e. the interrupts IPL is set to a value not greater than the CPU's
IPL).
The internal clock φ and the watchdog timer will continue running when at the issuance of the wait instruction
any nonmasked interrupt request was pending and the I flag in the flag register was cleared.
The same applies to an internal clock φ stopped during wait mode: If during wait mode a disabled but not
masked interrupt is requested and the I flag is cleared internal clock φ restarts. Though the CPU remains in
wait, the watchdog timer recommences activity where it left off and will in time request an interrupt itself.
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
WDC
Bit symbol
Address
000F16
When reset
000XXXXX2
Bit name
Function
R W
High-order bits of watchdog timer
Reserved bit
This bit can neither be set nor reset.
Reserved bit
Must always be set to “0”
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
Figure 8-2. Watchdog timer control and start registers
80
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(six). All these timers function independently. Figures 9-1 and 9-2 show the block diagram of timers.
PCLK0 = 1
Clock prescaler
f2
1/2
f8
1/4
1/4
f32
fC32
1/32
XCIN
Clock prescaler reset flag (bit 7
at address 038116) set to 1
Reset
f2 f 8f 32f C32
Timer mode
One-shot mode
PWM mode
Timer A0 interrupt
TA0IN
Noise
filter
Timer A0
Event counter mode
Timer mode
One-shot mode
PWM mode
TA1IN
Noise
filter
Timer A1 interrupt
Timer A1
Event counter mode
Timer mode
One-shot mode
PWM mode
Timer A2 interrupt
TA2IN
Noise
filter
Timer A2
Event counter mode
Timer mode
One-shot mode
PWM mode
Timer A3 interrupt
TA3IN
Noise
filter
Timer A3
Event counter mode
Timer mode
One-shot mode
PWM mode
Timer A4 interrupt
TA4IN
Noise
filter
Timer A4
Event counter mode
Timer B2 overflow
Figure 9-1. Timer A block diagram
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
PCLK0 = 1
Clock prescaler
f2
1/2
f8
1/4
1/4
f32
1/32
XCIN
Clock prescaler reset flag (bit 7
at address 038116) set to 1
fC32
Reset
f2 f8 f32 fC32
Timer A
Timer mode
Pulse width measuring mode
TB0IN
Timer B0 interrupt
Noise
filter
Timer B0
Event counter mode
Timer mode
Pulse width measuring mode
TB1IN
Noise
filter
Timer B1 interrupt
Timer B1
Event counter mode
Timer mode
Pulse width measuring mode
TB2IN
Noise
filter
Timer B2 interrupt
Timer B2
Event counter mode
Timer mode
Pulse width measuring mode
TB3IN
Timer B3 interrupt
Noise
filter
Timer B3
Event counter mode
Timer mode
Pulse width measuring mode
TB4IN
Noise
filter
Timer B4 interrupt
Timer B4
Event counter mode
Timer mode
Pulse width measuring mode
TB5IN
Noise
filter
Timer B5
Figure 9-2. Timer B block diagram
82
Timer B5 interrupt
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A
Figure 9-3 shows the block diagram of timer A. Figures 9-4 to 9-6 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f2
f8
f32
Low-order
8 bits
• Timer
(gate function)
fC32
High-order
8 bits
Reload register (16)
• Event counter
Counter (16)
Polarity
selection
Up count/down count
Clock selection
TAiIN
(i = 0 to 4)
Always down count except
in event counter mode
Count start flag
(Address 038016)
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Down count
TB2 overflow
External
trigger
TAj overflow
Up/down flag
(Address 038416)
(j = i – 1. Note, however, that j = 4 when i = 0)
Addresses
038716 038616
038916 038816
038B16 038A16
038D16 038C16
038F16 038E16
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Figure 9-3. Block diagram of timer A
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
Address
When reset
0016
039616 to 039A16
Bit name
Operation mode select bit
TMOD1
MR0
MR1
Function
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
Function varies with each operation mode
MR2
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Figure 9-4. Timer A-related registers (1)
83
RW
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer Ai register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA0
TA1
TA2
TA3
TA4
Address
038716,038616
038916,038816
038B16,038A16
038D16,038C16
038F16,038E16
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
Values that can be set
• Timer mode
Counts an internal count source
000016 to FFFF16
• Event counter mode
Counts pulses from an external source or timer overflow
000016 to FFFF16
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FE16
(Both high-order
and low-order
addresses)
RW
Note: Read and write data in 16-bit units.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit symbol
Address
038016
When reset
0016
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
R W
0 : Stops counting
1 : Starts counting
Up/down flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UDF
Bit symbol
Address
038416
Bit name
TA0UD
Timer A0 up/down flag
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
TA4UD
Timer A4 up/down flag
TA2P
TA3P
TA4P
When reset
0016
Function
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
Timer A2 two-phase pulse 0 : two-phase pulse signal
processing disabled
signal processing select bit
1 : two-phase pulse signal
processing enabled
Timer A3 two-phase pulse
signal processing select bit
When not using the two-phase
Timer A4 two-phase pulse pulse signal processing function,
signal processing select bit set the select bit to “0”
Figure 9-5. Timer A-related registers (2)
84
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
One-shot start flag
b7
b6
b5
b4
b3
b2
b1
Symbol
ONSF
b0
Address
038216
When reset
00X000002
Bit symbol
Bit name
TA0OS
Timer A0 one-shot start flag
Function
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
RW
1 : Timer start
When read, the value is “0”
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
TA0TGL
Timer A0 event/trigger
select bit
TA0TGH
b7 b6
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
Trigger select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TRGSR
Bit symbol
TA1TGL
Address
038316
When reset
0016
Bit name
Timer A1 event/trigger
select bit
TA1TGH
TA2TGL
Timer A2 event/trigger
select bit
TA2TGH
TA3TGL
Timer A3 event/trigger
select bit
TA3TGH
TA4TGL
Timer A4 event/trigger
select bit
TA4TGH
Function
R W
b1 b0
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
b3 b2
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
b5 b4
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”.
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
When reset
0XXXXXXX2
Function
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
CPSR
Clock prescaler reset flag
Figure 9-6. Timer A-related registers (3)
85
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
RW
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 9-1.) Figure 9-7 shows the
timer Ai mode register in timer mode.
Table 9-1. Specifications of timer mode
Item
Count source
Count operation
Specification
f2, f8, f32, fc32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing When the timer underflows
TAiIN pin function
Programmable I/O port or gate input
TAiOUT pin function
Programmable I/O port or pulse output
Read from timer
Count value can be read out by reading timer Ai register
Write to timer
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
0 0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
TMOD1
Address
When reset
039616 to 039A16
0016
Bit name
Operation mode
select bit
Function
RW
b1 b0
0 0 : Timer mode
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
Gate function select bit
b4 b3
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held “L” (Note 3)
1 1 : Timer counts only when TAiIN pin is
held “H” (Note 3)
MR2
MR3
0 (Must always be fixed to “0” in timer mode)
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f2
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Figure 9-7. Timer Ai mode register in timer mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 9-2 lists timer specifications when counting a single-phase external signal. Figure
9-8 shows the timer Ai mode register in event counter mode.
Table 9-2 lists timer specifications when counting a two-phase external signal. Figure 9-9 shows the timer
Ai mode register in event counter mode.
Table 9-2. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
• External signals input to TAiIN pin (effective edge can be selected by software)
Count source
• TB2 overflow, TAj overflow
Count operation
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
Programmable I/O port or count source input
TAiOUT pin function
Programmable I/O port, pulse output, or up/down count select input
Read from timer
Count value can be read out by reading timer Ai register
Write to timer
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
TAiMR(i = 0, 1)
0 1
Address
039616, 039716
When reset
0016
Bit symbol
Bit name
TMOD0
Operation mode select bit
b1 b0
Function
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TAiOUT pin is a pulse output pin)
MR1
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
MR2
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 4)
RW
0 1 : Event counter mode (Note 1)
TMOD1
MR3
0 (Must always be fixed to “0” in event counter mode)
TCK0
Count operation type
select bit
TCK1
Invalid in event counter mode
Can be “0” or “1”
0 : Reload type
1 : Free-run type
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Figure 9-8. Timer Ai mode register in event counter mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Table 9-3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4)
Item
Count source
Count operation
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pin
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
Timer overflows or underflows
Two-phase pulse input
Two-phase pulse input
Count value can be read out by reading timer A2, A3, or A4 register
• When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
• Normal processing operation
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
Down
count count
Down
count
Down
count
• Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count up all edges
Count down all edges
Count up all edges
Count down all edges
TAiIN
(i=3,4)
Note: This does not apply when the free-run function is selected.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer Ai mode register
(When not using two-phase pulse signal processing)
b7
b6
b5
b4
b3
b2
0
b1
b0
0 1
Symbol
Address
When reset
0016
TAiMR(i = 2 to 4) 039816 to 039A16
Bit symbol
TMOD0
Bit name
Operation mode select bit
TMOD1
Function
R W
b1 b0
0 1 : Event counter mode
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
Count polarity
select bit (Note 2)
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
MR2
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
MR3
0 : (Must always be “0” in event counter mode)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK1
Two-phase pulse signal
processing operation
select bit (Note 4)(Note 5)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for the timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Timer Ai mode register
(When using two-phase pulse signal processing)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 0 0 0 1
Symbol
Address
When reset
0016
TAiMR(i = 2 to 4) 039816 to 039A16
Bit symbol
Bit name
TMOD0
TMOD1
Operation mode select bit
Function
RW
b1 b0
0 1 : Event counter mode
MR0
0 (Must always be “0” when using two-phase pulse signal
processing)
MR1
0 (Must always be “0” when using two-phase pulse signal
processing)
MR2
1 (Must always be “1” when using two-phase pulse signal
processing)
MR3
0 (Must always be “0” when using two-phase pulse signal
processing)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK1
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0” or “1”.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Figure 9-9. Timer Ai mode register in event counter mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 9-4.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 9-10 shows the timer Ai mode register in one-shot timer
mode.
Table 9-4. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
f2, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
1/n
n : Set value
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
The count reaches 000016
Programmable I/O port or trigger input
Programmable I/O port or pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
1 0
Symbol
Address
When reset
TAiMR(i = 0 to 4) 039616 to 039A16
0016
Bit symbol
TMOD0
Bit name
Function
Operation mode select bit
b1 b0
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
External trigger select
bit (Note 2)
0 : Falling edge of TAiIN pin's input signal (Note 3)
1 : Rising edge of TAiIN pin's input signal (Note 3)
MR2
Trigger select bit
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
TMOD1
1 0 : One-shot timer mode
MR3
0 (Must always be “0” in one-shot timer mode)
TCK0
Count source select bit
TCK1
RW
b7 b6
0 0 : f2
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0”.
Figure 9-10. Timer Ai mode register in one-shot timer mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 9-5.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 9-11 shows the
timer Ai mode register in pulse width modulation mode. Figure 9-12 shows the example of how a 16-bit pulse
width modulator operates. Figure 9-13 shows the example of how an 8-bit pulse width modulator operates.
Table 9-5. Timer specifications in pulse width modulation mode
Item
Specification
Count source
Count operation
f2, f8, f32, fC32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
• High level width
n / fi n : Set value
16
• Cycle time
(2 -1) / fi fixed
• High level width n (m+1) / fi
n : values set to timer Ai register’s high-order address
• Cycle time
(28-1) (m+1) / fi
m : values set to timer Ai register’s low-order address
• External trigger is input
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
PWM pulse goes “L”
Programmable I/O port or trigger input
Pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
16-bit PWM
8-bit PWM
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
1 1
1
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
TMOD1
Address
When reset
0016
039616 to 039A16
Bit name
Operation mode
select bit
Function
R W
b1 b0
1 1 : PWM mode
MR0
1 (Must always be “1” in PWM mode)
MR1
External trigger select
bit (Note 1)
0: Falling edge of TAiIN pin's input signal (Note 2)
1: Rising edge of TAiIN pin's input signal (Note 2)
MR2
Trigger select bit
0: Count start flag is valid
1: Selected by event/trigger select register
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
TCK0
Count source select bit
0 0 : f2
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
TCK1
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port direction register to “0”.
Figure 9-11. Timer Ai mode register in pulse width modulation mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Condition: Reload register = 000316, when external trigger
(rising edge of TAiIN pin input signal) is selected
1 / fi X (2 16 – 1)
Count source
“H”
TAiIN pin
input signal
“L”
Trigger is not generated by this signal
1 / fi X n
PWM pulse output
from TAiOUT pin
“H”
Timer Ai interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f2, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFE16.
Figure 9-12. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (2 8 – 1)
Count source (Note1)
TAiIN pin input signal
“H”
“L”
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2) “L”
1 / fi X (m + 1) X n
PWM pulse output
from TAiOUT pin
“H”
Timer Ai interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f2, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleaerd by software
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16.
Figure 9-13. Example of how an 8-bit pulse width modulator operates
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer B
Figure 10-1 shows the block diagram of timer B. Figures 10-2 and 10-3 show the timer B-related registers.
Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f2
• Timer
• Pulse period/pulse width measurement
f8
f32
fC32
Reload register (16)
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
TBiIN
(i = 0 to 5)
(address 038016)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
TBj overflow
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Address
039116 039016
039316 039216
039516 039416
01D116 01D016
01D316 01D216
01D516 01D416
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Figure 10-1. Block diagram of timer B
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
TBiMR(i = 0 to 5) 039B16 to 039D16
01DB16 to 01DD16
Bit symbol
TMOD0
Function
Bit name
Operation mode select bit
TMOD1
MR0
When reset
00XX00002
00XX00002
R
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
Function varies with each operation mode
MR1
MR2
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 10-2. Timer B-related registers (1)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer Bi register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
039116, 039016
039316, 039216
039516, 039416
01D116, 01D016
01D316, 01D216
01D516, 01D416
Function
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Values that can be set
• Timer mode
Counts the timer's period
000016 to FFFF16
• Event counter mode
Counts external pulses input or a timer overflow
000016 to FFFF16
R W
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Address
038016
When reset
0016
Bit name
Bit symbol
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
RW
0 : Stops counting
1 : Starts counting
Timer B3, 4, 5 count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TBSR
Address
01C016
Bit symbol
When reset
0016
Bit name
Function
RW
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
TB3S
Timer B3 count start flag
TB4S
Timer B4 count start flag
TB5S
Timer B5 count start flag
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
When reset
0XXXXXXX2
Function
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
CPSR
Clock prescaler reset flag
Figure 10-3. Timer B-related registers (2)
94
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 10-1.) Figure 10-4 shows
the timer Bi mode register in timer mode.
Table 10-1. Timer specifications in timer mode
Item
Count source
Count operation
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TBiIN pin function
Read from timer
Write to timer
Specification
f2, f8, f32, fC32
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
1/(n+1) n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
The timer underflows
Programmable I/O port
Count value is read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
TBiMR(i=0 to 5)
Bit symbol
TMOD0
Address
039B16 to 039D16
01DB16 to 01DD16
Bit name
Operation mode select bit
TMOD1
MR0
When reset
00XX00002
00XX00002
Function
R
b1 b0
0 0 : Timer mode
MR1
Invalid in timer mode
Can be “0” or “1”
MR2
0 (Fixed to “0” in timer mode ; i = 0, 3)
(Note 1)
Nothing is assiigned (i = 1, 2, 4, 5).
This bit can neither be set nor reset. When read, its content is indeterminate.
MR3
Invalid in timer mode.
This bit can neither be set nor reset. When read in timer mode,
its content is indeterminate.
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f2
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 10-4. Timer Bi mode register in timer mode
95
(Note 2)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 10-2.) Figure
10-5 shows the timer Bi mode register in event counter mode.
Table 10-2. Timer specifications in event counter mode
Item
Count source
Specification
• External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Count source input
Read from timer
Count value can be read out by reading timer Bi register
Write to timer
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
TBiMR(i=0 to 5)
Address
039B16 to 039D16
01DB16 to 01DD16
Bit symbol
Bit name
TMOD0
Operation mode select bit
TMOD1
MR0
Count polarity select
bit (Note 1)
MR1
MR2
MR3
When reset
00XX00002
00XX00002
Function
0 1 : Event counter mode
b3 b2
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
0 (Fixed to “0” in event counter mode; i = 0, 3)
Nothing is assigned (i = 1, 2, 4, 5).
This bit can neither be set nor reset. When read, its content is
indeterminate.
Invalid in event counter mode.
This bit can neither be set nor reset. When read in event
counter mode, its content is indeterminate.
TCK0
Invalid in event counter mode.
Can be “0” or “1”.
TCK1
Event clock select
0 : Input from TBiIN pin (Note 4)
1 : TBj overflow
(j = i – 1; however, j = 2 when i = 0,
j = 5 when i = 3)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Note 4: Set the corresponding port direction register to “0”.
Figure 10-5. Timer Bi mode register in event counter mode
96
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(Note 2)
(Note 3)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 10-3.)
Figure 10-6 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 107 shows the operation timing when measuring a pulse period. Figure 10-8 shows the operation timing
when measuring a pulse width.
Table 10-3. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f2, f8, f32, fc32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function
Measurement pulse input
Read from timer
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
TBiMR(i=0 to 5)
Bit symbol
TMOD0
TMOD1
MR0
Address
039B16 to 039D16
01DB16 to 01DD16
Bit name
Operation mode
select bit
Measurement mode
select bit
MR1
MR2
When reset
00XX00002
00XX00002
Function
b3 b2
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
Nothing is assigned (i = 1, 2, 4, 5).
This bit can neither be set nor reset. When read, its content is indeterminate.
Timer Bi overflow
flag ( Note 1)
TCK0
Count source
select bit
TCK1
W
1 0 : Pulse period / pulse width
measurement mode
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0, 3)
MR3
R
b1 b0
(Note 2)
(Note 3)
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
0 0 : f2
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Figure 10-6. Timer Bi mode register in pulse period/pulse width measurement mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
When measuring measurement pulse time interval from falling edge to falling edge
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
Count start flag
“0”
Timer Bi interrupt
request bit
“1”
Timer Bi overflow flag
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 10-7. Operation timing when measuring a pulse period
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
counter
Transfer
(indeterminate
value)
(Note 1)
Transfer
(measured value)
(Note 1)
Transfer
(measured
value)
(Note 1)
Transfer
(measured value)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 10-8. Operation timing when measuring a pulse width
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
Timers’ functions for three-phase motor control
Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor driving
waveforms.
Figures 11-1 through 11-3 show registers related to timers for three-phase motor control.
Three-phase PWM control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
INVC0
01C816
0016
Bit symbol
INV00
Bit name
Description
R
W
Effective interrupt output 0: A timer B2 interrupt occurs when the timer
polarity select bit
A1 reload control signal is 0 .
1: A timer B2 interrupt occurs when the timer
A1 reload control signal is 1 .
Effective only in three-phase mode 1
INV01
Effective interrupt output 0: Not specified.
specification bit
1: Selected by the effective interrupt output
polarity selection bit.
Effective only in three-phase mode 1
INV02
Mode select bit
(Note 2)
0: Normal mode
1: Three-phase PWM output mode
INV03
Output control bit
0: Output disabled
1: Output enabled
INV04
Bit to enable the function 0: Feature disabled
1: Feature enabled
for concurrent L output
disablement of positive
and negative phases
INV05
Flag to detect concurrent 0: Not detected yet
L output of positive and 1: Already detected
negative phases
INV06
Modulation mode select
bit (Note 3)
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
INV07
Software trigger bit
1: Trigger generated
The value, when read, is 0 .
(Note 1)
Note 1: No value other than 0 can be written.
Note 2: Selecting three-phase PWM output mode causes P80, P81, and P72 through P75 to output U, U, V, V, W, and W, and
works the timer for setting short circuit prevention time, the U, V, W phase output control circuits, and the circuit for
setting timer B2 interrupt frequency.
Note 3: In triangular wave modulation mode:
The short circuit prevention timer starts in synchronization with the falling edge of timer Ai output.
The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in
synchronization with the transfer trigger signal after writing to the three-phase output buffer register.
In sawtooth wave modulation mode:
The short circuit prevention timer starts in synchronization with the falling edge of timer A output and with the transfer trigger signal.
The data transfer from the three-phase output buffer register to the three-phase output shift register i
every transfer trigger.
s made with respect to
Note 4: To write 1 both to bit 0 (INV00) and bit 1 (INV01) of the three-phase PWM control register, set in advance the content of the timer
B2 interrupt occurrences frequency set counter.
Three-phase
b7
b6
b5
b4
0
b3
PWM control register 1
b2
b1
b0
Symbol
Address
When reset
INVC1
01C916
0016
Bit symbol
Bit name
Description
INV10
Timer Ai start trigger
signal select bit
0: Timer B2 overflow signal
1: Timer B2 overflow signal,
signal for writing to timer B2
INV11
Timer A1-1, A2-1, A4-1
control bit
0: Three-phase mode 0
1: Three-phase mode 1
INV12
Short circuit timer count
source select bit (Note 1)
0 : inhibited
1 : f2/2
Noting is assigned.
These bits can be set nor reset. When read, their contents are indeterminate.
Reserved bit
Always set to 0
Noting is assigned.
In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .
Note 1: To use three-phase PWM output mode, write 1 to INV12.
Figure 11-1. Registers related to timers for three-phase motor control
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
Three-phase output buffer register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IDB0
Address
01CA16
When reset
0016
Bit Symbol
Bit name
Function
DU0
U phase output buffer 0
Setting in U phase output buffer 0
DUB0
U phase output buffer 0
Setting in U phase output buffer 0
DV0
V phase output buffer 0
Setting in V phase output buffer 0
DVB0
V phase output buffer 0
Setting in V phase output buffer 0
DW0
W phase output buffer 0
Setting in W phase output buffer 0
DWB0
W phase output buffer 0
Setting in W phase output buffer 0
R
W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note: When executing read instruction of this register, the contents of three-phase shift
register is read out.
Three-phase output buffer register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IDB1
Address
01CB16
When reset
0016
Bit Symbol
Bit name
Function
DU1
U phase output buffer 1
Setting in U phase output buffer 1
DUB1
U phase output buffer 1
Setting in U phase output buffer 1
DV1
V phase output buffer 1
Setting in V phase output buffer 1
DVB1
V phase output buffer 1
Setting in V phase output buffer 1
DW1
W phase output buffer 1
Setting in W phase output buffer 1
DWB1
W phase output buffer 1
Setting in W phase output buffer 1
R
W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note: When executing read instruction of this register, the contents of three-phase shift
register is read out.
Dead time timer
by
by
Symbol
DOT
Address
01CC16
Function
When reset
Indeterminate
Values that can be set
Set dead time timer
R
W
R
W
1 to 255
Timer B2 interrupt occurrences frequency set counter
by
by
Symbol
ICTB2
Address
01CD16
Function
Set occurrence frequency of timer B2
interrupt request
When reset
Indeterminate
Values that can be set
1 to 15
Note1: In setting 1 to bit 1 (INV01) - the effective interrupt output specification bit - of threephase PWM control register 0, do not change the B2 interrupt occurrences frequency
set counter to deal with the timer function for three-phase motor control.
Note2: Do not write at the timing of an overflow occurrence in timer B2.
Figure 11-2. Registers related to timers for three-phase motor control
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
Timer Ai register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA1
TA2
TA4
TB2
Address
038916,038816
038B16,038A16
038F16,038E16
039516,039416
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
Values that can be set
• Timer mode
Counts an internal count source
000016 to FFFF16
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
R W
@
Note: Read and write data in 16-bit units.
Timer Ai-1 register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA11
TA21
TA41
Address
01C3 16,01C216
01C5 16,01C416
01C7 16,01C616
Function
When reset
Indeterminate
Indeterminate
Indeterminate
Values that can be set
Counts an internal count source
000016 to FFFF16
R W
@
Note: Read and write data in 16-bit units.
Trigger select register
b7
b6
b5
b4
b3
b2
b1
Symbol
TRGSR
b0
Bit symbol
TA1TGL
Address
038316
When reset
0016
Bit name
Timer A1 event/trigger
select bit
TA1TGH
TA2TGL
0
1
0
1
b3 b2
Timer A3 event/trigger
select bit
b5 b4
Timer A4 event/trigger
select bit
b7 b6
TA3TGH
TA4TGL
0
0
1
1
Timer A2 event/trigger
select bit
TA2TGH
TA3TGL
Function
TA4TGH
R W
b1 b0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
:
:
:
:
Input on TA1IN is selected (Note)
:
:
:
:
Input on TA2IN is selected (Note)
TB2 overflow is selected
TA0 overflow is selected
TA2 overflow is selected
TB2 overflow is selected
TA1 overflow is selected
TA3 overflow is selected
: Input on TA3IN is selected (Note)
: TB2 overflow is selected
: TA2 overflow is selected
: TA4 overflow is selected
:
:
:
:
Input on TA4IN is selected (Note)
TB2 overflow is selected
TA3 overflow is selected
TA0 overflow is selected
Note: Set the corresponding port direction register to “0”.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit symbol
Address
038016
When reset
0016
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
0 : Stops counting
1 : Starts counting
Figure 11-3. Registers related to timers for three-phase motor control
101
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
Three-phase motor driving waveform output mode (three-phase waveform mode)
Setting “1” in the mode select bit - bit 2 of three-phase PWM control register 0 (01C816) shown in Fig. 111 - causes three-phase waveform mode that uses four timers A1, A2, A4, and B2 to be selected. As shown
in Figure 11-4, set timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer
B2 in timer mode using the respective timer mode registers.
Timer Ai mode register
b7
b6
b5
b4
b3
b2
0 1
b1
Symbol
TA1MR
TA2MR
TA4MR
b0
1 0
Bit symbol
TMOD0
TMOD1
Address
039716
039816
039A16
When reset
0016
0016
0016
Function
Bit name
Operation mode
select bit
RW
b1 b0
1 0 : One-shot timer mode
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
External trigger select
bit (Note 2)
0 : Falling edge of TAiIN pin’s input signal (Note 3)
1 : Rising edge of TAiIN pin’s input signal (Note 3)
MR2
Trigger select bit
1 : Selected by event/trigger select
register
MR3
0 (Must always be 0 in one-shot timer mode)
TCK0
Count source select bit
b7 b6
TCK1
0 0 : f2
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be 1 or 0 .
Note 3: Set the corresponding port direction register to 0 .
Timer B2 mode register
b7
b6
b5
b4
0
b3
b2
b1
b0
0 0
Symbol
TB2MR
Bit symbol
TMOD0
Address
039D16
Bit name
Operation mode select bit
TMOD1
MR0
When reset
00XX00002
Function
b1 b0
0 0 : Timer mode
MR1
Invalid in timer mode
Can be 0 or 1
MR2
0 (Fixed to 0 in timer mode ; i = 0)
MR3
Invalid in timer mode.
This bit can neither be set nor reset. When read in timer mode,
its content is indeterminate.
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f2
0 1 : f8
1 0 : f32
1 1 : fC32
Figure 11-4. Timer mode registers in three-phase waveform mode
102
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
Figure 11-5 shows the block diagram for three-phase waveform mode. In three-phase waveform mode, the
positive-phase waveforms (U phase, V phase, and W phase) and negative waveforms (U phase, V phase,
and W phase), six waveforms in total, are output from P80, P81, P72, P73, P74, and P75 as active on the
“L” level. Of the timers used in this mode, timer A4 controls the U phase and U phase, timer A1 controls the
V phase and V phase, and timer A2 controls the W phase and W phase respectively; timer B2 controls the
periods of one-shot pulse output from timers A4, A1, and A2.
In outputting a waveform, dead time can be set so as to cause the “L” level of the positive waveform output
(U phase, V phase, and W phase) not to lap over the “L” level of the negative waveform output (U phase,
V phase, and W phase).
To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value
from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead
time works as a one-shot timer. If a value is written to the dead timer (01CC16), the value is written to the
reload register shared by the three timers for setting dead time.
Any of the timers for setting dead time takes the value of the reload register into its counter, if a start
trigger comes from its corresponding timer, and performs a down count in line with the clock source
selected by the dead time timer count source select bit (bit 2) of three-phase PWM control register 1
(01C916). The timer can receive another trigger again before the workings due to the previous trigger are
completed. In this instance, the timer performs a down count from the reload register’s content after its
transfer, provoked by the trigger, to the timer for setting dead time.
Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger
comes; it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger to
come.
The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V
phase, and W phase) in three-phase waveform mode are output from respective ports by means of setting
“1” in the output control bit (bit 3) of three-phase PWM control register 0 (01C816). Setting “0” in this bit
causes the ports to be the state of set by port direction register. This bit can be set to “0” not only by use
of the applicable instruction, but by entering a falling edge in the NMI terminal or by resetting. Also, if “1” is
set in the positive and negative phases concurrent L output disable function enable bit (bit4) of threephase PWM control register 0 (01C816) causes one of the pairs of U phase and U phase, V phase and V
phase, and W phase and W phase concurrently go to “L”, as a result, the output control bit become the
state of set by port direction register.
103
(Timer mode)
Timer B2
Figure 11-5. Block diagram for three-phase waveform mode
104
Trigger
Reload
Timer A4 counter
Timer A4-1
Timer A1-1
Timer A1 counter
Reload
To be set to “0” when
timer A4 stops
T Q
INV11
INV11
Timer A2-1
T Q
To be set to “0” when
timer A2 stops
INV11
1/2
1
Trigger signal for
transfer
f2
INV12
0
T
Q
T
Q
T
Q
T
Q
U phase output signal
Three-phase output
shift register
(U phase)
U phase output signal
U phase output
control circuit
W phase output signal
W phase output signal
n = 1 to 255
Timer for setting short
circuit prevention time (8)
For short circuit
prevention
V phase output signal
V phase output signal
n = 1 to 255
Timer for setting short
circuit prevention time (8)
D
DUB0
D
DU0
V phase output
control circuit
D
DUB1
D
DU1
T
D Q
D Q
T
D Q
T
D Q
T
T
D Q
D Q
T
INV05
Interrupt request bit
Bit 0 of three-phase
output buffer register 0
Bit 0 of three-phase
output buffer register 1
Timer for setting short
circuit prevention time
n = 1 to 255
Reload register
n = 1 to 255
Counter for setting the frequency
of interrupt occurrences
n = 1 to 15
U phase output control circuit
0
1
Circuit for setting the frequency
of interrupt occurrences
INV03
R
D
Q
W(P75)
W(P74)
V(P73)
V(P72)
U(P81)
U(P80)
Diagram for switching to P80, P81, and to P72 - P75 is not shown.
INV04
RESET
NMI
Specifications in this manual are tentative and subject to change.
(One-shot timer mode)
Timer A2 counter
Reload
To be set to “0” when
timer A1 stops
T Q
(One-shot timer mode)
Timer A2
Trigger
INV00
Control signal for timer A4 reload
INV07
(One-shot timer mode)
Timer A1
Trigger
Timer A4
Trigger signal for
timer Ai start
INV10
Signal to be
written to B2
Overflow
INV01
INV11
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Preliminary Specifications REV.B
Mitsubishi microcomputers
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C / 6N Group
Timers’ functions for three-phase motor control
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
Triangular wave modulation
To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit (bit 6)
of three-phase PWM control register 0 (01C816). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit
1) of three-phase PWM control register 1 (01C916). In this mode, each of timers A4, A1, and A2 has two
timer registers, and alternately reloads the timer register’s content to the counter every time timer B2
counter’s content becomes 000016. If “1” is set to the effective interrupt output specification bit (bit 1) of
three-phase PWM control register 0 (01C816), the frequency of interrupt requests that occur every time the
timer B2 counter’s value becomes 000016 can be set by use of the timer B2 counter (01CD16) for setting the
frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting p 0).
Setting “1” in the effective interrupt output specification bit (bit 1) of three-phase PWM control register 0
provides the means to choose which value of the timer A1 reload control signal to use, “0” or “1”, to cause
timer B2’s interrupt request to occur. To make this selection, use the effective interrupt output polarity
selection bit (bit 0) of three-phase PWM control register 0 (01C816).
An example of U phase waveform is shown in Figure 11-6, and the description of waveform output workings
is given below. Set “1” in bit 0 (DU0) of three-phase output buffer register 0 (01CA16). and set “0” in bit 1
(DUB0) of the same register. In addition, set “0” in bit 0 (DU1) of three-phase output buffer register 1
(01CB16) and set “1” in bit 1 (DUB1) of the same register. Also, set “0” in the effective interrupt output
specification bit (bit 1) of three-phase PWM control register 0 to set a value in the timer B2 interrupt
occurence frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s
content becomes 000016 as many as (setting) times. Furthermore, set “1” in the effective interrupt output
specification bit (bit 1) of three-phase PWM control register 0, set in the effective interrupt polarity select bit
(bit 0) of three-phase PWM control register 0 and set "1" in the interrupt occurence frequency set counter
(01CD16). These settings cause a timer B2 interrupt to occur every other interval when the U phase output
goes to “H”.
When the timer B2 counter’s content becomes 000016, timer A4 starts outputting one-shot pulses. In this
instance, the content of the three-phase buffer register DU1 and that of DU0 are set in the three-phase
output shift register (U phase), the content of DUB1 and that of DUB0 are set in the three-phase shift register
(U phase). After triangular wave modulation mode is selected, however, no setting is made in the shift
register even though the timer B2 counter’s content becomes 000016.
The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when timer A4
finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position, and the
value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output signal
respectively. At the same time, one-shot pulses are output from the timer for setting dead time used for
setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level of the U phase
waveform, which has the opposite phase of the former. The U phase waveform output that started from the
“H” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though
the three-phase output shift register’s content changes from “1” to “0” by the effect of the one-shot pulses.
When the timer for setting dead time finishes outputting one-shot pulses, "0" already shifted in the threephase shift register goes effective, and the U phase waveform changes to the "L" level. When the timer B2
counter’s content becomes 000016, the timer A4 counter starts counting the value written to timer A4-1
(01C116, 01C016), and starts outputting one-shot pulses. When timer A4 finishes outputting one-shot
pulses, the three-phase shift register’s content is shifted one position, but if the three-phase output shift
register’s content changes from “0” to “1” as a result of the shift, the output level changes from “L” to “H”
without waiting for the timer for setting dead time to finish outputting one-shot pulses. A U phase waveform
105
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
is generated by these workings repeatedly. With the exception that the three-phase output shift register on
the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of
the U phase waveform, are the same as in generating a U phase waveform . In this way, a waveform can be
picked up from the applicable terminal in a manner in which the L level of the U phase waveform doesn’t lap
over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the
“L” level too can be adjusted by varying the values of timer B2, timer A4, and timer A4-1. In dealing with the
V and W phases, and V and W phases, the latter are of opposite phase of the former, have the
corresponding timers work similarly to dealing with the U and U phases to generate an intended waveform.
A carrier wave of triangular waveform
Carrier wave
Signal wave
Timer B2
Timber B2 interrupt occurres
Rewriting timer A4 and timer A4-1.
Possible to set the number of overflows to generate an
interrupt by use of the interrupt occurrences frequency
set circuit
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Timer A4 output
m
n
m
n
m
p
o
Control signal for
timer A4 reload
U phase
output signal
U phase
output signal
U phase
U phase
Dead time
Trigger signal: set to triangular wave modulation mode and to three-phase mode 1
Figure 11-6. Timing chart of operation (1)
106
The three-phase
shift register
shifts in
synchronization
with the falling
edge of the A4
output.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
Assigning certain values to DU0 (bit0) of three-phase output buffer register 0 (01CA16) and DUB0 (bit1) of the
same register, and to DU1 (bit0) of three-phase output buffer register 1 (01CB16) and DUB1 (bit1) of the same
register allows you to output the waveforms as shown in the Figure 11-7, that is, to output the U phase alone,
to fix U phase to "H", to fix the U phase to "H", or to output the U phase alone.
A carrier wave of triangular waveform
Carrier wave
Signal wave
Timer B2
Rewriting timer A4 every timer B2 interrupt occurres.
Timer B2 interrupt occurres.
Rewriting three-phase buffer register.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Timer A4 output
m
n
m
n
m
p
Control signal for
timer A4 reload
U phase
output signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to triangular wave modulation mode and to three-phase mode 1.
Figure 11-7. Timing chart of operation (2)
107
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
Sawtooth modulation
To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit
6) of three-phase PWM control register 0 (01C816). Also, set “0” in the timers A4, A1, and A2-1 control bit
(bit 1) of three-phase PWM control register 1 (01C916). In this mode, the timer registers of timers A4, A1,
and of A2 comprise conventional timers A4, A1, and A2 alone, and reload the corresponding timer
register’s content to the counter every time the timer B2 counter’s content becomes 000016. The effective
interrupt output specification bit (bit 1) of three-phase PWM control register 0 (01C816) and the effective
interrupt output polarity selection bit (bit 0) turn nullified.
An example of U phase waveform is shown in Figure 11-8, and the description of waveform output
workings is given below. Set “1” in bit 0 (DU0) of three-phase output buffer register 0 (01CA16), and set
“0” in bit 1 (DUB0) of the same register. In addition, set “0” in bit 0 (DU1) of three-phase output buffer
register 1 (01CA16) and set “1” in bit 1 (DUB1) of the same register.
When the timber B2 counter’s content becomes 000016, timer B2 generates an interrupt, and timer A4
starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer
registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of
DUB1 and DUB0 are set in the three-phase output register (U phase). After this, the three-phase buffer
register’s content is set in the three-phase shift register every time the timer B2 counter’s content becomes 000016.
The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when
timer A4 finishes outputting one-shot pulses, the three-phase output shift register’s content is shifted one
position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U
output signal respectively. At the same time, one-shot pulses are output from the timer for setting dead
time used for setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L”
level of the U phase waveform, which has the opposite phase of the former. The U phase waveform
output that started from the “H” level keeps its level until the timer for setting dead time finishes outputting
one-shot pulses even though the three-phase output shift register’s content changes from “1” to “0 ”by
the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot
pulses, 0 already shifted in the three-phase shift register goes effective, and the U phase waveform
changes to the “L” level. When the timer B2 counter’s content becomes 000016, the contents of the threephase buffer registers DU1 and DU0 are set in the three-phase shift register (U phase), and the contents
of DUB1 and DUB0 are set in the three-phase shift register (U phase) again.
A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase
output shift register on the U phase side is used, the workings in generating a U phase waveform, which
has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In
this way, a waveform can be picked up from the applicable terminal in a manner in which the “L” level of
the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of
the U phase waveform. The width of the “L” level too can be adjusted by varying the values of timer B2
and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase
of the former, have the corresponding timers work similarly to dealing with the U and U phases to generate an intended waveform.
Setting “1” both in bit 1 (DUB0) of three-phase buffer register 0 (01CA16) and in bit 1 (DUB1) of threephase buffer register 1 (01CA16) provides a means to output the U phase alone and to fix the U phase
output to “H” as shown in Figure 11-9.
108
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
A carrier wave of sawtooth waveform
Carrier wave
Signal wave
Timer B2
Interrupt occurres.
Rewriting the value of timer A4.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Timer A4 output
m
n
Data transfer is made from the threephase buffer register to the threephase shift register in step with the
timing of the timer B overflow.
o
U phase output
signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to sawtooth modulation mode and to three-phase mode 0.
Figure 11-8. Timing chart of operation (3)
109
p
The three-phase
shift register
shifts in
synchronization
with the falling
edge of timer A4.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
A carrier wave of sawtooth waveform
Carrier wave
Signal wave
Timer B2
Interrupt occurres.
Rewriting the value of timer A4.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Timer A4 output
Interrupt occurres.
Rewriting the value of timer A4.
Rewriting three-phase
output buffer register
m
n
Data transfer is made from the threephase buffer register to the threephase shift register in step with the
timing of the timer B overflow.
p
U phase
output signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to sawtooth modulation mode and to three-phase mode 0.
Figure 11-9. Timing chart of operation (4)
110
The three-phase
shift register shifts
in synchronization
with the falling
edge of timer A4.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured as four channels: UART0, UART1, UART2 and S I/O3.
UART0 to 2
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate
independently of each other.
Figure 12-1 shows the block diagram of UART0, UART1 and UART2. Figures 12-2 and 12-3 show the block
diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016, 03A816 and 01F816) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions.
UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is
compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode
(Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and
the RxD pin are different in level.
Table 12-1 shows the comparison of functions of UART0 through UART2, and Figures 12-4 through 12-8
show the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Table 12-1. Comparison of functions of UART0 through UART2
Function
UART0
UART1
UART2
CLK polarity selection
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 1)
LSB first / MSB first selection
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 2)
Continuous receive mode selection
Possible
(Note 1)
Possible
(Note 1)
Possible
(Note 1)
Transfer clock output from multiple
pins selection
Impossible
Possible
(Note 1)
Impossible
Separate CTS/RTS pins
Possible
Impossible
Impossible
Serial data logic switch
Impossible
Impossible
Possible
Sleep mode selection
Possible
TxD, RxD I/O polarity switch
Impossible
TxD port output format
N-channel open-drain N-channel open-drain
/CMOS output
/CMOS output
N-channel open-drain
/CMOS output
Parity error signal output
Impossible
Impossible
Possible
Bus collision detection
Impossible
Impossible
Possible
(Note 3)
Possible
(Note 3)
Impossible
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
111
(Note 4)
Impossible
Possible
(Note 4)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
(UART0)
RxD0
TxD0
UART reception
1/16
Clock source selection
Reception
control circuit
Clock synchronous type
Bit rate generator
Internal (address 03A1 16 )
f2SIO
f8SIO
f32SIO
1/(n0 +1)
UART transmission
1/16
Transmission
control circuit
Clock synchronous type
External
Receive
clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
CLK0
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS selected
RTS0
CTS0 /RTS 0
Vcc
CTS/RTS disabled
CTS0
CTS/RTS separated
CTS0 from UART1
(UART1)
RxD1
TxD1
Clock source selection
Bit rate generator
Internal (address 03A9 16)
f2SIO
f8SIO
f32SIO
UART reception
1/16
1/(n 1 +1)
UART transmission
1/16
CTS1 /RTS1
/CTS 0 /CLKS1
Clock synchronous type
(when internal clock is selected)
Transmit
clock
Clock synchronous type
(when external clock is
selected)
CTS/RTS disabled
CTS/RTS separated
Clock output pin
select switch
Transmit/
receive
unit
(when internal clock is selected)
1/2
CLK1
Transmission
control circuit
Clock synchronous type
Clock synchronous type
External
CLK
polarity
reversing
circuit
Reception
control circuit
Clock synchronous type
Receive
clock
RTS1
VCC
CTS/RTS disabled
CTS0
CTS1
CTS0 to UART0
(UART2)
RxD2
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
UART reception
1/16
Clock source selection
Bit rate generator
Internal (address 01F916)
f2SIO
f8SIO
f32SIO
1/(n2 +1)
Clock synchronous type
UART transmission
1/16
Clock synchronous type
External
Reception
control circuit
Transmission
control circuit
Receive
clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
1/2
CLK2
CLK
polarity
reversing
circuit
(when internal clock is selected)
Clock synchronous type
(when internal clock is selected)
CTS/RTS
selected
Clock synchronous type
(when external clock is
selected)
CTS/RTS disabled
RTS2
CTS2 /RTS 2
Vcc
CTS/RTS disabled
CTS2
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
Figure 12-1. Block diagram of UARTi (i = 0 to 2)
112
TxD2
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Clock
synchronous type
PAR
disabled
1SP
RxDi
SP
SP
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
UARTi receive register
UART (7 bits)
PAR
2SP
PAR
enabled
UART
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive
buffer register
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
D1
UART (9 bits)
2SP
SP
SP
Clock synchronous
type
UART
TxDi
PAR
1SP
UARTitransmit
buffer register
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
UART (8 bits)
UART (9 bits)
PAR
enabled
D0
PAR
disabled
“0”
Clock
synchronous
type
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
Clock synchronous
type
Figure 12-2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
113
SP: Stop bit
PAR: Parity bit
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
No reverse
RxD data
reverse circuit
RxD2
Reverse
Clock
synchronous type
PAR
disabled
1SP
SP
SP
Clock
synchronous
type
UART2 receive register
UART(7 bits)
PAR
2SP
PAR
enabled
0
UART
(7 bits)
UART
(8 bits)
0
0
0
UART
0
Clock
synchronous type
UART
(9 bits)
0
0
UART
(8 bits)
UART
(9 bits)
D8
D0
UART2 receive
buffer register
Logic reverse circuit + MSB/LSB conversion circuit
Address 01FE16
Address 01FF16
D7
D6
D5
D4
D3
D2
D1
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
D1
D0
UART2transmit
buffer register
Address 01FA16
Address 01FB16
UART
(8 bits)
UART
(9 bits)
PAR
enabled
2SP
SP
SP
UART
(9 bits)
Clock
synchronous type
UART
PAR
1SP
PAR
disabled
“0”
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
UART2 transmit register
UART(7 bits)
Clock
synchronous type
Error signal output
disable
No reverse
TxD data
reverse circuit
Error signal
output circuit
Error signal output
enable
Reverse
SP: Stop bit
PAR: Parity bit
Figure 12-3. Block diagram of UART2 transmit/receive unit
114
TxD2
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0TB
U1TB
U2TB
Address
03A316, 03A216
03AB16, 03AA16
01FB16, 01FA16
When reset
Indeterminate
Indeterminate
Indeterminate
Function
R W
Transmit data (Note)
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
Note: Bit 8 is set to “1” when I2C mode is used.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
U2RB
b0
Bit
symbol
Address
03A716, 03A616
03AF16, 03AE16
01FF16, 01FE16
When reset
Indeterminate
Indeterminate
Indeterminate
Function
(During clock synchronous
serial I/O mode)
Bit name
Receive data
Function
(During UART mode)
R W
Receive data
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
ABT
Arbitration lost detecting
flag (Note 2)
OER
Overrun error flag (Note 1) 0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
FER
Framing error flag (Note 1) Invalid
0 : No framing error
1 : Framing error found
PER
Parity error flag (Note 1)
Invalid
0 : No parity error
1 : Parity error found
SUM
Error sum flag (Note 1)
Invalid
0 : No error
1 : Error found
0 : Not detected
1 : Detected
Invalid
Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016,
03A816 and 01F816) are set to “0002” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 01FE16) is read out.
Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is
assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value
of this bit is “0”.
UARTi bit rate generator
b7
b0
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
01F916
When reset
Indeterminate
Indeterminate
Indeterminate
Function
Assuming that set value = n, BRGi divides the count source by
n+1
Figure 12-4. Serial I/O-related registers (1)
115
Values that can be set
0016 to FF16
RW
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Bit name
SMD0
Serial I/O mode select bit
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
Function
(During UART mode)
R W
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit Invalid
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
Must always be “0”
0 : Sleep mode deselected
1 : Sleep mode selected
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
UART2 transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
U2MR
b0
Address
01F816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Bit name
SMD0
Serial I/O mode select bit
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : (Note)
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
Function
(During UART mode)
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit Invalid
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
Usually set to “0”
0 : No reverse
1 : Reverse
Usually set to “0”
Note: Bit 2 to bit 0 are set to “0102” when I2C mode is used.
Figure 12-5. Serial I/O-related registers (2)
116
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiC0(i=0,1)
Bit
symbol
CLK0
Address
03A416, 03AC16
Function
(During clock synchronous
serial I/O mode)
Bit name
b1 b0
BRG count source
select bit
CLK1
CRS
TXEPT
When reset
0816
CTS/RTS function
select bit
Transmit register empty
flag
Function
(During UART mode)
R W
b1 b0
0 0 : f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Inhibited
0
0
1
1
0
1
0
1
:
:
:
:
f2SIO is selected
f8SIO is selected
f32SIO is selected
Inhibited
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
programmable I/O port)
NCH
Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
CKPOL
CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U2C0
Bit
symbol
CLK0
Address
01FC16
Bit name
BRG count source
select bit
CLK1
CRS
TXEPT
CTS/RTS function
select bit
Transmit register empty
flag
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
b1 b0
b1 b0
0 0 : f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Inhibited
0
0
1
1
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0
1
0
1
:
:
:
:
f2SIO is selected
f8SIO is selected
f32SIO is selected
Inhibited
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions programmable
I/O port)
NCH
Data output select bit
0 : TXDi
pin is
CMOS
output
TXD2/RXD
2 pin
is CMOS
output
1 : TXDi
pin is N-channel
TXD2/RXD2
pin is N-channel
open-drainoutput
output
open-drain
(Note 4)
pin is
CMOS
output
00:: TXDi
TXD2/RXD
2 pin
is CMOS
output
pin is N-channel
11:: TXDi
TXD2/RXD2
pin is N-channel
open-drain
output
open-drain
output
CKPOL
CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
(Note 3)
0 : LSB first
1 : MSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Note 4: For Flash chips P71 can only be Nch open drain output!
Figure 12-6. Serial I/O-related registers (3)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
UiC1(i=0,1)
b0
Bit
symbol
Address
03A516,03AD16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit name
Function
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
R W
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
UART2 transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
U2C1
b0
Bit
symbol
Address
01FD16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit name
Function
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
U2ERE Error signal output
enable bit
Must be fixed to “0”
0 : Output disabled
1 : Output enabled
U2IRS UART2 transmit interrupt
cause select bit
Figure 12-7. Serial I/O-related registers (4)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UART transmit/receive control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UCON
Bit
symbol
U0IRS
Address
03B016
When reset
X00000002
Function
(During clock synchronous
serial I/O mode)
Bit
name
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS
(TXEPT = 1)
Function
(During UART mode)
RW
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
CLKMD0 CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1 CLK/CLKS select
bit 1 (Note)
0 : Normal mode
Must always be “0”
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
RCSP
Separate CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Bit
symbol
Address
01F716
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
name
Function
(During UART mode)
IICM
IIC mode selection bit
0 : Normal mode
1 : IIC mode
Must always be “0”
ABC
Arbitration lost detecting
flag control bit
0 : Update per bit
1 : Update per byte
Must always be “0”
BBS
Bus busy flag
0 : STOP condition detected
1 : START condition detected
Must always be “0”
SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Must always be “0”
ABSCS
Bus collision detect
sampling
clock select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
Auto clear function
select bit of transmit
enable bit
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
SSS
Transmit start condition
select bit
Must always be “0”
0 : Ordinary
1 : Falling edge of RxD2
LSYN
(Note)
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
Note: Nothing but "0" may be written.
Figure 12-8. Serial I/O-related registers (5)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
Serial synchronous
I/O
serial I/O mode
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 12-2
and 12-3 list the specifications of the clock synchronous serial I/O mode. Figure 12-9 shows the UARTi
transmit/receive mode register.
Table 12-2. Specifications of clock synchronous serial I/O mode (1)
Item
Transfer data format
Transfer clock
Transmission/reception control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Specification
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 01F816
= “0”) : fi/ 2(n+1) (Note 1) fi = f2SIO, f8SIO, f32SIO
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 01F816
= “1”) : Input from CLKi pin (Note 2)
• CTS function/RTS function/CTS, RTS function chosen to be invalid
• To start transmission, the following requirements must be met:
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 01FD16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 01FD16) = “0”
_
When CTS function selected, CTS input level = “L”
• Furthermore, if external clock is selected, the following requirements must also be met:
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = “0”:
CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = “1”:
CLKi input level = “L”
• To start reception, the following requirements must be met:
_
Receive enable bit (bit 2 at addresses 03A516, 03AD16, 01FD16) = “1”
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 01FD16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 01FD16) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = “0”:
CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = “1”:
CLKi input level = “L”
• When transmitting
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 01FD16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 01FD16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: Maximum 5 Mbps.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
Table 12-3. Specifications of clock synchronous serial I/O mode (2)
Item
Select function
Specification
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
• Separate CTS/RTS pins (UART0) (Note)
UART0 CTS and RTS pins each can be assigned to separate pins
• Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TxD, RxD I/O polarity reverse (UART2)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
Note: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
UARTi transmit/receive mode registers
b7
b6
b5
b4
b3
0
b2
b1
b0
0 0 1
Symbol
UiMR(i=0,1)
Bit symbol
SMD0
Address
03A016, 03A816
When reset
0016
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
Internal/external clock
select bit
Function
RW
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Must always be “0” in clock synchronous serial I/O mode)
UART2 transmit/receive mode register
b7
0
b6
b5
b4
b3
b2
b1
b0
0 0 1
Symbol
U2MR
Address
01F816
Bit symbol
SMD0
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Internal/external clock
select bit
Function
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
Note: Usually set to “0”.
Figure 12-9. UARTi transmit/receive mode register in clock synchronous serial I/O mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
Table 12-4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table
shows the pin functions when the transfer clock output from multiple pins and the separate CTS/RTS pins
functions are not selected. Note that for a period from when the UARTi operation mode is selected to
when transfer starts, the TxDi pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in
floating state.)
Table 12-4. Input/output pin functions in clock synchronous serial I/O mode
Pin name
Function
Method of selection
TxDi
Serial data output
(P63, P67, P70)
(Outputs dummy data when performing reception only)
Serial data input
RxDi
(P62, P66, P71)
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16,
bit 1 at address 03EF16)= “0”
(Can be used as an input port when performing transmission only)
CLKi
Transfer clock output
(P61, P65, P72)
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 01F816) = “0”
CTSi/RTSi
CTS input
(P60, P64, P73)
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 01F816) = “1”
Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16,
bit 2 at address 03EF16) = “0”
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 01FC16) = “0”
Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16,
bit 3 at address 03EF16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 01FC16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = “1”
(when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
bit (TE)
“0”
Data is set in UARTi transmit buffer register
“1”
Transmit buffer
empty flag (Tl)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
TCLK
“L”
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
CLKi
TxDi
D 0 D 1 D2 D3
Transmit
register empty
flag (TXEPT)
D4 D 5 D6 D 7
D 0 D 1 D 2 D 3 D 4 D5 D 6 D7
D 0 D 1 D2 D3
D4 D5 D6 D7
“1”
“0”
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f2, f8, f32)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
Transmit enable
bit (TE)
“0”
Transmit buffer
empty flag (Tl)
“1”
“0”
“H”
RTSi
Dummy data is set in UARTi transmit buffer register
“1”
Transferred from UARTi transmit buffer register to UARTi transmit register
“L”
1 / fEXT
CLKi
Receive data is taken in
D0 D 1 D 2 D3
RxDi
Receive complete “1”
flag (Rl)
“0”
Receive interrupt
request bit (IR)
D 4 D 5 D6 D7
Transferred from UARTi receive register
to UARTi receive buffer register
D0 D 1 D 2
D3 D 4 D5
Read out from UARTi receive buffer register
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
fEXT: frequency of external clock
Figure 12-10. Typical transmit/receive timings in clock synchronous serial I/O mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
(a) Polarity select function
As shown in Figure 12-11, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16)
allows selection of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: The CLK pin level when not
transferring data is “H”.
• When CLK polarity select bit = “1”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 2: The CLK pin level when not
transferring data is “L”.
Figure 12-11. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 12-12, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16,
01FC16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
LSB first
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
D2
D1
D0
• When transfer format select bit = “1”
CLKi
TXDi
D7
D6
D5
D4
D3
MSB first
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
Note: This applies when the CLK polarity select bit = “0”.
Figure 12-12. Transfer format
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Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
serial I/O mode
Serial synchronous
I/O
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 12-13.) The
multiple pins function is valid only when the internal clock is selected for UART1. Note that when this
function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 12-13. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 01FD16) is
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data
to the transmit buffer register back again.
(e) Separate CTS/RTS pins function (UART0)
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
(f) Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 01FD16) = “1”, and writing to transmit buffer register or
reading from receive buffer register, data is reversed. Figure 12-14 shows the example of serial data
logic switch timing.
•When LSB first
Transfer clock
“H”
“L”
TxD2
“H”
(no reverse) “L”
TxD2
“H”
(reverse) “L”
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Figure 12-14. Serial data logic switch timing
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Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 13-1 and 13-2 list the specifications of the UART mode. Figure 13-1 shows the
UARTi transmit/receive mode register.
Table 13-1. Specifications of UART Mode (1)
Item
Transfer data format
Transfer clock
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 01F816=“0”) :
fi/16(n+1) (Note 1) fi = f2SIO, f8SIO, f32SIO
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 01F816 =“1”) :
fEXT/16(n+1)(Note 1) (Note 2)
Transmission/reception control
• CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 01FD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 01FD16) = “0”
- When CTS function selected, CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 01FD16) = “1”
- Start bit detection
Interrupt request
• When transmitting
generation timing
- Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at
address 01FD16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 01FD16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Table 13-2. Specifications of UART Mode (2)
Item
Select function
Specification
• Separate CTS/RTS pins (UART0)
UART0 CTS and RTS pins each can be assigned to separate pins
• Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave microcomputers
• Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
• TxD, RxD I/O polarity switch (UART2)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
UARTi transmit / receive mode registers
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UiMR(i=0,1)
Bit symbol
SMD0
Address
03A016, 03A816
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Function
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Internal / external clock
select bit
Stop bit length select bit
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
PRY
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
0 : Sleep mode deselected
1 : Sleep mode selected
STPS
RW
UART2 transmit / receive mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U2MR
Address
01F816
Bit symbol
SMD0
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Function
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Internal / external clock
select bit
Stop bit length select bit
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
PRY
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
STPS
Note: Usually set to “0”.
Figure 13-1. UARTi transmit/receive mode register in UART mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Table 13-3 lists the functions of the input/output pins during UART mode. This table shows the pin functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the
UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-channel
open-drain is selected, this pin is in floating state.)
Table 13-3. Input/output pin functions in UART mode
Pin name
Function
TxDi
Serial data output
(P63, P67, P70)
Method of selection
RxDi
Serial data input
(P62, P66, P71)
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16,
bit 1 at address 03EF16)= “0”
(Can be used as an input port when performing transmission only)
CLKi
Programmable I/O port
(P61, P65, P72)
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 01F816) = “0”
CTSi/RTSi
CTS input
(P60, P64, P73)
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 01FC16) = “0”
Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16,
bit 3 at address 03EF16) = “0”
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 01F816) = “1”
Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16,
bit 2 at address 03EF16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 01FC16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = “1”
(when separate CTS/RTS pins function is not selected)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register.
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
“L”
Start
bit
TxDi
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
Stopped pulsing because transmit enable bit = “0”
Stop
bit
SP
P
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1
SP
“1”
Transmit register
empty flag (TXEPT)
“0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f2SIO, f8SIO, f32SIO)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
“1”
Transmit register
empty flag (TXEPT)
“0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt cause select bit = “0”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f2SIO, f8SIO, f32SIO)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Figure 13-2. Typical transmit timings in UART mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
Receive enable bit
“1”
“0”
Stop bit
Start bit
RxDi
D1
D0
D7
Sampled “L”
Receive data taken in
Transfer clock
Receive
complete flag
RTSi
Receive interrupt
request bit
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Transferred from UARTi receive register to
UARTi receive buffer register
“0”
“H”
“L”
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Figure 13-3. Typical receive timing in UART mode
(a) Separate CTS/RTS pins function (UART0)
With the separate CTS/RTS bit (bit 6 at address 03B016) is set to “1”, the unit outputs/inputs the CTS
and RTS signals on different pins. (See Figure 13-4.) This function is valid only for UART0. Note that
if this function is selected, the CTS/RTS function for UART1 cannot be used.
Microcomputer
IC
TXD0 (P63)
IN
RXD0 (P62)
OUT
RTS0 (P60)
CTS
CTS0 (P64)
RTS
Figure 13-4. The separate CTS/RTS pins function usage
(b) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(c) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 01FD16) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 13-5 shows the example of
timing for switching serial data logic.
• When LSB first, parity enabled, one stop bit
Transfer clock
“H”
“L”
TxD2
“H”
(no reverse)
“L”
TxD2
“H”
(reverse)
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST : Start bit
P : Even parity
SP : Stop bit
Figure 13-5. Timing for switching serial data logic
(d) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
(e) Bus collision detection function (UART2)
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 13-6
shows the example of detection timing of a buss collision (in UART mode).
Transfer clock
“H”
“L”
TxD2
“H”
ST
SP
ST
SP
“L”
RxD2
“H”
“L”
Bus collision detection
interrupt request signal
“1”
Bus collision detection
interrupt request bit
“1”
“0”
“0”
ST : Start bit
SP : Stop bit
Figure 13-6. Detection timing of a bus collision (in UART mode)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some
extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 13-4
shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface).
Table 13-4. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item
Transfer data format
Transfer clock
Specification
• Transfer data 8-bit UART mode (bit 2 through bit 0 of address 01F816 = “1012”)
• One stop bit (bit 4 of address 01F816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 01F8 16 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 01FD16 = “0”).
Set transfer format to LSB (bit 7 of address 01FC16 = “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 01F816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 01FD16 = “1”)
Set transfer format to MSB (bit 7 of address 01FC16 = “1”)
• With the internal clock chosen (bit 3 of address 01F816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f2, f8, f32
• With an external clock chosen (bit 3 of address 01F816 = “1”) : fEXT / 16 (n+1) (Note 1) (Note 2)
Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 01FC16 = “1”)
Other settings
• The sleep mode select function is not available for UART2
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 01FD16 = “1”)
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 01FD16) = “1”
- Transmit buffer empty flag (bit 1 of address 01FD16) = “0”
Reception start condition
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 01FD16) = “1”
- Detection of a start bit
Interrupt request
• When transmitting
generation timing
When data transmission from the UART2 transfer register is completed
(bit 4 of address 01FD16 = “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TxD 2 pin by use of the parity error
signal output function (bit 7 of address 01FD 16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RxD2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLK2 pin.
Note 3: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxD2
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P SP
P
SP
RxD2
A “L” level returns from TxD2
due to the occurrence of a parity error.
Signal conductor level
(Note 1)
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P SP
The level is
detected by the
interrupt routine.
The level is detected by the
interrupt routine.
“1”
Transmit register
empty flag (TXEPT)
“0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f2SIO, f8SIO, f32SIO)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc
Transfer clock
Receive enable
bit (RE)
“1”
“0”
Start
bit
TxD2
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P
Stop
bit
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
RxD2
A “L” level returns from TxD2
due to the occurrence of a parity error.
Signal conductor level
(Note 1)
Receive complete
flag (RI)
“1”
Receive interrupt
request bit (IR)
“1”
ST D0 D1 D2 D3 D4 D5 D6 D7
P SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
“0”
Read to receive buffer
Read to receive buffer
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
Figure 13-7. Typical transmit/receive timing in UART mode (compliant with the SIM interface)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(a) Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 01FD16) assigned “1”, you can output an “L”
level from the TxD2 pin when a parity error is detected. In step with this function, the generation timing
of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure
13-8 shows the output timing of the parity error signal.
• LSB first
Transfer
clock
“H”
RxD2
“H”
TxD2
“H”
Receive
complete flag
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
“L”
Hi-Z
“L”
“1”
“0”
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 13-8. Output timing of the parity error signal
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and
output from TxD2.
Figure 13-9 shows the SIM interface format.
Transfer
clcck
TxD2
(direct)
D0
D1
D2
D3
D4
D5
D6
D7
P
TxD2
(inverse)
D7
D6
D5
D4
D3
D2
D1
D0
P
P : Even parity
Figure 13-9. SIM interface format
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Figure 13-10 shows the example of connecting the SIM interface. Connect TxD2 and RxD2 and apply pull-up.
Microcomputer
SIM card
TxD2
RxD2
Figure 13-10. Connecting the SIM interface
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
asynchronous
serial
I/O (UART) mode
UART2
Special Mode
Register
UART2 Special Mode Register
The UART2 special mode register (address 01F716) is used to control UART2 in various ways.
Figure 13-11 shows the special UART2 mode register.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Bit
symbol
Address
01F716
When reset
X00000002
Function
(During clock synchronous
serial I/O mode)
Bit name
IICM
I 2C mode selection bit
ABC
Arbitration loss detecting 0 : Update per bit
1 : Update per byte
flag control bit
BBS
Bus busy flag
0 : Normal mode
1 : I2 C mode
Function
(During UART mode)
Must always be “0”
Must always be “0”
0 : STOP condition detected
1 : START condition detected
Must always be “0”
(Note)
LSYN
SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Must always be “0”
ABSCS
Bus collision detect
sampling clock select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
Auto clear function
select bit of transmit
enable bit
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
Transmit start condition
select bit
Must always be “0”
0 : Ordinary
1 : Falling edge of RxD2
SSS
RW
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
Note: Nothing but "0" may be written.
Figure 13-11. UART2 special mode register
Table13-5. Features in I2C mode
Function
Normal mode
I2C mode (Note 1)
Start condition detection or stop
condition detection
1
Factor of interrupt number 10 (Note 2)
Bus collision detection
2
Factor of interrupt number 15 (Note 2)
UART2 transmission
No acknowledgment detection (NACK)
3
Factor of interrupt number 16 (Note 2)
UART2 reception
Acknowledgment detection (ACK)
4
UART2 transmission output delay
Not delayed
Delayed
5
P70 at the time when UART2 is in use
TxD2 (output)
SDA (input/output) (Note 3)
6
P71 at the time when UART2 is in use
RxD2 (input)
SCL (input/output)
7
P72 at the time when UART2 is in use
CLK2
P72
8
DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request factor selection bits
UART2 reception
Acknowledgment detection (ACK)
9
Noise filter width
15ns
50ns
10 Reading P71
Reading the terminal when 0 is
assigned to the direction register
Reading the terminal regardless of the
value of the direction register
11 Initial value of UART2 output
H level (when 0 is assigned to
the CLK polarity select bit)
The value set in latch P70 when the port is
selected
Note 1: Make the settings given below when I2C mode is in use.
Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Select TXD2 as Nch. Choose the LSB First function.
Note 2: Follow the steps given below to switch from a factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous
I/O (UART) mode
UART2
Special Modeserial
Register
In the first place, the control bits related to the I2C bus(simplified I2C bus) interface are explained.
Bit 0 of the UART2 special mode register (01F716) is used as the I2C mode selection bit.
Setting “1” in the I2C mode selection bit (bit 0) goes the circuit to achieve the I2C bus interface effective.
Table 13-5 shows the relation between the I2C mode selection bit and respective control workings.
In order to configure P70 as Nch open drain output, set bit 5 (Nch) in the UART transmit/receive control
register 0 (U2C0).
Since this function uses clock-synchronous serial I/O mode, be sure to set this bit to “0” in UART mode.
P70 through P72 conforming to the simplified I 2C bus
P70/TxD2/SDA
Nch open drain/cmos
port select signal
To DMA0, DMA1
Timer
Selector
IICM=1
I/O
UART2
Transmission
register
delay
IICM=0
D
Noize
Filter
Q
IICM=1
UART2
To DMA0
Arbitration
T
IICM=1
Timer
UART2 transmission/
NACK interrupt
request
IICM=0
IICM=0
Reception register
UART2
IICM=0
UART2 reception/ACK
interrupt request
DMA1 request
IICM=1
Start condition detection
S
Stop condition detection
I/O
D
D Q
T
Data bus
IICM=1
Internal clock
CLK
IICM=1
Noize
Filter
Noize
Filter
ACK
9th pulse
(Port P71 output data latch)
UART2
IICM=1
NACK
Q
T
R
Q
Selector
Bus busy
L-synchronous
output enabling bit
Falling edge
detection
P71/RxD2/SCL
R Q
Bus collision
detection
Bus collision/start, stop
condition detection
interrupt request
IICM=0
External clock
IICM=0
UART2
Port reading
P72/CLK2
UART2 IICM=0
Selector
I/O
Timer
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
Figure 13-12. Functional block diagram for I2C mode
Figure 13-12 shows the functional block diagram for I2C mode. Setting “1” in the I2C mode selection bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock inputoutput terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output,
so the SDA output changes after SCL fully goes to L. An attempt to read Port P71 (SCL) results in getting
the terminal’s level regardless of the content of the port direction register. The initial value of SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision
detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop
condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection
interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL
terminal (P71) staying “H”. The bus busy flag (bit 2 of the special UART2 mode register) is set to “1” by the
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous
I/O (UART) mode
UART2
Special Modeserial
Register
start condition detection, and set to “0” by the stop condition detection. The acknowledgment nondetection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying
“H” at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the
interrupt that occurs when SDA terminal’s level is detected already went to “L” at the 9th transmission
clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA request factor selection bits provides the
means to start up the DMA transfer by the effect of acknowledgment detection.
Bit 1 of the special UART2 mode register (01F716) is used as the arbitration loss detection flag control bit.
Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal
data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2 reception
buffer register (01FF16), and “1” is set in this flag when nonconformity is detected. Use the arbitration loss
detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When
setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost
detecting flag is set to "1" at the falling edge of the 9th transmission clock.
If updated the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after
completing the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the special UART2 mode register is used as SCL- and L-synchronous output enabling bit. Setting
this bit to “1” resets the P71 data register to “0” in synchronization with the SCL terminal level going to “L”.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2
Clock asynchronous
Special Modeserial
Register
I/O (UART) mode
Some other functions added are explained here. Figure 13-13 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The
bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If
this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at
the rising edge of the transfer clock.
Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable
bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus
collision detect interrupt request bit (nonconformity).
Bit 6 of the UART2 special mode register is used as the transmission start condition select bit. Setting this
bit to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK
TxD/RxD
1: Timer A0 overflow
Timer A0
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
CLK
TxD/RxD
Bus collision
detect interrupt
request bit
Transmit
enable bit
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
0: In normal state
CLK
TxD
Enabling transmission
With "1: falling edge of RxD2" selected
CLK
TxD
RxD
Figure 13-13. Other functions controlled by UART2 special mode register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous
I/O (UART)
mode
UART2
Special Modeserial
Register
2
UART2 Special Mode Register 2
The UART2 special mode register 2(address 01F616) is used to further control UART2 in I2C mode.
Figure 13-14 shows the special UART2 mode register.
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Bit
symbol
Address
01F616
When reset
X0000000 2
Bit name
Function
IICM2
I 2C mode selection bit 2
Refer to Table 1.19.10
CSC
Clock-synchronous bit
0 : Disabled
1 : Enabled
SWC
SCL wait output bit
0 : Disabled
1 : Enabled
ASL
SDA output stop bit
0 : Disabled
1 : Enabled
STAC
UART2 initialization bit
0 : Disabled
1 : Enabled
SWC2
SCL wait output bit 2
SDHI
SDA output disable bit
0: UART2 clock
1: 0 output
0: Enabled
1: Disabled (high impedance)
SHTC
Start/stop condition
control bit
Set this bit to "1" in I2C mode
(refer to Table 1.19.11)
Figure 13-14. UART2 special mode register 2
142
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous
I/O (UART)
mode
UART2
Special Modeserial
Register
2
Bit 0 of the UART2 special mode register 2(address 01F616) is used as the I2C mode selection bit 2. Table
13-6 shows the types of control to be changed by I2C mode selection bit 2 when the I2C mode selection bit
is set to "1". Table 13-7 shows the timing characteristics of detecting the start condition and the stop
condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to "1" in I2C mode.
Table 13-6. Functions changed by I2C mode selection bit 2
IICM2 = 0
IICM2 = 1
1 Factor of interrupt number 15
No acknowledgment detection (NACK)
UART2 transmission (the rising edge
of the final bit of the clock)
2 Factor of interrupt number 16
Acknowledgment detection (ACK)
UART2 reception (the falling edge
of the final bit of the clock)
Function
3 DMA1 factor at the time when 1 1 0 1 Acknowledgment detection (ACK)
is assigned to the DMA request
factor selection bits
UART2 reception (the falling edge of
the final bit of the clock)
4 Timing for transferring data from the
UART2 reception shift register to the
reception buffer.
The rising edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
5 Timing for generating a UART2
reception/ACK interrupt request
The rising edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
Table 13-7. Timing characteristics of detecting the start condition and the stop condition
3 to 6 cycles < duration for setting-up (Note2)
3 to 6 cycles < duration for holding (Note2)
Note 1 : When the start/stop condition count bit is "1" .
Note 2 : "cycles" is in terms of the input oscillation frequency f(XIN) of the main clock.
Duration for
setting up
Duration for
holding
SCL
SDA
(Start condition)
SDA
(Stop condition)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous
I/O (UART)
mode
UART2
Special Modeserial
Register
2
Nch open drain/cmos
port select signal
P70/TxD2/SDA
Timer
Selector
To DMA0, DMA1
IICM=0
or
IICM2=1
I/0
UART2
IICM=1
delay
Transmission register
UART2
IICM=0
SDHI
ALS
D
IICM=1
and IICM2=0
To DMA0
Arbitration
Q
T
Noize
Filter
UART2 transmission/
NACK interrupt
request
IICM=0
or IICM2=1
IICM=1
Reception register
IICM=0
UART2
IICM=1
and IICM2=0
Start condition detection
S
R
UART2 reception/ACK interrupt request
DMA1 request
Bus
busy
Q
Stop condition detection
P71/RXD2/SCL
D
L-synchronous
output enabling bit
Falling edge
detection
D
I/0
R
ACK
9th pulse
Selector
UART2
IICM=1
IICM=1
Noize
Filter
Q
T
Data register
Noize
Filter
NACK
Q
T
IICM=1
Internal clock
SWC2
External clock
IICM=0
CLK
control
Bus collision
detection
Bus collision/start, stop condition detection
interrupt request
IICM=0
UART2
Falling of 9th pulse
R
S
SWC
Port reading
UART2
IICM=0
P72/CLK2
Selector
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
I/0
Timer
Figure 13-15. Functional block diagram for I2C mode
Functions available in I2C mode are shown in Figure 13-15 — a functional block diagram.
Bit 3 of the UART2 special mode register 2 (address 01F616)is used as the SDA output stop bit. Setting
this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the
instant when the arbitration loss detecting flag is set to "1".
Bit 1 of the UART2 special mode register 2 (address 01F616) is used as the clock synchronization bit. With
this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the falling
edge is found in the SCL pin; and the baus rate generator reloads the set value, and start counting within
the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops counting
the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this function,
the UART2 transmission-reception clock becomes the logical product of the signal flowing through the
internal SCL and that flowing through the SCL pin. This function operates over the period from the moment
earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use
this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (01F616) is used as the SCL wait output bit. Setting this bit to
"1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to
"0" frees the output fixed to "L".
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous
I/O (UART)
mode
UART2
Special Modeserial
Register
2
Bit 4 of the UART2 special mode register 2(address 01F616) is used as the UART2 initialization bit. Setting
this bit to "1", and when the start condition is detected, the microcomputer operates as follows:
(1) The transmission shift register is initialized, and the content of the transmission register is transferred
to the transmission shift register. This starts transmission by dealing with the clock entered next as
the first bit. The UART2 output value, however, does not change until the first bit data is output after
the entrance ofr the clock, and remains unchanged from the value at the moment when the
microcomputer detected the start condition.
(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the
clock entered next as the first bit.
(3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of
the clock.
Starting to transmit/receive signals to/from UART2 using this function does not change the value of the
transmission buffer empty flag. To use this function, choose the external clock for the tansfer clocl.
Bit 5 of the UART2 special mode register 2 (01F616) is used as the SCL pin wait output bit 2. Setting this
bit to "1" with the serial I/O specified allows the user to forcibly output an "L" from the SCL pin even if
UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2 clock
is input/output.
Bit 6 of the UART special mode register 2 (01F616) is used as the SDA output enable bit. Setting this bit to
"1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit at
the rising edge of the UART2 transfer clock. There can be instances in which arbitration loss detecting flag
is turned on.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3
S I/O3
S I/O3 is exclusive clock-synchronous serial I/O.
Figure 14-1 shows the S I/O3 block diagram, and Figure 14-2 shows the S I/O3 control register.
Table 14-1 shows the specifications of S I/O3.
Data bus
f2SIO
SM31
SM30
f8SIO
f32SIO
Synchronous
circuit
SM33
SM36
1/(n+1)
1/2
Transfer rate register (8)
SM36
P90/CLK3
S I/O3
interrupt request
S I/O3 counter (3)
SM32
SM33
SM35 LSB
P92/SOUT3
P91/SIN3
MSB
S I/O3 transmission/reception register (8)
8
n: A value set in the S I/O3 transfer rate register (01E316)
Figure 14-1. S I/O3 block diagram
S I/O3 control register (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
S3C
Bit
symbol
SM30
Address
01E216
output,
Description
Bit name
Internal synchronous
clock select bit
b1 b0
SOUT3 high impedance
control bit
0 : SOUT3 output
1 : SOUT3 high impedance
SM31
SM32
When reset
4016
R W
0 0 : Selecting f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Not to be used
S I/O3 port select bit
0 : Input-output port
(Note 2)
1 : SOUT3 output, CLK function
Nothing is assigned.
This bit can neither be set nor read.
When read, the value of this bit is “0”.
SM33
SM35
Transfer direction
select bit
0 : LSB first
1 : MSB first
SM36
Synchronous clock
select bit
0 : External clock
1 : Internal clock
SM37
SOUT3 initial value
set bit
Effective when SM33 = 0
0 : L output
1 : H output
Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the
S I/O3 control register.
Note 2: When set "0" to SM33 and select input - output port, set "1" to SM36
and select internal clock, or input "H" to P90 and P95.
Figure 14-2. S I/O3 control register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3
Table 14-1. Specifications of S I/O3
Item
Transfer data format
Transfer clock
Conditions for
transmission/
reception start
Interrupt request
generation timing
Select function
Specifications
• Transfer data length: 8 bits
• With the internal clock selected (bit 6 of 01E216 = “1”): f2SIO/2(n+1),
f8SIO/2(n+1), f32SIO/2(n+1) (Note 1)
• With the external clock selected (bit 6 of 01E216): Input from the CLK3 terminal (Note 2)
• To start transmit/reception, the following requirements must be met:
- Select the synchronous clock (use bit 6 of 01E216).
Select a frequency dividing ratio if the internal clock has been selected (use bits
0 and 1 of 01E216).
- SOUT3 initial value set bit (use bit 7 of 01E216)= 1.
- S I/O3 port select bit (bit 3 of 01E216) = 1.
- Select the transfer direction (use bit 5 of 01E216)
• To use S I/O3 interrupts, the following requirements must be met:
- S I/O3 interrupt request bit (bit 3 of 004916) = 0.
• An interrupt occurs after counting eight transfer clock either in transmitting or
receiving data. (Note 3)
- In transmitting: At the time data transfer from the S I/O3 transmission/reception register finishes.
- In receiving: At the time data reception to the S I/O3 transmission/reception register finishes.
• LSB first or MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected.
Note 1: n is a value from 0016 through FF16 set in the S I/O3 transfer rate register.
Note 2: With the external clock selected:
• To write to the S I/O3 transmission/reception register (01E216), enter the “H” level to the CLK3
terminal. Also, to write to the bit 7 (SOUT3 initial value set bit) of SI/O3 control register (01E216),
enter the “H” level to the CLK3 terminal.
• The S I/O3 circuit keeps on with the shift operation as long as the synchronous clock is entered in it,
so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected,
automatically stops.
Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the “H” state.
SI/O3 bit rate generator
b7
Symbol
S3BRG
b0
Address
01E316
When reset
Indeterminate
Values that can be set
Indeterminate
Assuming that set value = n, BRG3 divides the count
source by n + 1
R W
0016 to FF16
SI/O3 transmit/receive register
b7
Symbol
S3TRR
b0
Address
01E016
When reset
Indeterminate
Indeterminate
Transmission/reception starts by writing data to this register.
After transmission/reception finishes, reception data is input.
Figure 14-3. SI/O3 related register
147
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3
Functions for setting an SOUT3 initial value
In carrying out transmission, the output level of the SOUT3 terminal as it is before transmitting 1-bit
data can be set either to “H” or to “L”. Figure 14-4 shows the timing chart for setting an SOUT3 initial
value and how to set it.
(Example) With “H” selected for SOUT3
S I/O3 port select bit SM33 = 0
Signal written to the S I/O3
transmission/reception
register
SOUT3 initial value select bit
SM37 = 1
(SOUT3: Internal -> “H” level)
SOUT3's initial value
setting bit (SM37)
S I/O3 port select bit
SM33 = 0 ->1
(Port select: Normal port -> SOUT3)
S I/O3 port select bit
(SM33)
D0
SOUT3 terminal = “H” output
SOUT3 (internal)
Signal written to the S I/O3 register
=“L” -> “H” -> “L”
(Falling edge)
D0
Port output
SOUT3 terminal output
Initial value = “H” (Note)
Setting the SOUT3
initial value to H
Port selection
(normal port -> SOUT3)
SOUT3 terminal = Outputting
stored data in the S I/O3
transmission/reception register
Note: The set value is output only when the external clock has been selected.
If the internal clock has been selected or if SOUT high impedance has been set,
this output goes to the high-impedance state.
Figure 14-4. Timing chart for setting SOUT3’s initial value and how to set it
S I/O3 operation timing
Figure 14-5 shows the S I/O3 operation timing
Transfer clock
(Note 1)
Signal written to the
S I/O3 register
(Note 2)
S I/O3 output SOUT3
D0
D1
D2
D3
D4
D5
D6
D7
S I/O3 input SIN3
Setting the S I/O3 interrupt request bit
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using
bits 0 and 1 of the S I/O3 control register. (2-division frequency, 8-division frequency, 32-division frequency)
Note 2: With the internal clock selected for the transfer clock, the SOUT3 terminal becomes to the high-impedance
state after the transfer finishes.
Figure 14-5. S I/O3 operation timing chart
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a
capacitive coupling amplifier. Pins P00 to P07, P20 to P27, P100 to P107, P95, and P96 function as the analog signal input
pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5
at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input
pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF,
reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716
to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit
precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When
set to 8-bit precision, the 8 bits are stored in the even addresses.
Table 15-1 shows the performance of the A-D converter. Figure 15-1 shows the block diagram of the A-D
converter, and Figures 15-2 and 15-3 show the A-D converter-related registers.
Table 15-1. Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating condition (Note 2) VCC = 5V, fAD2 divided by 1, 2, or 4, fAD2=f(XIN) divided by 1 or 2
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V
• Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN7 input : ±3LSB
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected) : ±7LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and
repeat sweep mode 1
Analog input pins
24 pins (AN0 to AN7, AN00 to AN07 and AN20 to AN27) + 2 pins (ANEX0 and ANEX1)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the φAD frequency to 250kHz min.
With the sample and hold function, set the φAD frequency to 1MHz min.
In either case, the φAD frequency may not exceed 10 MHz.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
CKS1=1
CKS0=1
AD
fAD2
1/2
1/2
CKS0=0
CKS1=0
A-D conversion rate
selection
V REF
VCUT=0
Resistor ladder
AV SS
VCUT=1
Successive conversion register
A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C116, 03C016)
A-D register 0(16)
(03C316, 03C216)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
(03C516, 03C416)
(03C716, 03C616)
(03C916, 03C816)
A-D register 4(16)
(03CB16, 03CA16)
(03CD16, 03CC16)
A-D register 5(16)
A-D register 6(16)
(03CF16, 03CE16)
A-D register 7(16)
Vref
Decoder
VIN
Comparator
Data bus high-order
Data bus low-order
002
AN0
ADGSEL1,0
102
112
AN00 AN20
AN1
AN01
AN21
AN2
AN02
AN22
AN3
AN03
AN23
AN4
AN04
AN24
AN5
AN05
AN25
AN6
AN06
AN26
AN7
AN07
AN27
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
OPA1,OPA0=0,0
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
OPA1, OPA0
OPA1,OPA0=1,1
OPA0=1
ANEX0
OPA1,OPA0=0,1
ANEX1
OPA1=1
Figure 15-1. Block diagram of A-D converter
150
0
0
1
1
0 : Normal operation
1 : ANEX0
0 : ANEX1
1 : External op-amp mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
Function
RW
b2 b1 b0
CH0
Analog input pin select bit
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD2 /4 is selected
1 : fAD2 /2 is selected
CH1
CH2
MD0
MD1
TRG
b4 b3
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A-D control register 1 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
SCAN0
Function
RW
When single sweep and repeat sweep
mode 0 are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
When repeat sweep mode 1 is selected
SCAN1
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
MD2
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD2 /2 or fAD2 /4 is selected
1 : fAD2 is selected
Vref connect bit
0 : Vref not connected
1 : Vref connected
External op-amp
connection mode bit
b7 b6
VCUT
OPA0
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 15-2. A-D converter-related registers (1)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 2 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
Address
When reset
ADCON2
03D416
XXXX0000 2
Bit symbol
SMP
ADGSEL0
Bit name
A-D conversion method
select bit
A-D group select bit
ADGSEL1
Function
RW
0 : Without sample and hold
1 : With sample and hold
b2 b1
0
0
1
1
0
1
0
1
:
:
:
:
Port P10 group select
inhibited
Port P0 group select
Port P2 group select
Always set to “0”
Reserved bit
Nothing is assigned.
These bits can neither be set nor reset. When read, their content is “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
A-D register i
(b15)
b7
ADi(i=0 to 7)
Address
When reset
03C016 to 03CF16 Indeterminate
(b8)
b0 b7
b0
Function
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
These bits can neither be set nor reset. When read, their
content is “0”.
Figure 15-3. A-D converter-related registers (2)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 15-2 shows the specifications of one-shot mode. Figure 15-4 shows the A-D control register in
one-shot mode.
Table 15-2. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
Bit name
Analog input pin select
bit
CH1
CH2
MD0
When reset
00000XXX2
Function
RW
b2 b1 b0
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
(Note 2)
b4 b3
MD1
A-D operation mode
select bit 0
TRG
Trigger select bit
ADST
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 0 : One-shot mode
(Note 2)
0 : Software trigger
1 : ADTRG trigger
0 : fAD2/4 is selected
0 : fAD2/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin
select bit
Invalid in one-shot mode
MD2
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit1
0 : fAD2/2 or fAD2/4 is selected
1 : fAD2 is selected
SCAN0
RW
SCAN1
VCUT
Vref connect bit
OPA0
External op-amp
connection mode bit
1 : Vref connected
OPA1
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 15-4. A-D conversion register in one-shot mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
Table 15-3 shows the specifications of repeat mode. Figure 15-5 shows the A-D control register in repeat
mode.
Table 15-3. Repeat mode specifications
Item
Specification
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
None generated
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
CH1
CH2
b4 b3
MD1
A-D operation mode
select bit 0
TRG
Trigger select bit
ADST
A-D conversion start flag
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
MD0
RW
b2 b1 b0
Analog input pin
select bit
0 1 : Repeat mode
(Note 2)
(Note 2)
0 : fAD2/4 is selected
1 : fAD2/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin
select bit
Invalid in repeat mode
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD2/2 or fAD2/4 is selected
1 : fAD2 is selected
VCUT
Vref connect bit
1 : Vref connected
OPA0
External op-amp
connection mode bit
SCAN0
SCAN1
MD2
BITS
OPA1
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 15-5. A-D conversion register in repeat mode
154
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 15-4 shows the specifications of single sweep mode. Figure 15-6 shows the A-D control
register in single sweep mode.
Table 15-4. Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Start condition
Writing “1” to A-D converter start flag
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Analog input pin
select bit
Function
RW
Invalid in single sweep mode
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 0 : Single sweep mode
MD1
TRG
ADST
CKS0
Trigger select bit
A-D conversion start flag
Frequency select bit 0
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD2 /4 is selected
1 : fAD2 /2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
Function
R W
When single sweep and repeat sweep mode 0
are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
MD2
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
BITS
8/10-bit mode select bit
CKS1
Frequency select bit 1
0 : 8-bit mode
1 : 10-bit mode
0 : fAD2 /2 or fAD2 /4 is selected
1 : fAD2 is selected
VCUT
Vref connect bit
OPA0
External op-amp
connection mode
bit (Note 2)
1 : Vref connected
OPA1
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit
Figure 15-6. A-D conversion register in single sweep mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 15-5 shows the specifications of repeat sweep mode 0. Figure 15-7 shows the AD control register in repeat sweep mode 0.
Table 15-5. Repeat sweep mode 0 specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
Analog input pin
select bit
RW
Invalid in repeat sweep mode 0
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 1 : Repeat sweep mode 0
MD1
TRG
ADST
CKS0
Trigger select bit
A-D conversion start flag
Frequency select bit 0
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD2 /4 is selected
1 : fAD2 /2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin select bit
RW
When single sweep and repeat sweep mode 0
are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : fAD2 /2 or fAD2 /4 is selected
1 : fAD2 is selected
VCUT
Vref connect bit
1 : Vref connected
OPA0
External op-amp
connection mode
bit (Note 2)
b7 b6
MD2
BITS
CKS1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither “01” nor “10” can be selected with the external op-amp connection mode bit.
Figure 15-7. A-D conversion register in repeat sweep mode 0
156
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using
the A-D sweep pin select bit. Table 15-6 shows the specifications of repeat sweep mode 1. Figure 15-8
shows the A-D control register in repeat sweep mode 1.
Table 15-6. Repeat sweep mode 1 specifications
Item
Specification
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
None generated
AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Read A-D register corresponding to selected pin (at any time)
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Analog input pin
select bit
Function
RW
Invalid in repeat sweep mode 1
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 1 : Repeat sweep mode 1
MD1
TRG
ADST
CKS0
Trigger select bit
A-D conversion start flag
Frequency select bit 0
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD2 /4 is selected
1 : fAD2 /2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
1
b1
b0
Symbol
ADCON1
Address
03D716
Bit symbol
Bit name
SCAN0
A-D sweep pin select bit
When reset
0016
Function
R W
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
SCAN1
MD2
A-D operation mode
select bit 1
1 : Repeat sweep mode 1
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD2 /2 or fAD2 /4 is selected
1 : fAD2 is selected
VCUT
Vref connect bit
1 : Vref connected
OPA0
External op-amp
connection mode
bit (Note 2)
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Figure 15-8. A-D conversion register in repeat sweep mode 1
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 f AD cycle is
achieved with 8-bit resolution and 33 f AD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold
is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the
corresponding A-D register. The speed of A-D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 15-9 is an example of how to
connect the pins in external operation amp mode.
Resistor ladder
Successive conversion register
Analog
input
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ANEX0
ANEX1
Comparator
External op-amp
Figure 15-9. Example of external op-amp connection mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of
this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the
target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 16-1 lists the performance of the D-A converter. Figure 16-1 shows the block diagram of the D-A
converter. Figure 16-2 shows the D-A control register.
Table 16-1. Performance of D-A converter
Item
Conversion method
Resolution
Analog output pin
Performance
R-2R method
8 bits
2 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816)
D-A0 output enable bit
P93/DA0
R-2R resistor ladder
D-A register1 (8)
(Address 03DA16)
D-A1 output enable bit
P94/DA1
R-2R resistor ladder
Figure 16-1. Block diagram of D-A converter
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A control register
b7
b6
b5
b4
b3
b2
b1
Symbol
DACON
b0
Address
03DC16
Bit symbol
When reset
0016
Bit name
Function
DA0E
D-A0 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”
D-A register
b7
Symbol
DAi (i = 0,1)
b0
Address
03D816, 03DA16
When reset
Indeterminate
Function
RW
R
W
Output value of D-A conversion
Figure 16-2. D-A control register
D-A0 output enable bit
"0"
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
2R
DA0
"1"
2R
MSB
LSB
D-A0 register0
AVSS
VREF
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16.
Note 2: The same circuit as this is also used for D-A1.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016
so that no current flows in the resistors Rs and 2Rs.
Figure 16-3. D-A converter equivalent circuit
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer
uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed
in two machine cycles.
Figure 17-1 shows the block diagram of the CRC circuit. Figure 17-2 shows the CRC-related registers.
Figure 17-3 shows the calculation example using the CRC calculation circuit.
Data bus high-order bits
Data bus low-order bits
Eight low-order bits
Eight high-order bits
CRC data register (16)
(Addresses 03BD16, 03BC16)
CRC code generating circuit
x16 + x12 + x5 + 1
CRC input register (8)
(Address 03BE16)
Figure 17-1. Block diagram of CRC circuit
CRC data register
(b15)
b7
(b8)
b0 b7
b0
Symbol
CRCD
Address
03BD16, 03BC16
When reset
Indeterminate
Values that
can be set
Function
CRC calculation result output register
RW
000016 to FFFF16
CRC input register
b7
Symbo
CRCIN
b0
Function
Data input register
Address
03BE16
When reset
Indeterminate
Values that
can be set
0016 to FF16
Figure 17-2. CRC-related registers
161
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC
b15
b0
CRC data register
(1) Setting 000016
b7
CRCD
[03BD16, 03BC16]
b0
CRC input register
(2) Setting 0116
CRCIN
[03BE16]
2 cycles
After CRC calculation is complete
b15
b0
CRC data register
118916
CRCD
[03BD16, 03BC16]
Stores CRC code
The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
(X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
LSB
MSB
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001
9
1000 0000 0000
1000 1000 0001
1000 0001
1000 1000
1001
LSB
8
1
0000
0000
0000
0001
0001
0000
1
1000
0000
1000
0000
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
0
1
1000
MSB
1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
CRC input register
(3) Setting 2316
CRCIN
[03BE16]
After CRC calculation is complete
b15
b0
0A4116
CRC data register
CRCD
[03BD16, 03BC16]
Stores CRC code
Figure 17-3. Calculation example using the CRC calculation circuit
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Module 0/1
The CAN module provides the CAN (Controller Area Network) serial-bus data communication interface. This
asynchronous communication protocol is used in distributed systems, such as automotive and industrial
control systems and where high-speed processing and data exchange are required with a very high level of
security. This module supports data transfer rates up to 1 Mbps.
According to the BOSCH 2.0B CAN protocol specification, the CAN module can handle and process both
the standard and extended identifier message formats. For more details, refer to the BOSCH CAN Specification 2.0B, hereinafter referred to as CAN specification.
Data Bus
CAN Configuration
Register
CAN Control
Register
CAN Global Mask
Register
CAN Message
Control
Register 0 -15
CAN ExtID
Register
CAN Local Mask A
Register
CAN Local Mask B
Register
CTX
Message
Mailbox
Slot 0 - 15
Protocol
Controller
CRX
Acceptance Filter
Mailbox 0 - 15
Wake Up
Logic
16 Bit Timer
DLC
CAN Time Stamp
Register
Message Data
Time Stamp
Interrupt
Control
Logic
CAN REC
Register
CAN TEC
Register
Message ID
CAN Status
Register
CAN Slot Status
Register
CAN Int Control
Register
RecSuc Int
TrmSuc Int
CAN Error Int
Data Bus
CAN Wake-Up Int
Figure 18-1. Block diagram of one CAN module
Figure 18-1 shows a block diagram of the M16C CAN module. The main functional blocks in this description are:
Protocol Controller:
Message Mailbox:
Acceptance Filter:
16 bit Timer:
This controller handles the bus arbitration and the CAN serial communication protocol
message transmission and reception services, i.e. bit stuffing, CRC, error status etc.
This memory block consists of several message slots which can be configured to act
either as a transmit- or receive message box. Each slot consists of a relevant identifier, data length code, a data field (8 bytes) and a communication time stamp. This
message slot time stamp value corresponds to the instant of time (event) when the
Protocol Controller indicates a successful CAN message reception.
This block performs the comparison between the identifier of the received message
and the key identifier of all receive slots. For this acceptance filter, users can define
the content of special mask registers to filter a range of identifier for the corresponding message slot.
This 16 bit timer is used for a time stamp function. The timer provides the counter
status which will be stored together with the received message in the message mailbox.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Wake Up Logic:
Interrupt Generation:
The MCU can be set to stop- or wait mode to reduce power consumption. This module
provides the possibility to wake up the MCU from sleep mode via the CAN bus (refer
to section CAN wake up interrupt).
The CAN module signals the CPU different events via 6 interrupts.
Four interrupt channels are used for successful CAN message transmission and reception indication, i.e. 'message receive successful' interrupt (C0RECIC/C1RECIC)
and 'message transmit successful' interrupt (C0TRMIC/ C1TRMIC).
One interrupt signals if the CAN module enters an error operating state (C01ERRIC),
i.e. 'error passive', 'bus off' and if any CAN bus error occurred in the communication
process. The CAN bus error interrupt generation can be individually disabled in the
CAN Control Register.
The wake up case will also be flagged to the CPU by an additional interrupt line
(C01WKPIC).
Interrupts
• 6 Interrupts
CAN0- Successful Transmission Interrupt
CAN0- Successful Reception Interrupt
CAN1- Successful Transmission Interrupt
CAN1- Successful Reception Interrupt
CAN0/1- Error Interrupt
- Error Passive State
- Error BusOff State
- Bus Error (this feature could be disabled separately)
CAN0/1- Wake Up Interrupt
When the CPU detects an Successful Transmission/Reception Interrupt, the CAN Status Register
must be read to determine which Mailbox has issued the interrupt.
Memory Map of the CAN0/1 Special Function Registers
This memory map is valid for both CAN channels (CAN0 and CAN1)
• CAN Mailboxes
- 16 message slots (each mailbox comprises 16 bytes (8 words))
- fixed mailbox-organization
- 'Basic CAN'-feature is composed of two regular CAN slots (#14/15) - This feature is implemented as
an option.
• CAN Mask Registers
- 3 masks for the acceptance filter (refer to section 'Mask Register and Acceptance Filter') (each mask
comprises 6 bytes)
• CAN SFR Registers
- 9 CAN Special Function Registers
Control Register
(16 Bits): controls the CAN module.
Status Register
(16 Bits): displays the status of the CAN module.
Slot Status Register
(16 Bits): for each slot, the current content status is monitored.
Interrupt Control Register (16 Bits): for each slot, the interrupts can be disabled.
Extended ID Register
(16 Bits): distinguishes between ExtendedID and StandardID
mailboxes.
Configuration Register
(16 Bits): configuration of the bus timing
REC Register
(8 Bits) : receive error counter of the CAN module
TEC Register
(8 Bits) : transmit error counter of the CAN module
Time Stamp Register
(16 Bits): time stamp counter
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Memory Map of a Message Object
Content
Address
Byte Order (8 Bits)
Word Order (16 Bits)
006016 + x•16 + 0
StdID [10 to 6]
StdID [5 to 0]
006016 + x•16 + 1
StdID [5 to 0]
StdID [10 to 6]
006016 + x•16 + 2
ExtID [17 to 14]
ExtID [13 to 6]
006016 + x•16 + 3
ExtID [13 to 6]
ExtID [17 to 14]
006016 + x•16 + 4
ExtID [5 to 0]
DLC
006016 + x•16 + 5
DLC
ExtID [5 to 0]
006016 + x•16 + 6
Data Byte 0
Data Byte 1
006016 + x•16 + 7
Data Byte 1
Data Byte 0
...
...
...
006016 + x•16 + 13
Data Byte 7
Data Byte 6
006016 + x•16 + 14
Time Stamp Upper Byte
Time Stamp Lower Byte
006016 + x•16 + 15
Time Stamp Lower Byte
Time Stamp Upper Byte
Note: x: Number of message slot (x = 0 to 15)
Table 18-1. Message object overview (CAN0)
Content
Address
Byte Order (8 Bits)
Word Order (16 Bits)
026016 + x•16 + 0
StdID [10 to 6]
StdID [5 to 0]
026016 + x•16 + 1
StdID [5 to 0]
StdID [10 to 6]
026016 + x•16 + 2
ExtID [17 to 14]
ExtID [13 to 6]
026016 + x•16 + 3
ExtID [13 to 6]
ExtID [17 to 14]
026016 + x•16 + 4
ExtID [5 to 0]
DLC
026016 + x•16 + 5
DLC
ExtID [5 to 0]
026016 + x•16 + 6
Data Byte 0
Data Byte 1
026016 + x•16 + 7
Data Byte 1
Data Byte 0
...
...
...
026016 + x•16 + 13
Data Byte 7
Data Byte 6
026016 + x•16 + 14
Time Stamp Upper Byte
Time Stamp Lower Byte
026016 + x•16 + 15
Time Stamp Lower Byte
Time Stamp Upper Byte
Note: x: Number of message slot (x = 0 to 15)
Table 18-2. Message object overview (CAN1)
To access the message memory, either linear address order (byte access) or crossed address order (word
access), which supports word access especially for even addresses, can be selected. The location of the
message object bytes depends on the Message Order control bit (MsgOrder), which selects byte- or word
address order. Refer also to section 'CAN Control Register'.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Message Objects
Data can be written in the grey shaded bits in the identifier bytes. But in the case of read-process, the value of these
bits will be set to "0" if a successful receive process is performed for the corresponding slot. In case of no message
storage by the CAN module, these bits contain their previous values (written by the CPU).
Please note the meaning of byte order in the message object. This order corresponds directly with the data
field on the bus in chronological order (see Figures. 18-2/18-3 CAN data frames).
Bit 7
SID5
EID13
EID12
SID10
SID9
SID8
SID7
Bit 0
SID6
StdID [10 to 6]
SID4
SID3
SID2
SID1
SID0
StdID [5 to 0]
EID17
EID16
EID15
EID14
ExtID [17 to 14]
EID11
EID10
EID9
EID8
EID7
EID6
ExtID [13 to 6]
EID5
EID4
EID3
EID2
EID1
EID0
ExtID [5 to 0]
DLC 3
DLC 2
DLC1
DLC0
DLC
Data Byte 0
Data Byte 1
...
Data Byte 7
Time Stamp [15 to 8]
Time Stamp Upper Byte
Time Stamp [7 to 0]
Time Stamp Lower Byte
CAN Data Frame:
StdID[10 to 6] StdID[5 to 0] ExtID[17 to 14] ExtID[13 to 6] ExtID[5 to 0] DLC[3 to 0] Data 0[7 to 0] Data 1[7 to 0]
Data 7[7 to 0]
Figure 18-2. Bit organization of the message objects for byte access
Bit 15
Bit 8 Bit 7
SID10 SID9 SID8 SID7 SID6
Bit 0
SID5 SID4 SID3 SID 2 SID1 SID 0
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID 8 EID7 EID 6
EID5 EID4 EID3 EID2 EID1 EID0
DLC3 DLC2 DLC1 DLC0
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Time Stamp [15 to 8]
Time Stamp [7 to 0]
CAN Data Frame:
StdID[10 to 6] StdID[5 to 0] ExtID[17 to 14] ExtID[13 to 6] ExtID[5 to 0] DLC[3 to 0] Data 0[7 to 0] Data 1[7 to 0]
Figure 18-3. Bit organization of the message objects for word access
166
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Configuration Register
A programmable clock prescaler is used to derive the CAN module basic clock from the clock frequency
f(CAN0/1)/2. Bit 0 to bit 3 of the CAN configuration register represent the prescaler, allowing a division ratio
of 1 to 1/16 to be selected. So the CAN module basic clock frequency fCANB can be calculated as follows:
f (CAN0/1)
f CANB = 2----------------------------------------x (BRP + 1)
where BRP is the value of the prescaler (selectable from 0 to 15). The effective baud rate of the CAN bus
communication depends on the CAN bus timing control parameters and will be explained below.
fCAN0
1/2
1/BRP0
fCANB0
fCAN1
1/2
1/BRP1
fCANB1
Figure 18-4. Generation of CAN basic clock frequency
CAN bus timing control
Each bit-time consists of four different segments:
Bit-time
SS
PR
PH1
Synchronization segment (SS),
Propagation time segment (PR),
Phase buffer segment 1 (PH1) and
Phase buffer segment 2 (PH2).
PH2
Sample point
Figure 18-5. Bit timing
The first segment (SS) is fixed to one Time Quantum, the segments PR, PH1 and PH2 can be programmed
from 1 to 8 Time Quanta by the CAN configuration register. The whole bit-time has to consist of minimum 8
and maximum 25 Time Quanta. The duration of one Time Quantum is the cycle time of fCANB.
f (CAN0/1)
Baudrate = ------------------------------------------------------------------------2 x (BRP + 1) x Num(quanta)
For example: assuming f(XIN)=16MHz and BRP=0, one Time Quantum will be 125ns long. This allows a
maximum transmission rate of 1Mbps (assuming 8 Time Quanta per bit-time).
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Configuration Registers
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0CONR
C1CONR
Bit symbol
BRP
Address
021A16
023A16
When reset
Indeterminate
Indeterminate
Bit name
Prescaler Divider
Function
Prescaler division ratio selection
R
W
O
O
O
O
O
O
b3 b2 b1 b0
0 0 0 0:1
0 0 0 1 : 1/2
0 0 1 0 : 1/3
...
1 1 1 1 : 1/16
SAM
Sampling Control
Bit
PR
Propagation Time
0:
1:
One sample per bit
Three samples per bit
Duration Control Bits
b7 b6 b5
0 0
0 0
...
1 1
1 1
(b15)
b7
b6
b5
b4
b3
b2
b1
(b8)
b0
Symbol
C0CONR
C1CONR
Bit symbol
PH1
Address
021B16
023B16
0 : One Time Quantum
1 : Two Time Quanta
0 : Seven Time Quanta
1 : Eight Time Quanta
When reset
Indeterminate
Indeterminate
Bit name
Phase Buffer
Segment 1
Function
Duration Control Bits
R
W
O
O
O
O
O
O
b2 b1b0
0 0 0 : One Time Quantum
0 0 1 : Two Time Quanta
...
1 1 0 : Seven Time Quanta
1 1 1 : Eight Time Quanta
PH2
Phase Buffer
Segment 2
Duration Control Bits
b5 b4 b3
0 0 0 : One Time Quantum
0 0 1 : Two Time Quanta
...
1 1 0 : Seven Time Quanta
1 1 1 : Eight Time Q uanta
SJW
Synchronization
Jump Width
Control Bits
b7 b6
0
0
1
1
0 : One Time Quantum
1 : Two Time Quanta
0 : Three Time Quanta
1 : Four Time Quanta
Figure 18-6. Description of CAN configuration register (Settings for CAN bus timing)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Control Register
CAN Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0CTLR
C1CTLR
Address
021016
023016
Bit symbol
When reset
0116
0116
R
W
Reset
CAN Module Reset
Bit name
0:
1:
Operation Mode
Reset / Initialization Mode
Function
O
O
LoopBack
Loop Back Mode
for CAN Module
0:
1:
O
Normal Operation Mode
Loop Back Mode (read back and store the
transmitted message)
O
MsgOrder
Message Order
0:
The address order is adapted to word access O
(16Bit) for the message objects and also the
mask memory.
The address order is byte linear(8Bit access).
O
BasicCAN
Basic CAN Feature
O
0: Normal Operation Mode:
Slot #14/15 receive messages according to
the ’first fit’ system.
1: The CAN module switches between the
two active receive-slots #14 and #15 in case
of successive messages fitting into both slots.
O
BusErrEn
Bus Error Enable
0:
1:
O
Bus-errors will not be visible for ICU/CPU.
Bus-errors will be flagged for the ICU via the
CAN Error Interrupt signal.
O
Sleep
Local Sleep Mode
for CAN Module
0:
1:
Operation Mode
Clock of the CAN module will be stopped.
O
O
PortEn
CAN Port Enable
0:
1:
Port serves as I/O port.
Port serves as CAN terminal (CRX/CTX).
O
O
-
-
R
W
O
O
1:
(b15)
b7
b6
b5
b4
b3
b2
b1
(b8)
b0
Nothing is assigned. It is not allowed to write ’1’ to this bit location.
When read, its content is indeterminate.
Symbol
C0CTLR
C1CTLR
Address
021116
023116
Bit symbol
TSPreScale
Bit1, Bit0
When reset
0016
0016
Bit name
TimeStamp (TS)
Prescaler
Function
Prescaler value for TS counting source
(basic source is the CAN bit-clock.)
b1 b0
0 0: Bit-clock
0 1: (Bit-clock)/2
1 0: (Bit-clock)/4
1 1: (Bit-clock)/8
TSReset
RetBusOff
TimeStamp (TS)
Reset
0: TS counter counts bit cycles (s. the divider O
stages is activated by TSPreScale setting.)
1: Reset (Counter value is cleared to $0000.)
Return from ’Error
BusOff’ State
0:
1:
Normal Operation Mode
O
Reset only for the CAN module to return
from ’Error BusOff’ state
Nothing is assigned. It is not allowed to write ’1’ to these bit locations.
When read, their contents are indeterminate.
-
O
(Note)
O
(Note)
-
*) Note: If the TS Reset/RetBusOff (write ’1’) is activated, the control bit will be cleared automatically
by the CAN module after performing the reset for the TS counter or the return from ’BusOff’ state.
Figure 18-7. Structure of CAN control register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
After leaving the MCU 'Reset'-state, the CAN module starts in 'Reset/Initialization' mode. All module setup
parameters should be written in the relevant registers to enable the CAN module to take part in the CAN bus
communication with the correct transfer rate , bit timing etc. (CAN Configuration Register). After finishing the
initialization stage, the 'Reset' bit (CAN Control Register) has to be cleared by the user and the CAN module
will start the bus participation according to the CAN specification.
In order to change the existing setting of the protocol configuration, activate 'Reset/Initialization' mode also
during normal operation. In this case, the CAN module will leave the CAN bus communication in conformity
with the protocol. This means, a just started transmit process has to be finished before entering the 'reset'
state.
In case the protocol engine enters the 'Error BusOff' state, the system can be restarted in 'Error Active'
mode by setting the 'RetBusOff' bit in the CAN Control Register. This 'reset' for the 'protocol controller' has
no effect on the CAN-Interface configuration. The entire slot-configuration, slot contents and all SFR settings will be kept without changes.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Basic CAN Feature
Some applications for the CAN network operate with more than 16 message types (identifiers), so an original
CAN approach (one slot corresponds to one message type) is not a feasible way for these systems. The
first approach to give system support for these applications is the sophisticated mask concept implemented
in this CAN module (refer to section 'Mask Register and Acceptance Filter').
In case there is the requirement to receive most or all messages from the CAN bus (performing further
acceptance filter by software), the CAN module provides a special slot configuration to support this kind of
system solution. In the normal operation mode, the received message is stored in the first fitting message
slot. The slots under consideration for this decision will be determined in the acceptance filter phase. In this
case many messages will be received by one slot, the CPU is heavily loaded to serve this slot without
loosing a message because of 'overwriting' (receiving the next fitting message).
By activating the 'Basic CAN' feature, the slot scheduling in 'receive' case changes for slot #14 and #15.
Received messages are stored alternately in these two message boxes.
SLOT 14
SLOT 15
Empty
Locked (empty)
Msg n
Msg n
Locked (empty)
Msg n+1
Locked (Msg n)
Msg n+2
(lost Msg n)
Msg n + 1
Locked (Msg n+1)
etc.
Msg n+2
Figure 18-8. Receive slot scheduling for implementing the 'Basic CAN' feature
The CAN module uses two different slot addresses to build the Basic CAN feature (no shadow buffer
concept). The 'lock/unlock' function will be controlled exclusively by the CAN module without any influence
of the CPU. There is no 'message protection mechanism' implemented, so the message n+2 will overwrite
the content of message n (Figure 18-7).
The following restrictions have to be kept in case of using the 'Basic CAN' feature:
- The module configuration ('Basic CAN' ON/OFF) should be selected before leaving the 'Reset/Initialization' state. The CAN module will store the first fitting message into slot #14 (in case the filtering failed for all
preceding slots). In case the 'Basic CAN' feature will be enabled or disabled 'on the fly', the slot where the
first message will be stored is undetermined.
- The CAN module never checks, whether or not the received message will be accepted by slot #15 when
slot #14 is locked (last message is stored in slot #14). Therefore it is recommended to use the same
identifier for the message slots #14 and #15 (building the 'Basic CAN' channel) and the same mask values
for both local masks. Otherwise a received message might be dropped by the CAN module, although slot
#14 could accept this message.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
In the 'Basic CAN' mode, two exceptions regarding the message control register and the general configuration concept exist:
1. CAN Frame Type Tolerance
In the 'normal operation mode', decide if an activated slot should handle 'data' or 'remote' frames. It is not
possible to receive 'data' frames and 'remote' frames in the same slot without a reconfiguration process by
the CPU.
In case of the operation with a 'Basic CAN' channel, this behavior is not tolerable, because both frame types
must be handled without CPU interaction.
Therefore, the 'Basic CAN' feature enables message slots #14 and #15 to receive both types of CAN
frames, 'data'- and 'remote' frames.
2. CAN Frame Type Indication
In the 'normal operation mode', the Extended ID register (C0IDR/C1IDR) dictates the type of frames, i.e.
Extended or Standard, which can be handled by the message box. As described in the upper section for the
'Basic CAN' slots, it is possible to receive both frame types irrespective of the slot configuration. Therefore,
the CAN module provides the frame type information in the corresponding message control register.
Because the 'RemActive' information is not needed for the 'Basic CAN' slot function, the frame type information is mapped to this location (refer to section 'CAN Message Control Register'). The content of this bit
corresponds to the frame type stored last in this slot location .
CAN Extended ID Register
CAN ExtID Register
(b15)
b7 b6
(b8)
b0 b7
b0
Symbol
C0IDR
C1IDR
Address
021916, 021816
023916, 023816
Function
When reset
000016
000016
Values that can be set for each bit
ExtID Bits
0: Mailbox handles standard
identifiers.
Each bit corresponds with the appropriate message
mailbox.
1: Mailbox handles extended
identifiers.
ID-format assignment for each message mailbox
Note: These bits can not be set in Reset/Initialization Mode.
Figure 18-9. Structure of CAN extended ID register
172
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Message Control Register
CAN Message Control Register i
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0MCTLi
C1MCTLi
(i = 0 to 15)
Bit symbol
NewData
Address
020016 to 020F 16
022016 to 022F16
Bit name
Function
New Data
0:
1:
SentData
Sent Data
0:
1:
InvalData
Invalid Data
0:
1:
TrmActive
Transmission
Active
0:
1:
MsgLost
Message Lost
0:
1:
RemActive
Remote Active
0:
1:
RspLock
Response
Locked
0:
1:
Remote
Remote Mailbox
RecReq
TrmReq
Note:
Receive Mailbox
Transmit Mailbox
When reset
0016
0016
0:
1:
0:
1:
0:
1:
R
O
- Receive Mailbox
The content of the message slot is read or
still under processing by the CPU.
The CAN module has stored new data in the
corresponding mailbox.
W
O
(Note)
- Transmit Mailbox
Transmission is not started/finished yet.
Frame is transmitted successfully.
O
- Receive Mailbox
The content of the message slot is valid.
Message slot contains invalid data (update of
the message content is in progress).
O
(Note)
- Transmit Mailbox
Slot is waiting for bus free and passing internal
transmit arbitration.
Transmit process for this message is active.
- Receive Mailbox
No message was overwritten in this slot.
This mailbox already contained a message,
but it was overwritten by a newer one.
O
The module handles data frames; transmit/ O
receive case depends on the slot configuration
(BasicCAN mode: data frame is stored).
Remote part of the auto-switch modes (Transmit Remote Frame / Receive Remote Frame) is
active (BasicCAN mode: remote frame is stored).
- Transmission Remote Mailbox
After a remote frame is received, it will be
answered automatically.
After a remote frame is received, no transmission will be started as long as this bit is set to 1.
O
(Note)
O
(Note)
O
O
O
O
O
O
O
O
Mailbox is Remote Mailbox
(s. also table 18-3)
Mailbox is Receive Mailbox
(s. also table 18-3)
Mailbox is Transmission Mailbox
(s. also table 18-3)
The write access on CPU side is limited to ’write only 0’. If the CPU tries to set these bits to 1, it
will not have any influence to the content of these bits. In this case, the values of these bits are
forced to their ’status meaning’ defined by the current state of the CAN module.
Figure 18-10. Structure of CAN message control register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Reception- and Transmission Modes
TrmReq
RecReq
Remote
RspLock
Description
0
0
-
-
Configuration Mode
CPU could configure new transfer mode for this mailbox.
0
1
0
-
Mailbox is configured as a Receivebox for Dataframes.
1. Step: Mailbox transmits Remoteframe (RemAct-Bit is 1)
2. Step: Mailbox becomes a Receivebox for Dataframes
- RemActive-Bit is set to 0.
Exception: When the matching dataframe is already detected on the busline
before the remoteframe can be sent, the mailbox becomes immediately a
Receivebox for Dataframes.
1
0
1
0
1
0
0
0
0
1
1
1/0
Mailbox is configured as a Transmissionbox for Dataframes.
1. Step: Mailbox receives a Remoteframe (RemAct-Bit is 1).
2. Step: Mailbox becomes a Transmissionbox for Dataframes
- RemActive-Bit will be set to 0.
Remark: As long as RspLock=1, no transmission can be started. This means
that Remoteframes are not answered automatically.
Table 18-3. Table of all reception- and transmission modes
Notes - Reception Mode
• A received message, which fulfills the comparison conditions of several mailboxes, will be stored in the first
suitable mailbox starting with the Message Mailbox Slot0 (special case for the 'Basic CAN' feature). This
means the message will be stored only one time.
• When the CAN module transmits a message, the CAN module receives its own message. However,
the CAN module does not store that message in the normal operation mode, even if there is a receive box
with a fitting identifier. In case the CAN module operates in the 'loop back' mode (CAN Control Register),
the transmitted message is stored in a prepared mailbox (receivebox with corresponding identifier).
Notes - Transmission Mode
• Overwrite Procedure of an activated Transmission Mailbox
- In order to activate a transmission mailbox, set the configuration bits according to table 18-3.
- In order to overwrite the content of a transmission mailbox, deactivate the transmission mailbox. This
means, the CPU must clear the TrmReq-Bit (together with the RecReq-Bit!).
- The CPU has to read the TrmActive-Bit to check its current status. When the TrmActive-Bit is '0', the
abort request is successful and the CPU can overwrite the data of the transmission mailbox.
- After this check, the CPU has the possibility to determine whether the message is transmitted or not. The
abort request by CPU side is executed (successful), in case the SentData-Bit is not set. Otherwise the
message is transmitted successfully in spite of the abort request.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Slot Interrupt Control Register
CAN Slot Interrupt Control Register
(b15)
b7 b6
(b8)
b0 b7
b0
Symbol
C0SICR
C1SICR
Address
021716, 021616
023716, 023616
Function
When reset
000016
000016
Values that can be set for each bit
R
W
0: After a successful transmission O
Interrupt Enable Bits
or reception operation no
Each bit corresponds with the appropriate message
interrupt request bit is set.
mailbox.
1: After a successful transmission
The transfer interrupts (’Successful Reception’ /
or reception operation the
’Successful Transmission’) for each message
interrupt request bit in the corremailbox can be enabled and disabled.
sponding MCU interrupt
control register is set.
O
Note: These bits can not be set in Reset/Initialization Mode.
Figure 18-11. Structure of CAN slot interrupt control register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Mask Register and Acceptance Filter
For the acceptance filter, three 29-Bit mask registers are provided. One global mask is assigned to the
mailboxes 0 to 13 and two local masks belong to mailbox 14 and 15 respectively. If the mailbox is configured
as a receive slot, the Standard ID and the Extended ID of the message object act as the local ID mask.
Global Mask
Mailbox #0
Mailbox #1
Mailbox #2
Mailbox #3
Mailbox #4
Mailbox #5
Mailbox #6
Mailbox #7
Mailbox #8
Mailbox #9
Mailbox #10
Mailbox #11
Mailbox #12
Mailbox #13
Local Mask A
Local Mask B
Mailbox #14
Mailbox #15
Figure 18-12. Mask assignment
The mask registers provide the possibility to filter a range of identifier. They can mask the identifier by
setting each bit to '0'. The acceptance filter can be performed either for 29 or for 11 bit identifier length,
determined by the Extended ID register setting for the corresponding mailbox. The mailbox itself contains
the identifier for the filtering process. Together with the relevant mask, the filtering is performed as shown in
the figure below.
Received
Identifier
Identifier
stored in the
Mailbox
Mask Bit Values
0:The corresponding incoming ID bit
is do not care .
1: The corresponding ID bit is
checked against the incoming ID
bit.
Mask
Register
Acceptance
Signal
Acceptance Signal Values
0:The CAN module ignores the
current incoming message.
1:The CAN module stores the
incoming message; the relevant bits
(determined by the mask) of received
ID and mailbox ID are equal.
Figure 18-13. Structure of acceptance filter
Figure 18-13 and 18-14 show the memory location of these three filter masks and their bitmap. The structure of
the bit organization is adapted to the identifier format in every message slot (refer to Figure 18-2/18-3).
After MCU reset condition, the content of the mask registers is undefined.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Addresses
CAN0 CAN1
Bit 7
SID5
EID13
EID12
EID12
EID12
SID8
SID7
Bit 0
SID6
016016
036016
SID4
SID3
SID2
SID1
SID0
016116
036116
EID17
EID16
EID15
EID14
016216
036216
EID10
EID9
EID8
EID7
EID6
016316
036316
EID5
EID4
EID3
EID2
EID1
EID0
016416
036416
SID10
SID9
SID8
SID7
SID6
016616
036616
SID4
SID3
SID2
SID1
SID0
016716
036716
EID17
EID16
EID15
EID14
016816
036816
EID11
EID10
EID9
EID8
EID7
EID6
016916
036916
EID5
EID4
EID3
EID2
EID1
EID0
016A16
036A16
SID10
SID9
SID8
SID7
SID6
016C16
036C16
SID4
SID3
SID2
SID1
SID0
016D16
036D16
EID17
EID16
EID15
EID14
016E16
036E16
SID5
EID13
SID9
EID11
SID5
EID13
SID10
EID11
EID10
EID9
EID8
EID7
EID6
016F16
036F16
EID5
EID4
EID3
EID2
EID1
EID0
017016
037016
Global
Mask
Local
Mask A
Local
Mask B
Figure 18-14. Acceptance filter masks (byte address order)
n+1
Bit 15
Global Mask
n
Bit 8 Bit 7
SID 10 SID9 SID8 SID7 SID6
Addresses
CAN0 / CAN1
Bit 0
SID5 SID4 SID3 SID2 SID1 SID0
016016/036016
EID17 EID 16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
016216/036216
EID5 EID4 EID3 EID2 EID1 EID0
Local Mask A
SID 10 SID9 SID8 SID7 SID6
016416/036416
SID5 SID4 SID3 SID2 SID1 SID0
016616/036616
EID17 EID 16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
016816/036816
EID5 EID4 EID3 EID2 EID1 EID0
Local Mask B
SID 10 SID9 SID8 SID7 SID6
016A16/036A16
SID5 SID4 SID3 SID2 SID1 SID0
016C16/036C16
EID17 EID 16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
016E16/036E16
EID5 EID4 EID3 EID2 EID1 EID0
Figure 18-15. Acceptance filter masks (word address order)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Status Register
CAN Status Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0STR
C1STR
Address
021216
023216
Bit symbol
MBox
Bit3..Bit0
When reset
0016
0016
Bit name
Mailbox Number
Function
Number of the mailbox which transmitted/
received a message successfully
R
W
O
-
b3 b2 b1 b0
0 0 0 0 : Mailbox 0
0 0 0 1 : Mailbox 1
...
1 1 1 1 : Mailbox 15
(b15)
b7
b6
b5
b4
b3
b2
b1
(b8)
b0
TrmSucc
Transmission
Successful
0:
1:
No [successful] transmission
CAN module transmitted a message
successfully.
O
-
RecSucc
Receive
Successful
0:
1:
No [successful] reception
CAN module received a message
successfully.
O
-
TrmState
Transmitter
0:
1:
CAN module is idle or receiver.
CAN module is transmitter.
O
-
RecState
Receiver
0:
1:
CAN module is idle or transmitter.
CAN module is receiver.
O
-
Symbol
C0STR
C1STR
Address
021316
023316
Bit symbol
When reset
0116
0116
R
W
Reset
Reset
Acknowledge Bit
Bit name
0:
1:
Operation Mode
Reset
Function
O
-
LoopBack
Loop Back
Acknowledge
0:
1:
Normal Operation Mode
Loop Back Mode
O
-
MsgOrder
Message Order
0:
The address order for the message objects is O
adapted to word access.
The address order is byte linear (8 Bit access
only).
-
1:
BasicCAN
BasicCAN Feature
0:
1:
Normal Operation Mode
BasicCAN feature (slot #14/15)
O
-
BusError
Bus Error
0:
1:
No error occurred.
CAN Bus-Error occurred.
O
-
ErrPass
CAN module is in
Error Passive state
0:
1:
CAN module is not Error Passive and Bus Off. O
CAN module is Error Passive or Bus Off.
-
BusOff
CAN module is in
Error BusOff state
0:
1:
CAN module is not Bus Off.
CAN module is Bus Off.
O
-
-
-
Nothing is assigned. It is not allowed to write ’1’ to this bit location.
When read, their contents are indeterminate.
Figure 18-16. Structure of CAN status register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Slot Status Register
CAN Slot Status Register
(b15)
b7 b6
(b8)
b0 b7
b0
Symbol
C0SSTR
C1SSTR
Address
021516, 021416
023516, 023416
Function
When reset
000016
000016
Values that can be set for each bit
R
Slot Status Bits
0: - Receive Mailbox
O
Each bit corresponds with the appropriate message
Slot contains no unread mesmailbox.
sage.
- Transmit Mailbox
Message is not sent yet
1: - Receive Mailbox
Slot contains unread message.
- Transmit Mailbox
Message was sent successfully.
Figure 18-17. Structure of CAN slot status register
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Time Stamp Register
• The CPU can read out the content of the 16 bit timer responsible for the time stamp function of the CAN
module.
CAN Time Stamp Register
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0TSR
C1TSR
Address
021F16 , 021E16
023F16 , 023E16
Function
Time Stamp (16 Bit)
Counts the CAN bus bit cycles
When reset
0000 16
000016
Values that can be read
R
W
000016 to FFFF16
O
-
Figure 18-18. CAN time stamp register
The basic clock for this timer is the bit clock derived from the CAN bus bit timing. The content of the timer is
increased by one when received or transmitted frame bits. When the CAN bus is idle, the timer is increased
by the nominal bit rate, which is defined in the CAN Configuration Register.
By help of an additional prescaler structure, the basic clock can be divided by the scale factor 1/1, 1/2,
1/4 or 1/8 (refer to the description of the CAN Control Register).
For the 'time stamp' function the content of the counter is captured after the current message on the bus is
declared to be valid. This decision is made in conformity to the definition of a 'successful receive process'
based on the CAN specification. This 'time stamp' is stored in the message buffer which corresponds to the
successful receive process.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN REC- and CAN TEC-Register
• The REC- and TEC-Register can be used for the analysis of the CAN bus transmit and receive error
occurrences.
CAN REC Register
b7
b0
Symbol
C0RECR
C1RECR
Address
021C 16
023C16
When reset
0016
0016
Function
Receive Error Counter
Increment and decrement according to the CAN
specification
Values that can be read
R
W
0016 to FF16
O
-
Values that can be read
R
W
0016 to FF16
O
-
Figure 18-19. Structure of CAN REC register (Receive error counter)
CAN TEC Register
b7
b0
Symbol
C0TECR
C1TECR
Address
021D16
023D16
When reset
0016
0016
Function
Transmit Error Counter
Increment and decrement according to the CAN
specification
Figure 18-20. Structure of CAN TEC register (Transmit error counter)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Acceptance Filter Support Register
• The Acceptance filter Support Register can be used for the implementation of efficient acceptance filter
rooutines.
Acceptance Filter Support Register
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0AFS
C1AFS
Address
024316 , 024216
024516 , 024416
When reset
indeterminate
indeterminate
Function
At write each bit corresponds to an standard identifier bit
of a received message object.
At read a modified form of the standard identifier is
obtained.
Values that can be set
R
W
Standard identifier in
word- or byte order
can be set.
O
O
Figure 18-21. Acceptance Filter Support Register
When writing the first two bytes of a received message object to the Acceptance Filter Support Register, the
bits are modified as illustrated in Figure 18-20. Therefore, when read, the obtained value can be used for an
efficient software acceptance filtering of the most recently written standard identifier. The message order that
the Acceptance Filter Support Register expects is the message order of the according CAN module.
Bit 15
Bit 8 Bit 7
SID 10 SID9 SID8 SID7 SID6
When write
Addresses
CAN0 / CAN1
Bit 0
SID5 SID4 SID3 SID2 SID1 SID0
24216/24416
3/8 Decoder
Bit 15
When read
Bit 8 Bit 7
Bit 0
SID 10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
Figure 18-22. Write/read of Acceptance Filter Support Register (word order)
182
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Programmable I/O Ports
There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P71 and
P91 are Nch open drain ports and have no built-in pull-up resistance. P85 is an input-only port and has no builtin pull-up resistance.
Figures 19-1 and 19-3 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A
converter), they function as outputs regardless of the contents of the direction registers. See the descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 19-4 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 19-5 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A port
register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port
registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 19-6 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
However, in memory expansion mode and microprocessor mode, P0 to P5 operate as the bus and the
pull-up control register setting is invalid.
(4) Port control register
Figure 19-7 shows the port control register.
The bit 0 of port control register is used to read port P1 as follows:
0 : When port P1 is input port, port input level is read.
When port P1 is output port , the contents of port P1 register is read.
1 : The contents of port P1 register is read though port P1 is input/output port.
This register is valid in the following:
• External bus width is 8 bits in microprocessor mode or memory expansion mode.
• Port P1 can be used as a port in multiplexed bus for the entire space.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P00 to P07, P20 to P27,
Data bus
Port latch
Analog input
Pull-up selection
Direction register
P30 to P37, P40 to P47,
P50 to P54, P56
Data bus
Port latch
Pull-up selection
Direction register
P10 to P14
Port P1 control register
Data bus
Port latch
Pull-up selection
Direction register
P15 to P17
Port P1 control register
Data bus
Port latch
Input to respective peripheral functions
Pull-up selection
Direction register
P57, P60, P61, P64, P65,
P72 to P76, P80, P81,
P90, P92
"1"
Output
Data bus
Port latch
Input to respective peripheral functions
Figure 19-1. Programmable I/O ports (1)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
P82 to P84
Direction register
Data bus
Port latch
Input to respective peripheral functions
Pull-up selection
Direction register
P55, P62, P66, P77,
P97
Data bus
Port latch
Input to respective peripheral functions
Pull-up selection
Direction register
P63, P67
"1"
Output
Data bus
Nch
Port latch
Note 1: P63 and P67 can be N-channel open drain only when used as
TXD0/TXD1 pin.
Pull-up selection
Direction register
P70
"1"
Output
Data bus
Nch
Port latch
Input to respective peripheral functions
Note 2: P70 can be N-channel open drain only when used as TXD2 pin. If used as
input port it is only usable as CMOS port.
P85
Data bus
NMI interrupt input
P71, P91
Direction register
"1"
Port latch
Output
(Note 3)
Input to respective peripheral functions
Note 3:
symbolizes a parasitic diode.
Figure 19-2. Programmable I/O ports (2)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
P100 to P103
(inside dotted-line not included)
P104 to P107
(inside dotted-line included)
Direction register
Data bus
Port latch
Analog input
Input to respective peripheral functions
Pull-up selection
D-A output enabled
Direction register
P93, P94
Data bus
Port latch
Input to respective peripheral functions
Analog output
D-A output enabled
Pull-up selection
Direction register
P96
"1"
Port latch
Data bus
Output
Analog input
Pull-up selection
Direction register
P95
"1"
Data bus
Port latch
Output
Input to respective peripheral functions
Analog input
Figure 19-3. Programmable I/O ports (3)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P87
Data bus
Port latch
fc
Rf
Pull-up selection
Rd
Direction register
P86
"1"
Data bus
Port latch
Output
Figure 19-4. Programmable I/O ports (4)
BYTE
BYTE signal input
CNVSS
CNVSS signal input
RESET
RESET signal input
Figure 19-5. I/O pins
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi direction register (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PDi (i = 0 to 10, except 8)
Bit symbol
Address
03E216, 03E316, 03E616, 03E716, 03EA16
03EB16, 03EE16, 03EF16, 03F316, 03F616
Bit name
PDi_0
Port Pi0 direction register
PDi_1
Port Pi1 direction register
PDi_2
Port Pi2 direction register
PDi_3
PDi_4
Port Pi3 direction register
Port Pi4 direction register
PDi_5
Port Pi5 direction register
PDi_6
Port Pi6 direction register
PDi_7
Port Pi7 direction register
Function
RW
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 10 except 8)
Note: Set bit 2 of protect register (address 000A16) to “1” before rewriting to
the port P7 and P9 direction register.
Port P8 direction register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PD8
Bit symbol
Address
03F216
Bit name
PD8_0
Port P80 direction register
PD8_1
Port P81 direction register
PD8_2
Port P82 direction register
PD8_3
Port P83 direction register
PD8_4
Port P84 direction register
When reset
00X000002
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
Nothing is assigned.
This bit can either be set nor reset. When read, its content is indeterminate.
PD8_6
Port P86 direction register
PD8_7
Port P87 direction register
Figure 19-6. Direction register
188
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
When reset
0016
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Pi (i = 0 to 10, except 8)
Bit symbol
Address
03E016, 03E116, 03E416, 03E516, 03E816
03E916, 03EC16, 03ED16, 03F116, 03F416
Bit name
Pi_0
Port Pi0 register
Pi_1
Pi_2
Port Pi1 register
Port Pi2 register
Pi_3
Port Pi3 register
Pi_4
Port Pi4 register
Pi_5
Port Pi5 register
Pi_6
Port Pi6 register
Pi_7
Port Pi7 register
Function
When reset
Indeterminate
Indeterminate
RW
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : L level data
1 : H level data
(i = 0 to 10 except 8)
Port P8 register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P8
Bit symbol
Address
03F016
Bit name
P8_0
Port P80 register
P8_1
Port P81 register
P8_2
Port P82 register
P8_3
Port P83 register
P8_4
Port P84 register
P8_5
Port P85 register
P8_6
Port P86 register
P8_7
Port P87 register
When reset
Indeterminate
Function
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P85)
0 : L level data
1 : H level data
Figure 19-7. Port register
189
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR0
Bit symbol
Address
03FC16
Bit name
PU00
P00 to P03 pull-up
PU01
P04 to P07 pull-up
PU02
P10 to P13 pull-up
PU03
P14 to P17 pull-up
PU04
P20 to P23 pull-up
PU05
P24 to P27 pull-up
PU06
P30 to P33 pull-up
PU07
P34 to P37 pull-up
When reset
0016
Function
RW
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Pull-up control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Bit symbol
Address
03FD16
Bit name
PU10
P40 to P43 pull-up
PU11
P44 to P47 pull-up
PU12
P50 to P53 pull-up
PU13
P54 to P57 pull-up
PU14
P60 to P63 pull-up
PU15
P64 to P67 pull-up
PU16
P70 to P73 pull-up (Note 1)
When reset
0016 (Note 2)
Function
R W
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
PU17
P74 to P77 pull-up
Note 1: Since P70 is N-channel open drain port, pull-up is not available for it.
Note 2: When the VCC level is being impressed to the CNVSS terminal, this register becomes
to 0216 when reset (PU11 becomes to 1 ).
Pull-up control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR2
Bit symbol
Address
03FE16
Bit name
PU20
P80 to P83 pull-up
PU21
P84 to P87 pull-up
(Except P85)
PU22
P90 to P93 pull-up (Note 3)
PU23
PU24
P94 to P97 pull-up
P100 to P103 pull-up
PU25
P104 to P107 pull-up
When reset
0016
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned.
Theses bits can neither be set nor reset. When read, their contents are 0 .
Note 3: Since P91 is N-channel open drain port, pull-up is not available for it.
Figure 19-8. Pull-up control register
190
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
PCR
Bit symbol
PCR0
Address
03FF16
Bit name
Port P1 control register
When reset
0016
Function
0 : When input port, read port
input level. When output port,
read the contents of port P1
register.
1 : Read the contents of port P1
register though input/output
port.
Nothing is assigned.
Theses bits can neither be set nor reset. When read, their contents are 0 .
Figure 19-9. Port control register
191
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Table 19-1. Example connection of unused pins in single-chip mode
Pin name
Connection
Ports P0 to P10
(excluding P85)
After setting for input mode, connect every pin to VSS or VCC via a
resistor; or after setting for output mode, leave these pins open.
XOUT (Note)
Open
NMI
Connect via resistor to VCC (pull-up)
AVCC
Connect to VCC
AVSS, VREF, BYTE
Connect to VSS
Note: With external clock input to XIN pin.
Table 19-2. Example connection of unused pins in memory expansion mode and microprocessor mode
Pull-up
P82
to
Direction
Data
bus
Port
Input
to
respective
register
latch
peripheral
Pull-up
Direction
P55,
P97
P62,
P66,
functions
selection
register
P77,
Data
bus
Input
Port
to
respective
latch
peripheral
Pull-up
P63,
selection
P84
Direction
P67
functions
selection
register
"1"
Output
Data
bus
Port
Note
Nch
latch
and
P67
can
P63
pin.
TXD0/TXD1
1:
Pull-up
Direction
be
N-channel
open
drain
only
when
used
as
selection
register
P70
"1"
Output
Data
bus
Port
Input
to
respective
Note
2:
P70
input
Nch
latch
peripheral
functions
can
be
N-channel
open
port
it
is
only
usable
as
drain
only
when
CMOS
port.
used
as
TXD2
pin.
If
used
as
P85
Data
bus
NMI
P71,
Direction
P91
interrupt
input
register
"1"
Port
Output
latch
(Note
Input
to
respective
Note
3:
peripheral
functions
symbolizes
a
parasitic
diode.
Microcomputer
Microcomputer
Port P0 to P10 (except for P85)
Port P6 to P10 (except for P85)
(Input mode)
·
·
·
(Input mode)
(Output mode)
(Input mode)
·
·
·
(Input mode)
··
·
Open
(Output mode)
Open
NMI
BHE
HLDA
ALE
XOUT
BCLK
NMI
XOUT
VCC
AVCC
··
·
Open
Open
VCC
HOLD
RDY
AVCC
BYTE
AVSS
VREF
AVSS
VREF
VSS
In single-chip mode
In memory expansion mode or
in microprocessor mode
Figure 19-10. Example connection of unused pins
192
VSS
3)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Usage Precaution
Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading the
timer Ai register after setting a value in the timer Ai register with a count halted but before the counter
starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by underflow
or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with
a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the timer Ai interrupt request bit does not becomes “1”.
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request
bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the
reload register. At this time, timer Bi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-D
conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as internal CPU clock.
Stop Mode and Wait Mode
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number
and interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an
interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to
set a value in the stack pointer before accepting an interrupt.
When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning
the first instruction immediately after reset, generating any interrupts including the NMI interrupt is
prohibited.
(3) The NMI interrupt
• As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the VCC pin if unused.
Be sure to work on it.
• Do not get either into stop mode or into wait mode with the NMI pin set to “L”.
External ROM version
The external ROM version is operated only in microprocessor mode, so be sure to perform the following:
• Connect CNVss pin to Vcc.
• Fix the processor mode bit to “112”
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Table 21-1. Absolute maximum ratings
Symbol
Vcc
AVcc
VI
VO
Pd
Topr
Tstg
Parameter
Supply voltage
Analog supply voltage
RESET, CNVSS , BYTE,
Input
P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P80 to P87,
P90 to P97, P100 to P107,
VREF, XIN
P71, P91
Output
P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37,P40 to P47, P50 to P57,
Condition
Rated value
Unit
VCC=AVCC
VCC=AVCC
-0.3 to 6.5
V
-0.3 to 6.5
V
P60 to P67,P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107,
XOUT
P70, P71,
Power dissipation
Ta=25 C
Operating ambient temperature
Storage temperature
Note 1: Specify a product of -40 to 85°C to use it.
195
-0.3 to Vcc+0.3
V
-0.3 to 6.5
V
-0.3 to Vcc+0.3
V
-0.3 to 6.5
V
700
-40 to 85 (Note 1)
-65 to 150
mW
C
C
t
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ve e r
lo
pm
en
Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Table 21-2. Recommended operating conditions (referenced to Vcc = 4.5 V to 5.5V at Ta = -40 to
85 °C (Note 3) unless otherwise specified)
Symbol
Vcc
AVcc
Vss
AVss
Parameter
Min
HIGH input P31 to P37, P40 to P47, P50 to P57, P60 to P67, P70, 0,
P72 to P77, P80 to P87, P90, P92 to P97, P100 to P107,
voltage
XIN, RESET, CNVSS, BYTE
P91 , P71
V
V
V
V
Vcc
V
0.8Vcc
6.5
V
0.8Vcc
Vcc
V
0.5Vcc
Vcc
V
(data input function during memory expansion and microprocessor modes)
0
0.2Vcc
V
0
0.2Vcc
V
0
0.16Vcc
V
LOW input P31 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P90 to P97, P100 to P107,
voltage
XIN, RESET, CNVSS, BYTE
P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode)
P00 to P07, P10 to P17, P20 to P27, P30
VIL
(data input function during memory expansion and microprocessor modes)
I OH (peak)
I OH (avg)
I OL (peak)
I OL (avg)
f (XIN)
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
HIGH peak output
P40 to P47, P50 to P57, P60 to P67,P70,P72 to P77,
current
P80 to P84,P86,P87, P90 ,P92 to P97,P100 to P107
HIGH average output P00 to P07, P10 to P17, P20 to P27,P30 to P37,
current
P40 to P47, P50 to P57, P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97,P100 to P107
P0
0 to P07, P10 to P17, P20 to P27,P30 to P37,
LOW peak output
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
current
P80 to P84,P86,P87,P90 to P97,P100 to P107
P00 to P07, P10 to P17, P20 to P27,P30 to P37,
LOW average
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
output current
P80 to P84,P86,P87,P90 to P97,P100 to P107
Vcc=4.2V to 5.5V
No wait Mask ROM, Flash
Main clock input
Vcc=4.2V to 5.5V
oscillation frequency
Vcc=4.2V to 5.5V
With wait Mask ROM, Flash
Vcc=4.2V to 5.5V
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
0
16
0
20
MHz
MHz
0
16
0
20
50
Subclock oscillation frequency
f (XcIN)
5.0
Vcc
0
0
0.8Vcc
P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode)
P00 to P07, P10 to P17, P20 to P27, P30
Unit
5.5
4.2
Supply voltage
Analog supply voltage
Supply voltage
Analog supply voltage
VIH
Standard
Max.
Typ.
32.768
MHz
MHz
kHz
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1,
P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P8 0 to P84 must be
80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max.
Note 3: Specify a product of -40 to 85°C to use it.
Note 4: Relationship between main clock oscillation frequency and supply voltage.
3.5
0.0
4.5
5.5
16.0
7.33 X VCC - 14.791MHZ
5.0
0.0
2.7
4.2
5.5
16.0
5 X VCC - 6.5MHZ
7.0
0.0
2.7
Main clock input oscillation frequency
(Mask ROM, With wait)
Operating maximum frequency [MHZ]
6.95 X VCC - 15.275MHZ
Main clock input oscillation frequency
(EPROM, One-time PROM, With wait)
Operating maximum frequency [MHZ]
16.0
2.7
Main clock input oscillation frequency
(Mask ROM, No wait)
Operating maximum frequency [MHZ]
Operating maximum frequency [MHZ]
Main clock input oscillation frequency
(EPROM, One-time PROM, No wait)
4.5
5.5
16.0
4 X VCC - 0.8MHZ
10.0
0.0
2.7
4.2
Supply voltage[V]
Supply voltage[V]
Supply voltage[V]
Supply voltage[V]
(BCLK: no division)
(BCLK: no division)
(BCLK: no division)
(BCLK: no division)
5.5
Note 5: Execute case without wait, program/erase of flash memory by Vcc = 4.2V to 5.5V and f(BCLK) ≤ 6.25 MHz. Execute case
with wait, program/erase of flash memory by Vcc = 4.2V to 5.5V and f(BCLK) ≤ 12.5 MHz.
196
t
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ve er
lo
pm
en
Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Table 21-3. Electrical characteristics (referenced to Vcc = AVcc = VREF = 5V, Vss = AVss = 0 V at
Ta = 25 °C, f(XIN) = 16MHz unless otherwise specified)
Parameter
Symbol
Measuring condition
VOH
P00 to P07, P10 to P17, P20 to P27,
HIGH output P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 , P72 to P77 ,
voltage
IOH=-5mA
P80 to P84 , P86, P87, P9 0 ,
P9 2 to P97 , P100 to P107
VOH
P00 to P07, P10 to P17, P20 to P27,
HIGH output P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 , P72 to P77 ,
IOH=-200µA
voltage
P80 to P84 , P86, P87, P9 0 ,
P9 2 to P97 , P100 to P107
VOH
HIGH output
voltage
XOUT
HIGH output
voltage
XCOUT
Standard
Min
Typ. Max.
3.0
V
4.7
V
HIGHPOWER
IOH=-1mA
3.0
LOWPOWER
IOH=-0.5mA
3.0
HIGHPOWER
With no load applied
With no load applied
LOWPOWER
Unit
V
3.0
1.6
V
VOL
LOW output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107
IOL=5mA
2.0
V
VOL
LOW output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107
IOL=200µA
0.45
V
VOL
LOW output
voltage
XOUT
HIGHPOWER
IOL=1mA
2.0
LOWPOWER
IOL=0.5mA
2.0
LOW output
voltage
XCOUT
HIGHPOWER
With no load applied
With no load applied
Hysteresis
VT+ - VT-
LOWPOWER
0
V
0
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB2IN, INT0 to INT5,
ADTRG, CTS0, CTS1, CLK0,
CLK1,TA2OUT to TA4OUT,NMI,
KI0 to KI3
0.2
0.8
V
0.2
1.8
V
µA
VT+ - VT-
Hysteresis
IIH
HIGH input P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
current
P60 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P107,
XIN, RESET, CNVss, BYTE
VI=5V
5.0
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P107,
XIN, RESET, CNVss, BYTE
VI=0V
-5.0
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P80 to P84,
P86, P87, P90 to P97, P100 to P107
VI=0V
LOW input
current
I IL
R PULLUP
Pull-up
resistance
V
RESET
30.0
50.0
167.0
µA
kkΩ
R fXIN
Feedback resistance XIN
1.0
MΩ
M
RfCXIN
Feedback resistance XCIN
6.0
MΩ
M
V
RAM retention voltage
RAM
Icc
Power supply current
When clock is stopped
In single-chip
mode, the
output pins
are open and
other pins are
VSS
f(XIN)=16MHz
Square wave, no division
Mask ROM version
f(XCIN)=32kHz
2.0
V
50.0
80.0
mA
200.0
µA
8.0
mA
4.0
µA
9.0
mA
Square wave
Flash memory 5V version
f(XCIN)=32kHz
Square wave
f(XCIN)=32kHz
Square wave
When a WAIT instruction is
executed
Timer A operates with fc32
Ring oscillation
197
Ta=25˚C
when clock is stopped
1.0
Ta=85˚C
when clock is stopped
20.0
µA
t
U
de nd
ve e r
lo
pm
en
Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Vcc = 5 V
Table 21-4. A-D conversion characteristics (referenced to Vcc = AVcc = VREF = 5V,
Vss = AVss = 0 V at Ta = 25 °C, f(XIN) = 16MHz unless otherwise specified)
Symbol
Parameter
Measuring condition
Resolution
VREF = VCC
Absolute Sample & hold function disabled
accuracy
VREF = VCC = 5V
Sample & hold function enabled10bit)
VREF =VCC
= 5V
Standard
Unit
Min. Typ. Max.
AN0 to AN7 input
AN00 to AN07 input
AN20 to AN27 input
ANEX0, ANEX1 input,
External op-amp connection mode
Sample & hold function enabled8bit)
RLADDER
tCONV
tCONV
tSAMP
VREF
VIA
Ladder resistance
Conversion time (10bit) (Note 1)
Conversion time (8bit) (Note 1)
Sampling time
Reference voltage
Analog input voltage
VREF = VCC = 5V
VREF = VCC
10
Bits
±3
LSB
±3
LSB
±7
LSB
±2
40
LSB
28
0.3
2
VCC
kΩ
cycles
cycles
µs
V
0
VREF
V
10
33
Note 1: The conversion times are given in cycles of fAD. fAD is derived from f(Xin) divided by 1, 2, 4, or 8
and may not exceed 10 MHz. Minimal conversion times are achieved with an f(Xin) of 10 MHz or 20
MHz.
Table 21-5. D-A conversion characteristics (referenced to Vcc = 5 V, VREF = 5V,
Vss = AVss = 0 V at Ta = 25 °C, f(XIN) = 16MHz unless otherwise specified)
Symbol
tsu
RO
IVREF
Parameter
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Measuring condition
Min.
4
(Note)
Standard
Typ. Max.
10
8
1.0
3
20
1.5
Unit
Bits
%
µs
kΩ
mA
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
"0016". The A-D converter's ladder resistance is not included. Also, when the VREF is unconnected at the
A-D control register, IVREF is sent.
198
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ve er
lo
pm
en
Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Vcc = 5 V
Timing requirements (referenced to Vcc = 5 V, Vss = 0 V at Ta = 25 °C unless otherwise specified)
Table 21-6. External clock input
Symbol
tc
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
Unit
ns
62.5
25
25
15
15
ns
ns
ns
ns
Table 21-7. Memory expansion- and microprocessor modes
Symbol
Parameter
tac1(RD-DB)
Data input access time (no wait)
tac2(RD-DB)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK )
tsu(HOLD-BCLK )
th(RD-DB)
th(BCLK -RDY)
th(BCLK-HOLD )
td(BCLK-HLDA )
Note: Calculated according to the BCLK frequency as follows:
tac1(RD – DB) =
10 9
– 45
f(BCLK) X 2
tac2(RD – DB) =
3 X 10
– 45
f(BCLK) X 2
tac3(RD – DB) =
3 X 10
– 45
f(BCLK) X 2
[ns]
9
[ns]
9
[ns]
199
Standard
Min.
Max.
(Note)
(Note)
(Note)
40
Unit
ns
ns
ns
40
ns
ns
ns
0
ns
0
ns
0
ns
30
40
ns
t
U
de nd
ve e r
lo
pm
en
Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Vcc = 5 V
Timing requirements (referenced to Vcc = 5 V, Vss = 0 V at Ta = 25 °C unless otherwise specified)
Table 21-8. Timer A input (counter input in event counter mode)
Symbol
Standard
Max.
Min.
100
40
Parameter
tc(TA)
TAiIN input cycle time
tw(TAH)
TAiIN input HIGH pulse width
tw(TAL)
TAiIN input LOW pulse width
40
Unit
ns
ns
ns
Table 21-9. Timer A input (gating input in timer mode)
Symbol
Standard
Max.
Min.
400
Parameter
tc(TA)
TAiIN input cycle time
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
200
200
Unit
ns
ns
ns
Table 21-10. Timer A input (gating input in timer mode)
Symbol
Standard
Max.
Parameter
Min.
Unit
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
tw(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
100
100
ns
ns
Table 21-11. Timer A input (external trigger input in one-shot timer mode)
Symbol
tw(TAH)
tw(TAL)
Standard
Max.
Min.
100
Parameter
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
100
Unit
ns
ns
Table 21-12. Timer A input (up/down input in event counter mode)
tc(UP)
TAiOUT input cycle time
tw(UPH)
TAiOUT input HIGH pulse width
Standard
Max.
Min.
2000
1000
tw(UPL)
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
1000
400
400
Symbol
tsu(UP-TIN)
th(TIN-UP)
Parameter
200
Unit
ns
ns
ns
ns
ns
t
U
de nd
ve er
lo
pm
en
Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Vcc = 5 V
Timing requirements (referenced to Vcc = 5 V, Vss = 0 V at Ta = 25 °C unless otherwise specified)
Table 21-13. Timer B input (counter input in event counter mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input HIGH pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input LOW pulse width (counted on one edge)
40
200
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
80
ns
ns
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
80
ns
Table 21-14. Timer B input (pulse period measurement mode)
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
200
200
ns
ns
Table 21-15. Timer B input (pulse width measurement mode)
Symbol
tc(TB)
Parameter
Standard
Min.
Max.
Unit
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input HIGH pulse width
200
ns
tw(TBL)
TBiIN input LOW pulse width
200
ns
Table 21-16. A-D trigger input
Symbol
tc(AD)
tw(ADL)
Standard
Parameter
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
Min.
1000
125
Max.
Unit
ns
ns
Table 21-17. Serial I/O
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input HIGH pulse width
100
ns
100
ns
tw(CKL)
CLKi input LOW pulse width
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
tsu(D-C)
RxDi input setup time
RxDi input hold time
th(C-D)
80
ns
0
30
ns
90
ns
ns
Table 21-18. External interrupt INTi inputs
Symbol
Parameter
tw(INH)
INTi input HIGH pulse width
tw(INL)
INTi input LOW pulse width
Standard
Min.
250
250
201
Max.
Unit
ns
ns
t
U
de nd
ve e r
lo
pm
en
Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Vcc = 5 V
Switching characteristics (referenced to Vcc = 5 V, Vss = 0 V at Ta = 25 °C, CM15 ="1"
unless otherwise specified)
Table 21-19. Memory expansion mode and microprocessor mode (no wait)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Measuring condition
Parameter
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)(Note2)
Standard
Min.
Max.
25
4
0
0
25
4
25
Figure 1.26.1
–4
25
0
25
0
40
4
(Note1)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
10 9
– 40
f(BCLK) X 2
[ns]
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
202
R
DBi
C
t
U
de nd
ve er
lo
pm
en
Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Vcc = 5 V
Switching characteristics (referenced to Vcc = 5 V, Vss = 0 V at Ta = -25 °C, CM15 ="1"
unless otherwise specified)
Table 21-20. Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Symbol
Measuring condition
Parameter
Standard
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
4
0
0
td(BCLK-CS)
th(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
4
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
th(BCLK-RD)
td(BCLK-WR)
RD signal output hold time
WR signal output delay time
0
th(BCLK-WR)
td(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
0
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)(Note2)
25
ns
ns
ns
ns
25
25
ns
ns
ns
ns
ns
25
ns
ns
40
ns
ns
25
Figure 1.26.1
Unit
–4
4
(Note1)
ns
ns
ns
0
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
10 9
f(BCLK)
– 40
[ns]
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
203
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Vcc = 5 V
Switching characteristics (referenced to Vcc = 5 V, Vss = 0 V at Ta = -25 °C, CM15 ="1"
unless otherwise specified)
Table 21-21. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Measuring condition
Parameter
Symbol
Standard
Min.
Max.
25
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
th(RD-AD)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
(Note)
ns
ns
th(WR-AD)
Address output hold time (WR standard)
(Note)
ns
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
Chip select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
th(BCLK-DB)
td(DB-WR)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
th(WR-DB)
td(BCLK-ALE)
Data output hold time (WR standard)
ALE signal output delay time (BCLK standard)
th(BCLK-ALE)
td(AD-ALE)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
(Note)
ns
ns
th(ALE-AD)
td(AD-RD)
ALE signal output hold time (Adderss standard)
Post-address RD signal output delay time
50
0
ns
ns
td(AD-WR)
tdZ(RD-AD)
Post-address WR signal output delay time
Address output floating start time
4
25
4
(Note)
(Note)
25
0
25
Figure 1.26.1
0
40
4
th(RD – AD) =
10 9
f(BCLK) X 2
th(WR – AD) =
10
f(BCLK) X 2
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
[ns]
th(WR – CS) =
10
f(BCLK) X 2
td(DB – WR) =
10 X 3
– 40
f(BCLK) X 2
th(WR – DB) =
10
f(BCLK) X 2
[ns]
td(AD – ALE) =
10 9
– 25
f(BCLK) X 2
[ns]
[ns]
9
9
[ns]
9
[ns]
9
204
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note)
Note: Calculated according to the BCLK frequency as follows:
ns
(Note)
25
–4
0
8
ns
ns
ns
ns
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
P0
P1
P2
30pF
P3
P4
P5
P6
P7
P8
P9
P10
Figure 21-1. Port P0 to P10 measurement circuit
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
VCC = 5V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
th(TIN–UP)
(When count on falling
edge is selected)
tsu(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
tw(INL)
INTi input
tw(INH)
Figure 21-2. Vcc = 5V timing diagram
206
th(C–D)
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(Valid only with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Valid with or without wait)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
Hi–Z
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P40 to P43.
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
• Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 21-3. Vcc = 5V timing diagram
207
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Memory Expansion Mode and Microprocessor Mode
(With no wait)
Read timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
4ns.min
25ns.max
CSi
th(RD–CS)
tcyc
0ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
ADi
BHE
ALE
4ns.min
th(RD–AD)
td(BCLK–ALE) th(BCLK–ALE)
0ns.min
–4ns.min
25ns.max
th(BCLK–RD)
td(BCLK–RD)
25ns.max
0ns.min
RD
tac1(RD–DB)
Hi–Z
DB
tSU(DB–RD)
th(RD–DB)
40ns.min
0ns.min
td(BCLK–CS)
th(BCLK–CS)
Write timing
BCLK
4ns.min
25ns.max
CSi
th(WR–CS)
tcyc
0ns.min
td(BCLK–AD)
th(BCLK-AD)
25ns.max
ADi
BHE
4ns.min
td(BCLK–ALE) th(BCLK–ALE)
th(WR–AD) 0ns.min
–4ns.min
ALE
25ns.max
th(BCLK–WR)
td(BCLK–WR)
WR, WRL,
WRH
DB
0ns.min
25ns.max
td(BCLK–DB)
40ns.max
Hi-Z
th(BCLK–DB)
4ns.min
td(DB–WR)
th(WR–DB)
0ns.min
(tcyc/2–40)ns.min
Figure 21-4. Vcc = 5V timing diagram
208
VCC = 5V
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Read timing
BCLK
th(BCLK–CS)
td(BCLK–CS)
4ns.min
25ns.max
CSi
th(RD–CS)
tcyc
0ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
ADi
BHE
4ns.min
td(BCLK–ALE) 25ns.max
th(BCLK–ALE)
th(RD–AD)
0ns.min
–4ns.min
ALE
th(BCLK–RD)
td(BCLK–RD)
0ns.min
25ns.max
RD
tac2(RD–DB)
Hi–Z
DB
tSU(DB–RD)
th(RD–DB)
40ns.min
0ns.min
Write timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
4ns.min
25ns.max
CSi
th(WR–CS)
tcyc
0ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
ADi
BHE
4ns.min
td(BCLK–ALE)
th(WR–AD)
25ns.max
th(BCLK–ALE)
0ns.min
–4ns.min
ALE
td(BCLK–WR)
25ns.max
WR, WRL,
WRH
td(BCLK–DB)
40ns.max
th(BCLK–WR)
0ns.min
th(BCLK–DB)
4ns.min
DBi
td(DB–WR)
(tcyc–40)ns.min
th(WR–DB)
0ns.min
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with: VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with: VOL=0.8V, VOH=2.0V
Figure 21-5. Vcc = 5V timing diagram
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Read timing
BCLK
td(BCLK–CS)
tcyc
CSi
td(AD–ALE)
th(BCLK–CS)
th(RD–CS)
(tcyc/2)ns.min
25ns.max
4ns.min
th(ALE–AD)
(tcyc/2-25)ns.min
50ns.min
ADi
/DBi
Address
Data input
tdz(RD–AD)
tac3(RD–DB)
8ns.max
Address
th(RD–DB)
tSU(DB–RD)
0ns.min
40ns.min
td(AD–RD)
0ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
ADi
BHE
ALE
4ns.min
td(BCLK–ALE)
th(BCLK–ALE)
th(RD–AD)
(tcyc/2)ns.min
–4ns.min
25ns.max
th(BCLK–RD)
td(BCLK–RD)
0ns.min
25ns.max
RD
Write timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
tcyc
th(WR–CS)
25ns.max
4ns.min
(tcyc/2)ns.min
CSi
th(BCLK–DB)
td(BCLK–DB)
4ns.min
40ns.max
ADi
/DBi
Data output
Address
td(DB–WR)
(tcyc*3/2–40)ns.min
td(AD–ALE)
(tcyc/2–25)ns.min
ADi
BHE
ALE
Address
th(WR–DB)
(tcyc/2)ns.min
td(BCLK–AD)
th(BCLK–AD)
25ns.max
4ns.min
td(BCLK–ALE)
th(BCLK–ALE)
–4ns.min
td(AD–WR)
0ns.min
25ns.max
td(BCLK–WR)
25ns.max
WR, WRL,
WRH
th(WR–AD)
(tcyc/2)ns.min
th(BCLK–WR)
0ns.min
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with VOL=0.8V, VOH=2.0V
Figure 21-6. Vcc = 5V timing diagram
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Chip Memory Description
Outline Performance
Table 22-1 shows the outline performance of the M16C/6N (with on-chip flash memory).
Table 22-1. Outline performance of the M16C/6N (with on-chip flash memory)
Item
Performance
Power supply voltage
5V version: 4.5 to 5.5 V
(f(XIN)=16MHz, without wait, 4.2 to 5.5V)
Program/erase voltage
5V version: 4.5 to 5.5 V
(f(XIN)=12.5MHz, with one wait)
Flash memory mode
Three modes (parallel I/O, standard serial I/O, CPU
rewrite)
Erase block
division
User ROM area
See Figure 22-3.
Boot ROM area
One division (8 Kbytes) (Note 1)
Program method
In units of pages (in units of 256 bytes)
Erase method
Collective erase/block erase
Program/erase control method
Program/erase control by software command
Protect method
Protected for each block by lock bit
Number of commands
8 commands
Program/erase count
100 times
ROM code protect
Parallel I/O and standard serial modes are supported.
Note 1: The boot ROM area contains a standard serial I/O mode control program which is stored in it
when shipped from the factory. This area can be erased and programmed in only parallel I/O
mode.
Table 22-2. Power supply current (typ.) of the M16C/6N (flash memory version)
Parameter
5 V power supply current (5 V version)
Measuring condition
f(Xin)=16 MHz, without wait, no division
211
Read
Standard (Typ.)
Program
Erase
35 mA
28 mA
25 mA
Remark
Division by 4 in program/erase
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Chip Memory Description
The following shows Mitsubishi plans to develop a line of M16C/6N products (with on-chip flash memory).
(1) ROM size
(2) Package
100P6S-A ... Plastic molded QFP
ROM size
(Bytes)
External
ROM
256K
M306N0FGTFP
128K
96K
64K
32K
Flash memory version
Figure 22-1. ROM expansion
The following lists the M16C/6N products to be supported in the future.
Table 22-3. Product list
Parameter
5 V power supply current (5 V version)
Type No.
Standard (Typ.)
Program Erase
Measuring condition
Read
f(Xin)=16 MHz, without wait, no division
35 mA
28 mA
25 mA
Remark
Division by 4 in program/erase
M306N0 M C T – XXX FP
Package type:
FP : Package
100P6S-A
ROM No.
Omitted for Flash version
Temperature Range
T : Automotive 85oC version
ROM capacity:
1 : 8K bytes
2 : 16K bytes
3 : 24K bytes
4 : 32K bytes
5 : 40K bytes
6 : 48K bytes
7 : 56K bytes
8 : 64K bytes
9 : 80K bytes
A : 96K bytes
C : 128K bytes
G : 256K bytes
Memory type:
M : Mask ROM version
F : Flash ROM version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/6N Group
M16C Family
Figure 22-2. Type names, memory sizes and package
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Chip Memory Description
Flash Memory Modes
The M16C/6N (with on-chip flash memory) contains the DINOR (Divided bit line NOR) type of flash memory
that can be rewritten with a single voltage of 5 V or 3.3 V. For this flash memory, three flash memory modes
are available in which to read, program and erase: parallel I/O and standard serial I/O modes in which the
flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory
can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. The
flash memory is divided into several blocks as shown in Figure 22-3, so that memory can be erased one block
at a time. Each block has a lock bit to enable or disable execution of an erase or program operation, allowing
for data in each block to be protected.
In addition to ordinary user ROM area to store a microcomputer operation control program, the flash memory
has a boot ROM area that is used to store a program to rewriting in CPU rewrite and standard serial I/O mode.
This boot ROM area has a standard serial I/O mode control program stored in it when shipped from the
factory. However, the user can write a rewrite control program in this area that suits the user's application
system. This boot ROM area can be rewritten in parallel I/O mode only.
0C000016
Block 6 : 64K byte
0D000016
Block 5 : 64K byte
0E000016
Block 4 : 64K byte
0F000016
0F800016
0FA00016
Type No.
Flash memory
start address
0FC00016
M306N0FG
0C000016
0FFFFF16
Block 3 : 32K byte
Note 1: The boot ROM area can be rewritten in
only parallel input/output mode. (Access
to any other areas is inhibited.)
Note 2: To specify a block, use the maximum
address in the block that is an even
address.
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
User ROM area
Figure 22-3. Block diagram of on-chip flash memory
213
0FE00016
0FFFFF16
8K byte
Boot ROM area
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program or erase) under
control
of the Central Processing Unit (CPU).
In CPU rewrite mode, it is possible to write only in the user ROM area in Figure 22-3; in the boot ROM area
not possible. Make sure the program and block erase commands are issued only for the user ROM area
and each block area.
The control program for CPU rewrite mode can be stored in either user ROM- or boot ROM area. In CPU
rewrite mode, since the flash memory cannot be accessed for read by the CPU, use the rewrite control
program except in the internal flash memory.
Boot Mode
The control program for CPU rewrite mode must be rewritten into the user ROM- or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure 23-3 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVss pin low. In
this case, the CPU starts operating, using the control program in the user ROM area.
When the microcomputer is reset by pulling the P55(EPM) pin low, the CNVss pin high, and the P50(CE)
pin high, the CPU start operating, using the control program in the boot ROM area. This mode is called
the "boot" mode. The control program in the boot ROM area can also be used to rewrite the user ROM
area.
Block Address
Block addresses refer to the maximum even address of each block. These addresses are used in the
block erase command, erase all unlock blocks command, lock bit program command and read lock
status command.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Outline Performance (CPU Rewrite Mode)
The CPU rewrite mode can be executed in single-chip mode, memory expansion mode and boot mode,
allowing for only the user ROM area to be rewritten.
In CPU rewrite mode, the on-chip flash memory is operated on for erase, program or read operation by
the CPU by writing a software command. Note that in this case the control program may not be located in
the internal flash memory. For example, in single-chip mode, transferred into internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 03B716) is set to 1, transition to CPU rewrite mode
occurs and software commands can be accepted.
In CPU rewrite mode, all software commands and data are written into and read from even addresses
(address A0 of byte address = 0) 16 bits at a time. Therefore, make sure 8-bit software commands are
always written into even addresses. Data at odd addresses have no effect.
Use software commands to control program and erase operations. Whether a program or erase operation
has terminated normally or in error can be verified by reading the status register.
Figure 23-1 shows the flash memory control register. Bit 0 is the RY/BY status flag, a read-only bit indicating the operating status of the flash memory. This flag is 0 (busy) during auto write and auto erase operation; otherwise, it is 1 (ready). (Its function is equivalent to that of the RY/BY pin in parallel I/O mode.) Bit
1 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to 1, so that
software commands become acceptable. In CPU rewrite mode, the CPU becomes unable to access the
on-chip flash memory directly. Therefore, use the control program except in the internal flash memory to
set this bit to 0. For this bit to be set to 1, the user needs to write a 0 and then a 1 in it in succession. The
bit can be set to 0 by writing a 0 only.
Bit 2 is a lock bit disable bit. By setting this bit to 1, it is possible to disable erase and write protect (block
lock) effectuated by the lock bit data. (This function is equivalent to that of the WP pin in parallel I/O mode.)
The lock bit disable bit only disables the function of the lock bit and cannot set the lock bit itself. However,
if an erase operation is performed when this bit is 1, the lock bit data that is 0 (locked) is set to 1 (unlocked)
after erasure. For this bit to be set to 1, it is necessary to write a 0 and then a 1 in it in succession when the
CPU rewrite mode select bit is 1. This bit can be manipulated only when the CPU rewrite mode select bit
is 1.
Bit 3 is a flash memory reset bit, provided to reset the control circuit of the on-chip flash memory. This bit
is used when exiting CPU rewrite mode and when flash memory access has failed. If this bit is set to 1
when the CPU rewrite mode select bit is 1, the flash memory is reset. To deassert this reset, the bit needs
to be cleared to 0 after being set to 1.
Bit 5 is a user ROM area select bit which is effective in boot mode only. If this bit is set to 1 in boot mode,
the area to access is switched from the boot ROM area to the user ROM area. When the CPU rewrite
mode needs to be used in boot mode, set this bit to 1. Note that if the microcomputer is booted from the
user ROM area, it is always the user ROM area that can be accessed and this bit has no effect. When in
boot mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off. Use
the control program outside the internal flash memory to rewrite this bit.
Figure 23-2 shows a flowchart to set and reset the CPU rewrite mode. Always be sure to follow this
flowchart.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
FMCR
0
03B716
When reset
XX0000012
Bit name
Bit symbol
Function
FMCR0
RY/BY status flag
0: Busy (being written or erased)
1: Ready
FMCR1
CPU rewrite mode
select bit (Note 2)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
FMCR2
Lock bit disable bit
(Note 3)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
FMCR3
Flash memory reset bit
(Note 3)
0: Normal operation
1: Reset
R WW
R
This bit must always be set to 0.
FMCR5
User ROM area select bit ( 0: Boot ROM area is accessed
Note 5) (Effective in only 1: User ROM area is accessed
boot mode)
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Note 1: The value of the flash memory control register after a reset is "--000001".
Note 2: For this bit to be set to 1, the user needs to write a 0 and then a 1 to it in succession. Use the control
program except in the internal flash memory for write to this bit.
Note 3: For this bit to be set to 1, the user needs to write a 0 and then a 1 to it in succession when the CPU
rewrite mode select bit = 1.
Note 4: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently after setting
it to 1 (reset).
Note 5: Use the control program except in the internal flash memory for write to this bit.
Figure 23-1. Flash memory control register
Flash memory control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
0 0
0 0
Symbol
Address
FMCR2
Bit symbol
03B616
Bit name
When reset
XX0000012
Function
Reserved bits
Must always be set to "0".
FMCR22 Flash memory power
supply-OFF bit (Note)
0: Flash memory power supply
is connected.
1: Flash memory power supply-OFF
Reserved bits
Must always be set to "0".
R WW
R
Note: For this bit to be set to "1", the user needs to write a 0"" and then a 1 to it in succession. When this
procedure is not taken, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA
transfer will be executed during the interval. During parallel I/O mode, programming, erase, or read
of flash memory is not controlled by this bit, only by external pins.
Figure 23-2. Flash memory control register 2
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Set the bit 2 of FMCR2 (address 03B616) in order to reduce power consumption.Although setting this bit
to "1" helps to reduce the device's power consumption, programs cannot be read from the internal flash
memory. Make sure the operation to saet this bit to "1" and other operations to be performed while this
bit remains "1" are executed in areas outside flash memory.
Start
Single-chip mode, memory expansion
mode, or boot mode
Set processor mode register (Note 1)
Transfer CPU rewrite mode control
program to internal RAM
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
(Boot mode only)
Set user ROM area select bit to 1
Set CPU rewrite mode select bit to 1 (by
writing 0 and then 1 in succession)
Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing 1 and then 0 in succession) (Note 2)
Write 0 to CPU rewrite mode select bit
(Boot mode only)
Write 0 to user ROM area select bit (Note 3)
End
Note 1: Set bit 7 (internal ROM access wait bit) of the processor mode register 1 (address
000516) to 1 (1 wait state).
Note 2: Before exiting the CPU rewrite mode after completing erase or program operation,
always be sure to execute a read array command or reset the flash memory.
Note 3: 1 can be set. However, when this bit is 1, user ROM area is accessed.
Figure 23-3 CPU rewrite mode set/reset flowchart
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Precautions on CPU Rewrite Mode
Described below are the precautions to observe when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
When in CPU rewrite mode, set the main clock frequency as shown below, using the main clock
divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716):
6.25 MHz or less when wait bit (bit 7 at address 000516) is 0 (without internal access wait state)
12.5 MHz or less when wait bit (bit 7 at address 000516) is 1 (with internal access wait state)
(2) Instructions inhibited
The instructions listed below cannot be used when in CPU rewrite mode, because they refer to
the internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction and BRK instruction (when
using fixed vector table only)
(3) Interrupts inhibited
the NMI interrupt and address match interrupt cannot be used in CPU rewrite mode because they
refer to the internal flash memory. If interrupts have their in the INTB register, they can be used by
transferring the vector into the RAM area. The WDT interrupt can be used because the operation
mode is forcibly changed to normal mode when the interrupt is generated. Since the rewrite
operation is halted when the WDT interrupt occurs, the erase/program operation needs to be
performed over again.
(4) Internal reserved expansion bit (bit 3 at address 000516)
The reserved area of the internal memory can be changed by using the internal reserved
expansion bit (bit 3 at address 000516). However, if the CPU rewrite mode select bit (bit 1 at
address 03B716) is set to 1, the internal reserved expansion bit (bit 3 at address 000516) is also set
to 1 automatically. Similarly, if the CPU rewrite mode select bit (bit 1 at address 03B716) is set to 0,
the internal reserved bit (bit 3 at address 000516) also is set to 0 automatically.
(5) Reset
Reset input is always accepted. After a reset, the address 0C000016 through 0CFFFF16 are made
a reserved area and cannot be accessed. Therefore, if your product has this area in the user
ROM area, do not write any address of this area into the reset vector. This area is made
accessible by changing the internal reserved expansion bit (bit 3 at address 000516) in a program.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Software Commands
Table 23-1 lists the software commands available with the M16C/6NT (with on-chip flash memory).
After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or
program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored.
The content of each software command is explained below.
Table 23-1. List of software commands (CPU rewrite mode)
First bus cycle
Command
Mode
Address
Second bus cycle
Data
(D0 to D7)
Mode
Address
Read
X
Read array
Write
Read status register
Write
X
7016
Clear status register
Write
X
5016
Page program
Write
X
4116
X
2016
Write
X
A716
(Note 3)
Block erase
Erase all unlock block
Write
Write
X
(Note 6)
Third bus cycle
Data
(D0 to D7)
Data
Mode Address (D0 to D7)
FF16
Lock bit program
Write
X
7716
Read lock bit status
Write
X
7116
Write
SRD
(Note 2)
WA0 (Note 3) WD0 (Note 3) Write
(Note 4)
D016
Write
X
D016
Write
BA
D016
Read
BA
D6
BA
WA1
WD1
(Note 5)
Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored.
Note 2: SRD = Status Register Data
Note 3: WA = Write Address, WD = Write Data
WA and WD must be set sequentially from 0016 to FE16 (byte address; however, an even address). The page size is
256 bytes.
Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: D6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0.
Note 6: X denotes a given address in the user ROM area (that is an even address).
Read Array Command (FF16)
The read array mode is entered by writing the command code "FF16" in the first bus cycle. When
an even address to read is input in one of the bus cycles that follow, the content of the specified
address is read out at the data bus (D0 to D15), 16 bits at a time.
The read array mode is retained intact until another command is written.
Read Status Register Command (7016)
When the command code "7016" is written in the first bus cycle, the content of the status register
is read out at the data bus (D0 to D7) by a read in the second bus cycle.
The status register is explained in the next section.
Clear Status Register Command (5016)
This command is used to clear the bits SR3 to 5 of the status register after they are set. These bits
indicate that operation has ended in an error. To use this command, write the command code
"5016" in the first bus cycle.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Page Program Command (4116)
Page program allows for high-speed programming in units of 256 bytes. Page program operation starts
when the command code "4116" is written in the first bus cycle. In the second cycle through the 129th
bus cycle, the write data are sequentially written 16 bits at a time. At this time, the addresses A0 to A7
need to be increased by 2 from "0016" to "FE16". When the system finishes loading the data it starts an
auto write operation (data program and verify operation).
Whether or not the auto write operation is completed can be confirmed by reading the status register or
the flash memory control register. At the same time the auto write operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The status
register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to 1 upon
completion of the auto write operation. In this case, the read status register mode remains active until
the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the flash
memory is reset using its reset bit.
The RY/BY status flag of the flash memory control register is 0 during the auto write operation and 1
when the auto write operation is completed as is the status register bit 7.
After the auto write operation is completed, the status register can be read out to know the result of the
auto write operation. For details, refer to the section where the status register is detailed.
Figure 23-3 shows an example of a page program flowchart.
Each block of the flash memory can be write protected by using a lock bit. For details, refer to the
section where the data protect function is detailed.
Additional writes in the already programmed pages are prohibited.
Start
Write 4116
n=0
Write address n and
data n
n = FE16
NO
YES
Read status register
SR7 = 1?
NO
YES
Check full status
Page program
completed
Figure 23-4. Page program flowchart
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Block Erase Command (4116)
By writing the command code "2016" in the first bus cycle, the confirmation command code "D016" and
the block address of a flash memory block in the second bus cycle that follows, the system initiates an
auto erase (erase and erase verify) operation.
Whether or not the auto erase operation is completed can be confirmed by reading the status register
or the flash memory control register. At the same time the auto erase operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The status
register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned to 1 upon
completion of the erase operation. In this case, the read status register mode remains active until the
Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the flash memory is
reset using its reset bit.
The RY/BY status flag of the flash memory control register is 0 during the auto erase operation and 1
when the auto erase operation is completed as is the status register bit 7.
After the auto erase operation is completed, the status register can be read out to know the result of the
auto erase operation. For details, refer to the section where the status register is detailed.
Figure 23-4 shows an example of a block erase flowchart.
Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer
to the section where the data protect function is detailed.
Start
Write 2016
Write D016
Block address
Read status register
SR7 = 1?
NO
YES
Check full status check
Block erase
completed
Figure 23-5. Block erase flowchart
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Erase All Unlock Blocks Command (A716/D016)
By writing the command code "A716" in the first bus cycle and the confirmation command code "D016" in
the second bus cycle that follows, the system starts erasing blocks successively.
Whether or not the erase all unlock blocks command is terminated can be confirmed by reading the
status register or the flash memory control register, in the same way as for block erase. Also, the status
register can be read out to know the result of the auto erase operation.
When the lock bit disable bit of the flash memory control register is 1, all blocks are erased no matter
how the lock bit is set. On the other hand, when the lock bit disable bit is 0, the function of the lock bit
is effective and only nonlocked blocks (when lock bit data is 1) are erased.
Lock Bit Program Command (7716/D016)
By writing the command code "7716" in the first bus cycle, the confirmation command code "D016" and
the block address of a flash memory block in the second bus cycle that follows, the system sets the
lock bit for the specified block to 0 (locked).
Figure 23-5 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit data)
can be read out by a read lock bit status command.
Whether or not the lock bit program command is terminated can be confirmed by reading the status
register or the flash memory control register, in the same way as for page program.
For details about the function of the lock bit and how to reset the lock bit, refer to the section where the
data protect function is detailed.
Start
Write 7716
Write D016
block address
SR7 = 1?
NO
YES
SR4 = 0?
NO
YES
Lock bit program
completed
Figure 23-6. Lock bit program flowchart
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Read Lock Bit Status Command (7116)
By writing the command code "7116" in the first bus cycle and then the block address of a flash memory
block in the second bus cycle that follows, the system reads out the status of the lock bit of the specified
block on to the data (D6).
Figure 23-6 shows an example of a read lock bit program flowchart.
Start
Write 7116
Enter block address
NO
D6 = 0?
YES
Blocks locked
Figure 23-7. Read lock bit status flowchart
223
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Data Protect Function (Block Lock)
Each block in figure 23-1 has a nonvolatile lock bit to specify that the block should be protected (locked)
against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of
each block can be read out using the read lock bit status command.
Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash
memory control register's lock bit disable bit is set.
(1) When the lock bit disable bit is 0, a specified block can be locked or unlocked by the lock bit status
(lock bit data). Blocks whose lock bit data are 0 are locked, so they are disabled against erase/write.
On the other hand, the blocks whose lock bit data are 1 are not locked, so they are enabled for
erase/write.
(2) When the lock bit disable bit is 1, all blocks are nonlocked regardless of the lock bit data, so they are
enabled for erase/write. In this case, the lock bit data that are 0 (locked) are set to 1 (nonlocked)
after erasure, so the lock bit-actuated lock is removed.
Status Register
The status register indicates the operating status of the flash memory and whether an erase- or a
program operation has terminated normally or in error. The content of this register can be read out only
by writing the read status register command (7016). Table 23-2 details the status register.
The status register is cleared by writing the Clear Status Register command (5016).
After a reset, the status register is set to "8016".
Each bit in this register is explained below.
Write state machine (WSM) status (SR7)
After power-on, the write status machine (WSM) status is set to 1.
The write state machine (WSM) status indicates the operating status of the device, as for output on the
RY/BY pin. This status bit is set to 0 during the auto write- or the auto erase operation and is set to 1
upon completion of these operations.
Erase status (SR5)
The erase status informs the operating status of the auto erase operation to the CPU. When an erase
error occurs, it is set to 1.
The erase status is reset to 0 when cleared.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Program status (SR4)
The program status informs the operating status of the auto write operation to the CPU. When a write
error occurs, it is set to 1.
The program status is reset to 0 when cleared.
When an erase command is in error (which occurs if the command entered after the block erase
command (2016) is not the confirmation command (D016)), both the program status and erase status
(SR5) are set to 1.
When the program status or erase status is 1, the following commands entered by command write are
not accepted.
Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error):
(1) When the valid command is not entered correctly.
(2) When the data entered in the second bus cycle of the lock bit program (7716/D016), block erase
(2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is
entered, read array is assumed and the command that has been set up in the first bus cycle is
cancelled.
Block status after program
If excessive data are written (phenomenon whereby the memory cell becomes depressed which
results in data not being read correctly), "1" is set for the program status after-program at the end of the
page write operation. In other words, when writing ends successfully, "8016" is output; when writing
fails, "9016" is output; and when excessive data are written, "8816" is output.
Table 23-2. Definition of each bit in status register
Definition
Each bit of
SRD
Status name
"1"
"0"
Ready
Busy
-
-
SR7 (bit7)
Write state machine (WSM) status
SR6 (bit6)
Reserved
SR5 (bit5)
Erase status
Terminated in error
Terminated normally
SR4 (bit4)
Program status
Terminated in error
Terminated normally
SR3 (bit3)
Block status after program
Terminated in error
Terminated normally
SR2 (bit2)
Reserved
-
-
SR1 (bit1)
Reserved
-
-
SR0 (bit0)
Reserved
-
-
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Full Status Check
By performing full status check, it is possible to know the execution results of erase- and program
operations. Figure 23-7 shows a full status check flowchart and the action to take when each error
occurs.
Read status register
YES
SR4=1 and SR5
=1 ?
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Command
sequence error
NO
SR5=0?
NO
Block erase error
Should a block erase error occur, the block in error
cannot be used.
YES
SR4=0?
NO
Program error (page
or lock bit)
NO
Program error
(block)
Execute the read lock bit status command (7116)
to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.
YES
SR3=0?
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
YES
End (block erase, program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase,
erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (5016) before executing these commands.
Figure 23-8. Full status check flowchart and reemedial procedure for errors
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions To Inhibit Rewriting On-chip Flash Memory
Functions To Inhibit Rewriting On-chip Flash Memory
To prevent the contents of the on-chip flash memory from being read out or rewritten easily, the device
incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for
use in standard serial I/O mode.
ROM Code Protect Function
The ROM code protect function reading out or modifying the contents of the on-chip flash memory by
using the ROM code protect address (0FFFFF16) when in parallel I/O mode. Figure 23-8 shows the
ROM code protect control address (0FFFFF16). (This address exists in the user ROM area.)
If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the
contents of the on-chip flash memory are protected against readout and modification. ROM code
protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against
readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and
level 2, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to "00", ROM code protect is turned off, so that the
contents of the on-chip flash memory can be read out or modified. Once ROM code protect is turned
on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the
serial I/O- or some other mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ROMCP
Address
0FFFFF16
When reset
FF16
Bit name
Bit symbol
Function
Always set this bit to 1.
Reserved bit
ROM code protect level
2 set bit (Note 1, 2)
b3 b2
ROMCP2
ROM code protect reset
bit (Note 3)
b5 b4
ROMCR
ROMCP1
ROM code protect level
1 set bit (Note 1)
b7 b6
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parallel input/
output mode, they need to be rewritten in serial input/output or some other mode.
Figure 23-9. ROM code protect control address
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions To Inhibit Rewriting On-chip Flash Memory
ID Code Check Function
Use this function in standard serial I/O mode. When the contents of the flash memory is not blank, the
ID code sent from the serial programmer is compared with the ID code written in the flash memory to
see if they match. If the ID codes do not match, the commands sent from the serial programmer are not
accepted. The ID code consists of 8-bit data, the area of which, beginning with the first byte, are
0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program
which has the ID code preset at these addresses to the flash memory.
Address
0FFFDF16 to 0FFFDC16
ID1 Undefined instruction vector
0FFFE316 to 0FFFE016
ID2 Overflow vector
0FFFE716 to 0FFFE416
BRK instruction vector
0FFFEB6 to 0FFFE816
ID3 Address match vector
0FFFEF16 to 0FFFEC16
ID4 Single step vector
0FFFF316 to 0FFFF016
ID5 Watchdog timer vector
0FFFF716 to 0FFFF416
ID6 DBC vector
0FFFFB16 to 0FFFF816
ID7
0FFFFF16 to 0FFFFC16
NMI vector
Reset
4 bytes
Figure 23-10. ID code store addresses
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Description of Pin Function (Flash Memory Parallel I/O Mode)
Pin name
Signal name
Function
I/O
Apply 3.3 ± 0.3 V to the Vcc pin (for both 5V and 3.3V versions) and 0 V to
the Vss pin.
VCC,VSS
Power supply input
CNVSS
CNVSS
I
Connect this pin to VCC.
RESET
Reset input
I
Reset input pin. When reset is held low, more than 20 cycles of clock are
required at the XIN pin.
XIN
Clock input
I
XOUT
Clock output
O
Connect a ceramic or crystal resonator between the XIN and XOUT pins.
When entering an externally derived clock, enter it from XIN and leave
XOUT open.
BYTE
BYTE
I
Connect this pin to Vcc or Vss.
AVCC, AVSS
Analog power supply input
VREF
Reference voltage input
O
Enter the reference voltage for AD from this pin.
P00 to P07
Data I/O D0 to D7
I/O
These are data D0–D7 input/output pins.
P10 to P17
Data I/O D8 to D15
I/O
These are data D8–D15 input/output pins.
P20 to P27
Address input A0
to A6
I
These are address A0–A6 (word address) input pins. Address Ai in parallel
input/output mode is equivalent to Ai + 1 in microcomputer mode.
P30 to P37
Address input A7 to A14
I
These are address A7–A14 (word address) input pins.
P40 to P42
Address input A15 to A17
I
These are address A15–A17 (word address) input pins.
P43 to P47
Input port P4
I
Enter high signals to these pins.
P50
CE input
I
This is a CE input pin.
P51
OE input
I
This is a OE input pin.
P52
WE input
I
This is a WE input pin.
P53
WP input
I
This is a WP input pin.
P54
BSEL input
I
This is a BSEL input pin.
P55
EPM input
I
Enter a low signal to this pin.
P56 to P57
Input port P5
I
Enter high signals to these pins.
P60 to P67
Input port P6
I
Enter high signals to these pins.
P70 to P77
Input port P7
I
Enter high signals to these pins.
P80 to P81
Input port P8
I
Enter high signals to these pins.
P82 to P84
Input port P8
I
Enter low signals to these pins.
P85
RP input
I
This is a RP input pin.
P86 to P87
Input port P8
I
Enter high signals to these pins.
P90
Input port P9
I
Enter high or low signals to these pins or leave these pins open.
P91
RY/BY output
Connect AVSS to Vss and AVcc to Vcc, respectively.
O
This is a RY/BY output pin.
P92 to P97
Input port P9
I
Enter high or low signals to these pins or leave these pins open.
P100 to P107
Input port P10
I
Enter high or low signals to these pins or leave these pins open.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Parallel I/O Mode
The parallel I/O mode is entered by making connections shown in Figure 24-2 and then turning the Vcc power
supply (3.3 V) on. In this mode, the M16C/6N (with on-chip flash memory) operates in a manner similar to the
DINOR flash memory M5M29FB800 by Mitsubishi. Note, however, that there are some differences in regard
to the functions not available with the microcomputer and matters related to memory size, as shown in Table
24-1.
Only in parallel I/O mode, the M16C/6N (with on-chip flash memory), either 5V- or 3.3V version, needs to be
operated with a supply voltage of 3.3 V + 0.3 V. Table 24-2 shows pin relationship between the M16C/6N and
M5M29FB800 in parallel I/O mode.
Table 24-1. Differences from the M5M29FB800
Functions not available with microcomputer
Differences in matters related to memory capacity
• Device ID code readout
• Flash memory capacity
• Suspend/resume functions
• Block arrangement (See Figure CC-1)
• Sleep function
Functions only available with microcomputer
• Additional write function
• Boot ROM area selection
Note: Do not apply VHH (12 V) to the A9 and RP pins.
Table 24-2. Pin relationship in parallel I/O mode
M16C/62(on-chip flash memory)
M5M29FB800
VCC
VCC
VCC
VSS
VSS
VSS
Address input
P21 to P27,
P30 to P37, P40, P41, P42
A0 to A16
Data I/O
P00 to P07, P10 to P17
D0 to D15
OE input
P51
OE
CE input
P50
CE
WP input
P53
WP
WE input
P52
WE
BYTE input
BYTE
BYTE
RP input
NMI
RP
RY/BY output
P70
RY/BY
BSEL input (Note)
P54
Note: BSEL is used to choose between the user ROM and boot ROM areas and has no
equivalent pin in the M5M29FB800.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Address
The M16C/6N (with on-chip flash memory) has word- and byte modes which are switched over by the BYTE
pin.
When the BYTE pin is high, the 16-bit data bus is selected and the memory is accessed in 16 bits. In this
case, addresses must always be specified by an even address. When the BYTE pin is low, the 8-bit data bus
is selected and the memory is accessed in 8 bits.
The user ROM is divided into blocks as shown in Figure 24-1. The block address referred to in this manual is
the maximum even address of each block.
0C000016
Block 6 : 64K byte
0D000016
Block 5 : 64K byte
0E000016
Block 4 : 64K byte
0F000016
0F800016
0FA00016
Type No.
Flash memory
start address
0FC00016
M306N0FGT
0C000016
0FFFFF16
Block 3 : 32K byte
Note 1: The boot ROM area can be rewritten in
only parallel input/output mode. (Access
to any other areas is inhibited.)
Note 2: To specify a block, use the maximum
address in the block that is an even
address.
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
User ROM area
Figure 24-1. Block diagram of on-chip flash memory
231
0FE00016
0FFFFF16
8K byte
Boot ROM area
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
D6
D4
Vss
Vss
D2
EPM
RESET
D0
Mode setup method
Value
Signal
Vcc
CNVss
D7
D5
D3
D1
P07/D7
P06/D6
P05/D5
P04/D4
P03/D3
P02/D2
P01/D1
P00/D0
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVcc
P97/ADTRG/SIN4
81
82
83
84
85
86
87
88
89
90
91
92
93
94
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
M306N0FGTFP
(100P6S)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P44/CS0
P45/CS1
P46/CS2
P47/CS3
P50/WRL/WR
P51/WRH/BHE
P52/RD
P53/BCLK
P54/HLDA
P55/HOLD
P56/ALE
P57/RDY/CLKOUT
P60/CTS0/RTS0
P61/CLK0
P62/RxD0
P63/TXD0
P64/CTS1/RTS1/CTS0/CLKS1
P65/CLK1
P66/RxD1
P67/TXD1
CE
WE
BSEL
Vss
Vcc
OE
WP
EPM
Figure 24-2. Pin connection diagram in parallel I/O mode
232
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
4 5
RP
Connect
oscillator
circuit.
RESET
2 3
CNVss
1
BYTE
95
96
97
98
99
100
RY/BY
P96/ANEX1/SOUT4
P95/ANEX0/CLK4
P94/DA1/TB4IN
P93/DA0/TB3IN
P92/TB2IN/SOUT3
P91/TB1IN/SIN3
P90/TB0IN/CLK3
BYTE
CNVss
P87/XCIN
P86/XCOUT
RESET
XOUT
VSS
XIN
VCC
P85/NMI
P84/INT2
P83/INT1
P82/INT0
P81/TA4IN/U
P80/TA4OUT/U
P77/TA3IN
P76/TA3OUT
P75/TA2IN/W
P74/TA2OUT/W
P73/CTS2/RTS2/TA1IN/V
P72/CLK2/TA1OUT/V
P71/RxD2/SCL/TA0IN/TB5IN
P70/TXD2/SDA/TA0OUT
P10/D8
P11/D9
P12/D10
P13/D11
P14/D12
P15/D13/INT3
P16/D14/INT4
P17/D15/INT5
P20/A0(/D0/-)
P21/A1(/D1/D0)
P22/A2(/D2/D1)
P23/A3(/D3/D2)
P24/A4(/D4/D3)
P25/A5(/D5/D4)
P26/A6(/D6/D5)
P27/A7(/D7/D6)
Vss
P30/A8(/-/D7)
Vcc
P31/A9
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
P40/A16
P41/A17
P42/A18
P43/A19
D8
D9
D10
D11
D12
D13
D14
D15/A-1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM- and boot ROM areas shown in Figure 24-1 can be rewritten.
BSEL pin is used to select between these two areas. The user ROM area is selected by pulling the BSEL
input low; the boot ROM area is selected by driving the BSEL input high. Both areas of flash memory can
be operated on in the same way.
Program- and block erase operations can be performed in the user ROM area. The user ROM area and its
blocks are shown in Figure 24-1.
The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at address 0FE00016 through
0FFFFF16. Make sure program- and block erase operations are always performed within this address
range. (Access to any location outside this address range is prohibited.)
In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area
has a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.
Therefore, if the device is going to be used in standard serial I/O mode, do not rewrite the boot ROM area.
Functional Outline (Parallel I/O Mode)
In parallel I/O mode, bus operation modes — Read, Output Disable, Standby, Write and Deep Power
Down — are selected by the status of the CE-, OE-, WE- and RP input pins.
The contents of erase-, program- and other operations are selected by writing a software command. The
data, status register, etc. in memory can be read out only by a read after software command input.
Program- and erase operations are controlled using software commands.
Table 24-3. Relationship between control signals and bus operation modes
Pin name
Read
D0 to D15
CE
OE
WE
RP
Array
VIL
VIL
VIH
VIH
Data output
Status register
VIL
VIL
VIH
VIH
Status register data output
Lock bit status
Mode
VIL
VIL
VIH
VIH
Lock bit data (D6) output
Output disabled
VIL
VIH
VIH
VIH
Hi-Z
Stand by
VIH
X
X
VIH
Hi-Z
Program
VIL
VIH
VIL
VIH
Command/data input
Erase
VIL
VIH
VIL
VIH
Command input
Other
VIL
VIH
VIL
VIH
Command input
X
X
X
VIL
Hi-Z
Write
Deep power down
Note: X can be VIL or VIH.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Bus Operation Modes
Read
The Read mode is entered by pulling the OE pin low when the CE pin is low and the WE- as well as RP
pins are high. There are three read modes: Array, Status Register and Lock Bit Status which are selected
by software command input. In Read mode, the data corresponding to each software command entered
are output from the data I/O pins D0 – D15. The Read Array mode is automatically selected when the device
is powered on after it exits Deep Power Down mode.
Output Disable
The Output Disable mode is entered by pulling the CE pin low and the WE-,OE- and RP pins high. Also,
the data I/O pins are placed in the high-impedance state.
Standby
The Standby mode is entered by driving the CE pin high when the RP pin is high. Also, the data I/O pins
are placed in the high-impedance state. However, if the CE pin is set high during erase- or program
operation, the internal control circuit does not halt immediately and normal power consumption is required
until the operation under way is completed.
Write
The Write mode is entered by pulling the WE pin low when the CE pin is low and the OE- as well as RP
pins are high. In this mode, the device accepts the software commands or write data entered from the data
I/O pins. A program-, erase- or some other operation is initiated depending on the content of the software
command entered here. The input data such as addresses and software command are latched at the rising
edge of WE or CE whichever occurs earlier.
Deep Power Down
The Deep Power Down is entered by pulling the RP pin low. Also, the data I/O pins are placed in the highimpedance state. When the device is freed from Deep Power Down mode, the Read Array mode is
selected and the content of the status register is set to "8016". If the RP pin is pulled low during erase- or
program operation, the operation under way is cancelled and the data in the relevant block becomes
invalid.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Software Commands
Table 24-4 lists the software commands available with the M16C/6NT (with on-chip flash memory). By
entering a software command from the data I/O pins (D0 – D7) in Write mode, specify the content of the
operation, such as erase- or program operation, to be performed. When entering a software command, the
upper byte (D8 – D15) is ignored.
Table 24-4. Software command list (parallel I/O mode)
First bus cycle
Command
Mode
Second bus cycle
Data
Address (D0 to D7)
Mode
Address
Read
X
Read array
Write
X (Note 6)
FF16
Read status register
Write
X
7016
Clear status register
Write
X
5016
Page program
Write
X
4116
X
2016
Write
X
A716
(Note 3)
Block erase
Erase all unlock block
Write
Write
Lock bit program
Write
X
7716
Read lock bit status
Write
X
7116
Write
Third bus cycle
Data
(D0 to D7)
SRD
Mode
(Note 2)
WA0 (Note 3) WD0 (Note 3) Write
(Note 4)
D016
Write
X
D016
Write
BA
D016
Read
BA
D6
BA
Data
Address (D0 to D7)
WA1
WD1
(Note 5)
Note 1: When a software command is input, the upper byte of data (D8 to D15) is ignored.
Note 2: SRD = Status Register Data
Note 3: WA = Write Address, WD = Write Data
WA and WD must be set sequentially from 0016 to FE16 (an even address). The page size is 256 bytes.
Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: D6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0.
Read Array Command (FF16)
The Read Array mode is entered by writing the command code "FF16" in the first bus cycle. When an
address to read is input in one of the bus cycles that follow, the content of the specified address is output
from the data bus (D0 – D15). The address entered here must be an even address when the BYTE pin is
high (16-bit mode).
The Read Array mode is retained intact until another command is written.
The Read Array mode is also selected automatically when the device is powered on and after it exits Deep
Power Down mode.
Read Status Register Command (7016)
When the command code "7016" is written in the first bus cycle, the content of the status register is output
from the data bus (D0 – D7) by a read in the second bus cycle. Since the content of the status register
is updated at the falling edge of OE or CE, the OE- or CE signal must be asserted each time the
status is read. The status register is explained in the next section.
Clear Status Register Command (5016)
This command is used to clear the bits SR3 to 5 of the status register after they are set. These bits
indicate that operation has ended in an error. To use this command, write the command code "5016" in the
first bus cycle.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Page Program Command (4116)
Page programming enables high-speed programming in blocks of 256 bytes. The page programming
operation is started when the "4116" command code is written for the first bus cycle. Write data are then
written sequentially from the second bus cycle to the 129th bus cycle. In this case, when the byte pin is
"H" level, the address must be odd and increased by two from "0016" to "FF16". When the byte pin is "L"
level, the address must increase from "0016" to "FF16". When data loading ends, the auto write (data
program and verify) operation starts.
Auto Write end can be verified by reading the status register or the status of the RY/BY signal. At the
start of the auto write operation, the read status register mode is automatically engaged, so the contents
of the status register can be read from the data I/O pins (D0 – D7). Status register bit 7 (SR7) becomes
"0" when the auto write operation starts and returns to "1" when it ends. In this way, the read status
register mode is maintained until the next read array command (FF16) or read lock bit status command
(7116) is written.
Similar to the status register bit 7, the RY/BY pin is "L" level during the auto write period and becomes
"H" level when auto write ends.
After the auto write operation ends, the result of the operation can be known by reading the status
register. For more information, see the section on the status register.
Figure 24-3 shows a flowchart of the page program. For the operation timing of the page program, see
the time chart in the section on electric characteristics.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection. Additional writing is not allowed with already programmed pages.
Start
Write 4116
n=0
Write address n and
data n
n=FF16
n=FE16
n=n+1/n=n+2
NO
YES
Read status register
SR7=1?
NO
YES
Run full status check if
needed
Page program end
Figure 24-3. Page program flowchart
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Block Erase Command (2016/D016)
Writing the "2016" command code for the first bus cycle and, after that, the "D016" verify command code
and the block address of a block for the second bus cycle starts the auto erase (erase and erase verify)
operation for the specified block.
Auto erase end can verified by reading the status register or the status of the RY/BY signal. At the start
of the auto erase operation, the read status register mode is automatically engaged, so the contents of the
status register can be read from the data I/O pins (D0 – D7). Status register bit 7 (SR7) becomes "0" when
the auto erase operation starts and returns to "1" when it ends. In this way, the read status register mode
is maintained until the next read array command (FF16) or read lock bit status command (7116) is written.
Similar to the status register bit 7, the RY/BY pin is "L" level during auto erase operations and becomes
"H" level when auto erase ends.
After the block erase operation ends, the result of the operation can be known by reading the status
register. For more information, see the section on the status register.
Figure 24-4 shows a flowchart of block erasing. For the block erase operation timing, see time chart in the
section on electric characteristics.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
Start
Write 2016
Write D016 and block
address
Read status register
SR7=1?
NO
YES
Run full status check if
needed
Block erase end
Figure 24-4. Block erase flowchart
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Erase All Unlocked Blocks Command (A716/D016)
Writing the "A716" command code for the first bus cycle and the "D016" verify command code for the
second bus cycle continuously executes the block erase operation for all the blocks. In this case, it is not
necessary to specify an address in the second bus cycle.
Even after the erase all unlock blocks operation ends, as with block erase, the end of the operation can be
verified by reading the status register or the status of the RY/BY signal. Also, the result of the erase
operation can be known by reading the status register.
When the WP pin is "H" level, all blocks are erased regardless of lock bit status. When the WP pin is "L"
level, The lock pin is enabled and only unlocked blocks (lock bit data are "1") are erased.
Lock Bit Program Command (7716/D016)
Writing the "7716" command code for the first bus cycle and, after that, the "D016" verify command code as
well as the block address of a block for the second bus cycle writes "0" (lock) for the lock bit of the
specified block.
Figure 24-5 shows an example of flowchart of the lock bit program. The lock bit status (lock bit data) can
be read with the read lock bit status command.
As with the page program, the end of the lock bit program auto write operation can be verified by reading
the status register or the status of the RY/BY signal.
For information on the lock bit function, reset procedure and so on, see the section on the data protection
function.
Start
Write 7716
Write D016 and block
address
SR7=1?
NO
YES
SR4=0?
NO
YES
Lock bit program end
Figure 24-5. Lock bit program flowchart
238
Lock bit program error
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Read Lock Bit Status Command (7116)
After the "7116" command code is written for the first bus cycle and the address block of a given block is
specified in the second bus cycle, the lock status of the specified block is output as data I/O pin bit 6 (D6).
Figure 24-6 shows an example of flowchart of the read lock bit status.
Star
t
Write 7116
Write block address
NO
(Note)
D6 = 0?
YES
Block
unlocked
Block locked
Note: Data bus bit 6.
Figure 24-5. Lock bit program flowchart
239
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Data Protection Function (Block Lock)
Each of the blocks in Figure 24-1 has a nonvolatile lock bit that specifies protection (block lock) against
erasing/writing. A block is locked (writing "0" for the lock bit) with the lock bit program command. Also, the
lock bit of any block can be read with the read lock bit status command.
Block lock enable/disable is determined by the status of the lock bit itself and the status of the RP- and
WP pins. This relationship is given in Table 24-5.
(1) When the RP pin is "L" level, the deep power down mode is engaged and all blocks are locked.
(2) When the RP pin is "H" level and the WP pin "L" level, the specified block can be locked/unlocked
using the lock bit (lock bit data). Blocks with "0" lock bit data are locked and cannot be erased or
written in. On the other hand, blocks with "1" lock bit data are unlocked and can be erased or written
in.
(3) When the RP pin and the WP pin are both "H" level, all blocks are unlocked regardless of lock bit
data status and can be erased or written in. In this case, lock bit data that were "0" before the block
was erased are set to "1" (unlocked) after erasing, therefore the block is actually unlocked with the
lock bit.
Table 24-5. Block lock conditions
RP
WP
(Note 1)
Lock bit
(Internal)
Block lock
VIL
X
X
Locks all blocks (Deep power down mode)
VIH
VIL
0
Locks block using lock bit data
VIH
VIL
1
Unlocks block using lock bit data
VIH
VIH
X
Unlocks all blocks (Note 2)
Note 1: During read/write operations or when the write state machine (WSM) status is busy (SR7
= "0"), do not switch WP pin state.
Note 2: In this case, the lock bit is set to "1" after the block is erased.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Status Register
The status register indicates status such as whether an erase operation or a program ended successfully
or in error. It can be read under the following conditions.
(1) In the read array mode or lock bit status mode, when the read status register command (7016) is
written and the block address is subsequently read.
(2) In the period from when the page program auto write or auto erase starts to when the read array
command (FF16) or the read lock bit status command (7116) is input.
The status register is cleared in the following situations.
(1) When the clear status register command (5016) is written
(2) When in the deep power down mode
(3) When power is turned off
Table 24-6 gives the definition of each status register bit. When power is turned on or returning from the
deep power down mode, the status register outputs "8016".
Table 24-6. Status register
Definition
Symbol
Status
"1"
"0"
Ready
Busy
SR7 (D7)
Write state machine (WSM) status
SR6 (D6)
Reserved
SR5 (D5)
Erase status
Ended in error
Ended successfully
SR4 (D4)
Program status
Ended in error
Ended successfully
SR3 (D3)
Program status after-program
Ended in error
Ended successfully
SR2 (D2)
Reserved
SR1 (D1)
Reserved
SR0 (D0)
Reserved
Write State Machine (WSM) Status (SR7)
The write state machine (WSM) status indicates the operating status of the flash memory. When
power is turned on or returning from deep power down mode, it is set to "1". This bit is "0" (busy)
during the auto write- or erase operation and becomes "1" when the operation ends.
Erase Status (SR5)
The erase status reports the operating status of the auto erase operation. If an erase error occurs, it
is set to "1". When the erase status is cleared, it is set to "0".
Program Status (SR4)
The program status reports the operating status of the auto write operation. If a write error occurs, it
is set to "1". When the program status is cleared, it is set to "0".
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Block Status After Program (SR3)
If excessive data are written (phenomenon whereby the memory cell becomes depressed which
results in data not being read correctly), the block status after-program is set to "1" at the end of the
page write operation. In other words, when writing ends successfully, "8016" is output; when writing
fails, "9016" is output; and when excessive data are written, "8816" is output.
If "1" is written for any of SR5-, SR4- or SR3 bits, the page program-, block erase-, erase all unlocked
blocks- and lock bit program commands are not accepted. Before executing these commands,,
execute the clear status register command (5016) and clear the status register.
Also in the following cases, both SR4 and SR5 are set to "1" (command sequence error).
(1) If data other than "D016" or "FF16" are input for the second bus cycle data of the lock bit
program command (7716/D016).
(2) If data other than "D016" or "FF16" are input for the second bus cycle data of the block erase
command (2016/D016).
(3) If data other than "D016" or "FF16" are input for the second bus cycle data of the erase all
unlocked blocks command (A716/D016). However, inputting "FF16" engages the read array
mode and cancels the setup command in the first bus cycle.
Full Status Check
Results of executed erase- and program operations can be known by running a full status check.
Figure 24-7 shows a flowchart of the full status check and explains how to remedy errors which may
occur.
Read status register
YES
SR4=1 and SR5
=1 ?
Command
sequence error
NO
SR5=0?
NO
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Block erase error
Should a block erase error occur, the block in error
cannot be used.
YES
SR4=0?
NO
Program error (page
or lock bit)
NO
Program error
(block)
YES
SR3=0?
YES
Execute the read lock bit status command (7116)
to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
End (block erase, program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase,
erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (5016) before executing these commands.
Figure 24-7. Full status flowchart and remedial procedure for errors
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
Ready/Busy (RY/BY) pin
The RY/BY pin is an output pin which, like the write state machine (WSM) status (SR7), indicates the
operating status of the flash memory. It is "L" level during the auto write- or the auto erase operation
and becomes to the high-impedance state (ready state) when the operation ends. The RY/BY pin
requires an external pull-up.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Pin functions (flash memory standard serial I/O mode)
Pin
Description Name
I/O
Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin.
VCC,VSS
Power input
CNVSS
CNVSS
I
Connect to Vcc pin.
RESET
Reset input
I
Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
XIN
Clock input
I
XOUT
Clock output
O
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
and open XOUT pin.
BYTE
BYTE
I
AVCC, AVSS
Analog power supply input
VREF
Reference voltage input
O
P00 to P07
Input port P0
I
P10 to P17
Input port P1
I
P20 to P27
Input port P2
I
P30 to P37
Input port P3
I
P40 to P47
Input port P4
I
P51 to P54,
P56, P57
Input port P5
I
P50
CE input
I
P55
EPM input
I
P60 to P63
Input port P6
I
P64
BUSY output
O
P65
SCLK input
I
P66
RxD input
I
P67
TxD output
O
P70 to P77
Input port P7
I
P80 to P87
Input port P8
I
P9 to P97
Input port P9
I
P100 to P107
Input port P10
I
Connect this pin to Vcc or Vss.
Connect AVSS to Vss and AVcc to Vcc, respectively.
Enter the reference voltage for AD from this pin.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" level signal.
Input "L" level signal.
Input "H" or "L" level signal or open.
BUSY signal output pin
Serial clock input pin
Serial data input pin
Serial data output pin
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
P07/D7
P06/D6
P05/D5
P04/D4
P03/D3
P02/D2
P01/D1
P00/D0
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVcc
P97/ADTRG/SIN4
Mode setup method
Value
Signal
CNVss
Vcc
Vss
EPM
RESET
Vss to Vcc
Vcc
CE
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Connect
oscillator
circuit.
M306N0FGTFP
(100P6S)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P44/CS0
P45/CS1
P46/CS2
P47/CS3
P50/WRL/WR
P51/WRH/BHE
P52/RD
P53/BCLK
P54/HLDA
P55/HOLD
P56/ALE
P57/RDY/CLKOUT
P60/CTS0/RTS0
P61/CLK0
P62/RxD0
P63/TXD0
P64/CTS1/RTS1/CTS0/CLKS1
P65/CLK1
P66/RxD1
P67/TXD1
SCLK
TxD
245
CE
EPM
BUSY
RxD
Vss
Vcc
Figure 25-1. Pin connections for serial I/O mode
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
2 3 4 5
RESET
1
CNVss
P96/ANEX1/SOUT4
P95/ANEX0/CLK4
P94/DA1/TB4IN
P93/DA0/TB3IN
P92/TB2IN/SOUT3
P91/TB1IN/SIN3
P90/TB0IN/CLK3
BYTE
CNVss
P87/XCIN
P86/XCOUT
RESET
XOUT
VSS
XIN
VCC
P85/NMI
P84/INT2
P83/INT1
P82/INT0
P81/TA4IN/U
P80/TA4OUT/U
P77/TA3IN
P76/TA3OUT
P75/TA2IN/W
P74/TA2OUT/W
P73/CTS2/RTS2/TA1IN/V
P72/CLK2/TA1OUT/V
P71/RxD2/SCL/TA0IN/TB5IN
P70/TXD2/SDA/TA0OUT
P10/D8
P11/D9
P12/D10
P13/D11
P14/D12
P15/D13/INT3
P16/D14/INT4
P17/D15/INT5
P20/A0(/D0/-)
P21/A1(/D1/D0)
P22/A2(/D2/D1)
P23/A3(/D3/D2)
P24/A4(/D4/D3)
P25/A5(/D5/D4)
P26/A6(/D6/D5)
P27/A7(/D7/D6)
Vss
P30/A8(/-/D7)
Vcc
P31/A9
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
P40/A16
P41/A17
P42/A18
P43/A19
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Standard Serial I/O Mode
The standard serial I/O mode serially inputs and outputs the software commands, addresses and data necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific serial
programmer.
The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like
rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard
serial mode is started by clearing the reset with an "H" level signal at the P50 (CE) pin, an "L" signal at the P55
(EPM) pin and an "H" level at the CNVss pin. (For the normal microprocessor mode, set CNVss to "L".)
This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if the
boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.
Figure 25-1 shows the pin connections for the standard serial I/O mode. Serial data I/O uses four UART1
pins: CLK1, RXD1, TXD1 and RTS1 (BUSY).
The CLK1 pin is the transfer clock input pin and it transfers the external transfer clock. The TXD1 pin outputs
the CMOS signal. The RTS1 (BUSY) pin outputs an "L" level when reception setup ends and an "H" level
when the reception operation starts. Transmission- and reception data are transferred serially in 8-byte
blocks.
In the standard serial I/O mode, only the user ROM area shown in 24-1 can be rewritten, the boot ROM area
cannot.
The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code does
not match the content of the flash memory, the command sent from the programmer is not accepted.
Function Overview (Standard Serial I/O Mode)
In the standard serial I/O mode, software commands, addresses and data are input and output between the
flash memory and an external device (serial programmer, etc.) using a 4-wire clock-synchronized serial I/O
(UART1). In reception, the software commands, addresses and program data are synchronized with the
rise of the transfer clock input to the CLK1 pin and input into the flash memory via the RXD1 pin. In
transmission, the read data and status are synchronized with the fall of the transfer clock and output to the
outside from the TXD1 pin.
The TXD1 pin is CMOS output. Transmission is in 8-bit blocks and LSB first.
When busy, either during transmission or reception, or while executing an erase operation or program the
RTS1 (BUSY) pin is "H" level. Accordingly, do not start the next transmission until the RTS1 (BUSY) pin is
"L" level.
Also, data in memory and the status register can be read after inputting a software command. It is possible
to check flash memory operating status or whether a program- or erase operation ended successfully or in
error by reading the status register.
Software commands and the status register are explained here following.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Software Commands
Table 25-1 lists software commands. In the standard serial I/O mode, erase operation, programs and
reading are controlled by transferring software commands via the RXD pin. Software commands for the
serial I/O mode are basically the same as those for the parallel I/O mode, but there are six additional
commands to make up for WP pin functions used in the parallel I/O mode. These commands are lock bit
disable, lock bit enable, ID check, download, version information output and boot area output.
Table 25-1. Software commands (standard serial I/O mode)
Control command
2nd byte
3rd byte
4th byte 5th byte 6th byte
Address
(middle)
Address
(high)
Data
output
Data
output
Data
output
Address
(middle)
Address
(high)
Data
input
Data
input
Data
input
Address
(middle)
D016
Address
(high)
D016
SRD
output
SRD1
output
1
Page read
FF16
2
Page program
4116
3
Block erase
2016
4
Erase all unlocked blocks
A716
5
Read status register
7016
6
Clear status register
5016
7
Read lockbit status
7116
Address
(middle)
Address
(high)
8
Lockbit program
7716
Address
(middle)
Address
(high)
9
Lockbit enable
7A16
10 Lockbit disable
7516
11 ID check function
F516
12 Download function
FA16
Address
(low)
Size
(low)
Address
(middle)
Size
(high)
Address
(high)
Checksum
Version
data
output
Address
(middle)
Version
data
output
Address
(high)
Version
data
output
Data
output
13 Version data output function FB16
14 Boot area output function
FC16
When ID is
not verificate
Not
acceptable
Data
output to
259th
byte
Data input
Not
to 259th acceptable
byte
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Not
acceptable
Lock bit
data
output
D016
ID size
ID1
To ID7
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Data
input
To
Not
required
acceptable
number
of times
Version
Version Version
Acceptable
data
data data output
output output to 9th byte
Data
Data
Data
Not
output to acceptable
output output
259th byte
• Shading indicates transfer from flash memory microcomputer to serial programmer. All other data is
transferred from the serial programmer to the flash memory microcomputer.
• SRD refers to status register data. SRD1 refers to status register 1 data.
• All commands can be accepted when the flash memory is totally blank.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Read Array Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time.
Execute the read array command as explained below.
(1) Send the "FF16" command code in the first byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the second and the third bytes of the transmission
respectively.
(3) From the fourth byte onward, data (D0 to D7) for the page (256 bytes) specified with addresses A8
to A23 will be output sequentially from the smaller address first in synchronization with the rise of
the clock.
CLK1
TxD1
FF16
A8 to
A15
A16 to
A23
data0
RxD1
data255
RTS1(BUSY)
Figure 25-2. Timing for reading array
Read Status Register Command
This command reads status information. When the "7016" command code is sent in the first byte of the
transmission, the contents of the status register (SRD) specified in the second byte of the transmission
and the contents of status register 1 (SRD1) specified in the third byte of the transmission are read.
CLK1
TxD1
RxD1
7016
SRD
output
RTS1(BUSY)
Figure 25-3. Timing for reading the status register
248
SRD1
output
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Clear Status Register Command
This command clears the bits (SR3 – SR5) which are set when the status register operation ends in error.
When the "5016" command code is sent in the first byte of the transmission, the abovementioned bits are
cleared. When the clear status register operation ends, the RTS1 (BUSY) signal changes from the "H" to
the "L" level.
CLK1
TxD1
5016
RxD1
(RTS1)BUSY
Figure 25-4. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained below.
(1) Send the "4116" command code in the first byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the second and the third bytes of the transmission
respectively.
(3) From the fourth byte onward, as write data (D0 – D7) for the page (256 bytes) specified with
addresses A8 to A23 are input sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the "H" to the
"L" level. The result of the page program can be known by reading the status register. For more information, see the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed in the already programmed pages.
CLK1
TxD1
4116
A8 to
A15
A16 to
A23
RxD1
RTS1(BUSY)
Figure 25-5. Timing for the page program
249
data0
data255
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
below.
(1) Send the "2016" command code in the first byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the second and the third bytes of the transmission
respectively.
(3) Send the verify command code "D016" in the fourth byte of the transmission. With the verify
command code, the erase operation will start for the specified block in the flash memory. Write the
highest address of the specified block for addresses A16 to A23.
When the block ease ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. After the block
erase ends, the result of the block erase operation can be known by reading the status register. For more
information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
CLK1
TxD1
2016
A8 to
A15
A16 to
A23
RxD1
RTS1(BUSY)
Figure 25-6. Timing for block erase
250
D016
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Erase All Unlocked Blocks Command
This command erases the content of all the blocks. Execute the erase all unlocked blocks command as
explained below.
(1) Send the "A716" command code in the first byte of the transmission.
(2) Send verify command code "D016" in the second byte of the transmission. With the verify command code, the erase operation will start and continue for all the block in the flash memory.
When the block erase ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of
the erase operation can be known by reading the status register. Each block can be erase-protected with
the lock bit. For more information, see the section on the data protection function.
CLK1
TxD1
A716
D016
RxD1
RTS1(BUSY)
Figure 25-7. Timing for erasing all unlocked blocks
Lock Bit Program Command
This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained below.
(1) Send the "7716" command code in the first byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the second and the third bytes of the transmission
respectively.
(3) Send verify command code "D016" in the fourth byte of the transmission. With the verify command
code, "0" is written for the lock bit of the specified block. Write the highest address of the specified
block for the addresses A8 to A23 .
When the writing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. Lock bit status can
be read with the read lock bit status command. For information on the lock bit function, see the section on
the data protection function.
CLK1
TxD1
7716
A8 to
A15
RxD1
RTS1(BUSY)
Figure 25-8. Timing for lock bit program
251
A16 to
A23
D016
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status command
as explained below.
(1) Send the "7116" command code in the first byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the second and the third bytes of the transmission
respectively.
(3) The lock bit data of the specified block are output in the fourth byte of the transmission. Write the
highest address of the specified block for the addresses A8 to A23 .
CLK1
TxD1
7116
A8 to
A15
RxD1
A16 to
A23
DQ6
RTS1(BUSY)
Figure 25-9. Timing for reading lock bit status
Lock Bit Enable Command
This command enables the lock bit in blocks whose bit has been disabled with the lock bit disable
command. It functions in the same way as the WP pin in the parallel I/O mode. The command code "7A16"
is sent in the first byte of the serial transmission. This command enables the lock bit function only; it does
not set the lock bit itself.
CLK1
TxD1
7A16
RxD1
RTS1(BUSY)
Figure 25-10. Timing for enabling the lock bit
252
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Lock Bit Disable Command
This command disables the lock bit. It functions in the same way as the WP pin in the parallel I/O mode.
The command code "7A16" is sent in the first byte of the serial transmission. This command enables the
lock bit function only; it does not set the lock bit itself. however, if an erase command is executed after
executing the lock bit disable command, "0" (locked) lock bit data will be set to "1" (unlocked) after the
erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled.
CLK1
TxD1
7516
RxD1
RTS1(BUSY)
Figure 25-11. Timing for disabling the lock bit
Download Command
This command downloads a program into the RAM for execution. Execute the download command as
explained below.
(1) Send the "FA16" command code in the first byte of the transmission.
(2) Send the program size in the second and the third bytes of the transmission.
(3) Send the check sum in the fourth byte of the transmission. The check sum is added to all the data
in the fifth byte onward.
(4) The program to execute is sent in the fifth byte onward.
When all the data are transmitted, if the check sum matches, the download program is executed.
The size of the program may vary according to the internal RAM.
CLK1
TxD1
Check
sum
FA16
Data size (low)
RxD1
Data size (high)
RTS1(BUSY)
Figure 25-12. Timing for download
253
Program
data
Program
data
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute the
version information output command as explained below.
(1) Send the "FB16" command code in the first byte of the transmission.
(2) The version information will be output from the second byte onward. These data are composed of
8 ASCII code characters.
CLK1
TxD1
FB16
RxD1
'V'
'E'
'R'
'X'
RTS1(BUSY)
Figure 25-13. Timing for version information output
Boot Area Output Command
This command outputs the control program stored in the boot area in one page blocks (256
bytes). Execute the boot area output command as explained below.
(1) Send the "FC16" command code in the first byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the second and the third bytes of the transmission
respectively.
(3) From the fourth byte onward, data (D0 – D7) for the page (256 bytes) specified with addresses A8
to A23 will be output sequentially from the smallest address first, in synchronization with the rise of
the clock.
CLK1
TxD1
FC16
A8 to
A15
A16 to
A23
data0
RxD1
RTS1(BUSY)
Figure 25-14. Timing for boot area output
254
data255
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
ID Check
This command checks the ID code. Execute the boot ID check command as explained below.
(1) Send the "F516" command code in the first byte of the transmission.
(2) Send addresses A0 to A7, A8 to A15 and A16 to A23 of the first byte of the ID code in the second, the
third and the fourth bytes of the transmission respectively.
(3) Send the number of data sets of the ID code in the fifth byte.
(4) The ID code is sent in the sixth byte onward, starting with the first byte of the code.
When all the data are transmitted, if the check sum matches, the download program is executed.
The size of the program may vary according to the internal RAM.
CLK1
TxD1
F516
DF16
FF16
0F16
ID size
ID1
ID7
RxD1
RTS1(BUSY)
Figure 25-15. Timing for ID check
ID Code
When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent from
the serial programmer is not accepted. An ID code contains 8 bits of data. Its area is, from the first byte,
0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the
flash memory, which already has the ID code set for these addresses.
Address
0FFFDF16 to 0FFFDC16
ID1 Undefined instruction vector
0FFFE316 to 0FFFE016
ID2 Overflow vector
0FFFE716 to 0FFFE416
BRK instruction vector
0FFFEB6 to 0FFFE816
ID3 Address match vector
0FFFEF16 to 0FFFEC16
ID4 Single step vector
0FFFF316 to 0FFFF016
ID5 Watchdog timer vector
0FFFF716 to 0FFFF416
ID6 DBC vector
0FFFFB16 to 0FFFF816
ID7
0FFFFF16 to 0FFFFC16
NMI vector
Reset
4 bytes
Figure 25-16. ID code storage addresses
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Data Protection (Block Lock)
Each of the blocks in Figure 24-1 has a nonvolatile lock bit that specifies protection (block lock) against
erasing/writing. A block is locked (writing "0" for the lock bit) with the lock bit program command. Also, the
lock bit of any block can be read with the read lock bit status command.
Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock
bit disable- and lock enable bit commands.
(1) After the reset is cancelled and the lock bit enable command executed, the specified block can be
locked/unlocked using the lock bit (lock bit data). Blocks with "0" lock bit data are locked and cannot
be erased or written in. On the other hand, blocks with "1" lock bit data are unlocked and can be
erased or written in.
(2) After the lock bit enable command is executed, all the blocks are unlocked regardless of lock bit data
status and can be erased or written in. In this case, lock bit data that were "0" before the block was
erased will be set to "1" (unlocked) after erasing, therefore the block is actually unlocked with the
lock bit.
0C000016
Block 6 : 64K byte
0D000016
Block 5 : 64K byte
0E000016
Block 4 : 64K byte
0F000016
0F800016
Type No.
Flash memory
start address
0FA00016
0C000016
0FFFFF16
M306N0FGTFP
0FC00016
Block 3 : 32K byte
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
User ROM area
Figure 25-17. Blocks in the user area
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 25-2 gives the definition of the status register bits. After clearing the reset, the status register outputs
"8016".
Table 25-2. Status register (SRD)
Definition
Each bit of
SRD
Status name
"1"
"0"
Ready
Busy
-
-
SR7 (bit7)
Write state machine (WSM) status
SR6 (bit6)
Reserved
SR5 (bit5)
Erase status
Terminated in error
Terminated normally
SR4 (bit4)
Program status
Terminated in error
Terminated normally
SR3 (bit3)
Block status after program
Terminated in error
Terminated normally
SR2 (bit2)
Reserved
-
-
SR1 (bit1)
Reserved
-
-
SR0 (bit0)
Reserved
-
-
Write State Machine (WSM) Status (SR7)
The write status machine (WSM) status indicates the operating status of the flash memory. When power
is turned on, it is set to "1" (ready). The bit is set to "0" (busy) during an auto write- or an auto erase
operation, but it is set back to "1" when the operation ends.
Erase Status (SR5)
The erase status reports the operating status of the auto erase operation. It is set to "1" if an erase error
occurs. When the erase status is cleared, it is set to "0".
Program Status (SR4)
The program status reports the operating status of the auto write operation. It is set to "1" if a write error
occurs. When the program status is cleared, it is set to "0".
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Program Status After Program (SR3)
If excessive data are written (phenomenon whereby the memory cell becomes depressed which results in
data not being read correctly), the block status after-program is set to "1" at the end of the page write
operation. In other words, when writing ends successfully, "8016" is output; when writing fails, "9016" is
output; and when excessive data are written, "8816" is output.
If "1" is written for any of SR5-, SR4- or SR3 bits, the page program-, block erase-, erase all unlocked
blocks- and lock bit program commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register.
Also in the following cases, both SR4 and SR5 are set to "1" (command sequence error).
(1) If data other than "D016" or "FF16" are input for the second bus cycle data of the lock bit
program command (7716/D016).
(2) If data other than "D016" or "FF16" are input for the second bus cycle data of the block erase
command (2016/D016).
(3) If data other than "D016" or "FF16" are input for the second bus cycle data of the erase all
unlocked blocks command (A716/D016). However, inputting "FF16" engages the read array
mode and cancels the setup command in the first bus cycle.
0C000016
Block 6 : 64K byte
0D000016
Block 5 : 64K byte
0E000016
Block 4 : 64K byte
0F000016
0F800016
Type No.
M306N0FGTFP
Flash memory
start address
0FA00016
0C000016
0FFFFF16
0FC00016
Block 3 : 32K byte
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
User ROM area
Figure 25-17. Blocks in the user area
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Preliminary Specifications REV.B
Mitsubishi microcomputers
M16C / 6N Group
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Status Register 1 (SRD1)
The status register 1 indicates status of serial communication, results of ID checks and those of check
sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also,
status register 1 is cleared by writing the clear status register command (5016).
Table 25-4 gives the definition of each status register bit. "0016" is output when power is turned on and the
flag status is maintained even after the reset.
Table 25-3. Status register 1 (SRD 1)
SRD1 bits
Status name
SR15 (bit7)
Definition
"1"
"0"
Boot update completed bit
-
-
SR14 (bit6)
Reserved
-
-
SR13 (bit5)
Reserved
-
-
SR12 (bit4)
Checksum match bit
Match
Mismatch
SR11 (bit3)
ID check completed bits
SR10 (bit2)
SR9 (bit1)
Data receive time out
SR8 (bit0)
Reserved
00
01
10
11
Not verified
Verification mismatch
Reserved
Verified
Time out
Normal operation
-
Block Update Completed Bit (SR15)
This flag indicates whether or not the control program was downloaded to the RAM, using the download
function.
Check Sum Consistency Bit (SR12)
This flag indicates whether or not the check sum matches when a program is downloaded for execution
using the download function.
ID Check Completed Bits (SR11 and SR 10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached during
data reception, the received data is discarded and the microcomputer returns to the command wait state.
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Full Status Check
Results of executed erase- and program operations can be known by running a full status check. Figure 2518 shows a flowchart of the full status check and explains how to remedy errors which may occur.
Read status register
YES
SR4=1 and SR5
=1 ?
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Command
sequence error
NO
SR5=0?
NO
Block erase error
Should a block erase error occur, the block in error
cannot be used.
YES
SR4=0?
NO
Program error (page
or lock bit)
NO
Program error
(block)
YES
SR3=0?
Execute the read lock bit status command (7116)
to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
YES
End (block erase, program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase,
erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (5016) before executing these commands.
Figure 25-18. Full status check flowchart and remedial procedure for errors
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
Example Circuit Application for The Standard Serial I/O Mode
The figure blow shows a circuit application for the standard serial I/O mode. Control pins may vary according to programmer, therefore see the programmer manual for more information.
CLK1
Clock input
RTS1(BUSY)
RTS1 output
Data input
RXD1
Data output
TXD1
M16C/62 Flash
memory
CNVss
NMI
P50(CE)
P55(EPM)
(1) Control pins and external circuitry will vary according to programmer. For
more information, see the programmer manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are
switched via a switch.
Figure 25-19. Example circuit application for the standard serial I/O mode
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Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard Serial I/O Mode
MITSUBISHI SEMICONDUCTORS
M16C/6N Group DATA SHEET REV.B
Second Edition March1999
Editioned by
Committee of editing of Mitsubishi Semiconductor DATA SHEET
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©1998 MITSUBISHI ELECTRIC CORPORATION
262