ON MC74HCT08ADR2G Quad 2-input and gate with lsttl compatible input Datasheet

MC74HCT08A
Quad 2-Input AND Gate
with LSTTL Compatible
Inputs
High−Performance Silicon−Gate CMOS
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The MC74HCT08A is identical in pinout to the LS08. The device
inputs are compatible with Standard CMOS or LSTTL outputs.
MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 V to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 24 FETs or 6 Equivalent Gates
These are Pb−Free Devices
14
PDIP−14
N SUFFIX
CASE 646
14
1
MC74HCT08AN
AWLYYWWG
1
14
SOIC−14
D SUFFIX
CASE 751A
14
1
HCT08AG
AWLYWW
1
A1
B1
A2
B2
A3
B3
A4
B4
1
3
2
14
Y1
6
5
1
Y2
1
Y = AB
9
8
10
12
11
13
HCT
08
ALYW G
G
TSSOP−14
DT SUFFIX
CASE 948G
14
4
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
Y3
Y4
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
Figure 1. Logic Diagram
Pinout: 14−Lead Packages (Top View)
VCC
B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
9
8
Output
A
B
Y
L
L
H
H
L
H
L
H
L
L
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
1
2
3
4
5
6
A1
B1
Y1
A2
B2
Y2
7
GND
Figure 2. Pinout
© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 8
1
Publication Order Number:
MC74HCT08A/D
MC74HCT08A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
−0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
PD
Power Dissipation in Still Air,
Tstg
Storage Temperature
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Plastic DIP†
SOIC Package†
TSSOP Package†
±50
mA
750
500
450
mW
−65 to +150
°C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
°C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating − Plastic DIP: − 10 mW/°C from 65°C to 125°C
SOIC Package: − 7 mW/°C from 65°C to 125°C
TSSOP Package: − 6.1 mW/°C from 65°C to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 3)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
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2
Min
Max
Unit
2.0
6.0
V
0
VCC
V
−55
+125
°C
0
0
0
1000
500
400
ns
MC74HCT08A
DC CHARACTERISTICS (Voltages Referenced to GND)
Parameter
Symbol
VCC
V
Condition
Guaranteed Limit
−55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High−Level Input Voltage
Vout = 0.1 V or VCC −0.1 V
|Iout| ≤ 20 mA
4.5 to
5.5
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input Voltage
Vout = 0.1 V or VCC − 0.1 V
|Iout| ≤ 20 mA
4.5 to
5.5
0.8
0.8
0.8
V
VOH
Minimum High−Level Output Voltage
Vin = VIH or VIL
|Iout| ≤ 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
4.5
3.98
3.84
3.70
VOL
Maximum Low−Level Output Voltage
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.40
Vin =VIH or VIL
|Iout| ≤ 4.0 mA
Vin = VIH or VIL
|Iout| ≤ 20mA
Vin = VIH or VIL
|Iout| ≤ 4.0 mA
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
5.5
1.0
10
40
mA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns, VCC = 5.0 V ± 10%)
VCC
V
Parameter
Symbol
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
Cin
tPLH
tPHL
Guaranteed Limit
−55 to 25°C
≤85°C
≤125°C
Unit
5.0
15
17
19
21
22
26
ns
5.0
15
19
22
ns
10
10
10
pF
Maximum Input Capacitance
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
20
Power Dissipation Capacitance (Per Buffer)*
*Used to determine the no−load dynamic power consumption: PD = CPD VCC
2f
pF
+ ICC VCC .
ORDERING INFORMATION
Package
Shipping†
MC74HCT08ANG
PDIP−14
(Pb−Free)
25 Units / Rail
MC74HCT08ADG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74HCT08ADR2G
SOIC−14
(Pb−Free)
Device
MC74HCT08ADTR2G
TSSOP−14*
MC74HCT08AFELG
SOEIAJ−14
(Pb−Free)
2500/Tape & Reel
2000/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74HCT08A
tr
tf
VCC
90%
INPUT
A OR B
(VI)
Vm
10%
GND
tPLH
VI = GND to 3.0 V
Vm = 1.3 V
tPHL
90%
Vm
10%
OUTPUT Y
tTLH
tTHL
Figure 3. Switching Waveforms
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL *
*Includes all probe and jig capacitance
Figure 4. Test Circuit
A
Y
B
Figure 5. Expanded Logic Diagram
(1/4 of the Device)
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4
MC74HCT08A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
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5
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
MC74HCT08A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HCT08A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
0.25 (0.010)
M
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
D 14 PL
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74HCT08A/D
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