ON NCP4354ADR2G Secondary side smps off mode controller Datasheet

NCP4353, NCP4354
Secondary Side SMPS OFF
Mode Controller for Low
Standby Power
The NCP4353/4 is a secondary side SMPS controller designed for
use in applications which require extremely low no load power
consumption. The device is capable of detecting “no load” conditions
and entering the power supply into a low consumption OFF mode.
During OFF mode, the primary side controller is turned off and energy
is provided by the output capacitors thus eliminating the power
consumption required to maintain regulation. During OFF mode, the
output voltage relaxes and is allowed to decrease to an adjustable
level. Once more energy is required, the NCP4353/4 automatically
restarts the primary side controller. The NCP4353/4 controls the
primary side controller with an “Active OFF” signal, meaning that it
drives optocoupler current during OFF mode to pull−down the FB pin
of the primary controller.
During normal power supply operation, the NCP4353/4 provides
integrated voltage feedback regulation, replacing the need for a shunt
regulator. The A versions include a current regulation loop in addition
to voltage regulation. Feedback control as well as ON/OFF signal can
be provided with only one optocoupler.
The NCP4354 includes a LED driver pin implemented with an open
drain MOSFET driven by a 1 kHz square wave with a 12.5% duty
cycle when primary side is in regulation for indication purpose.
The NCP4353 is available in TSOP−6 package while the NCP4354
is available in SOIC−8 package.
MARKING
DIAGRAMS
TSSOP−6
CASE 318G
1
XXXAYWG
G
1
8
XXXXX
ALYW G
G
SOIC−8
CASE 751
8
1
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Features
•
•
•
•
•
•
•
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Operating Input Voltage Range: 2.5 V to 36.0 V
Supply Current < 100 mA
±0.5% Reference Voltage Accuracy (TJ = 25°C)
Constant Voltage and Constant Current (A versions) Control Loop
Indication LED PWM Modulated Driver (NCP4354x)
Designed for use with NCP1246 Fixed Frequency PWM Controller
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
See detailed ordering, marking and shipping information in the
package dimensions section on page 15 of this data sheet.
Typical Applications
• Offline Adapters for Notebooks, Game Stations and Printers
• High Power AC−DC Converters for TVs, Set−Top Boxes, Monitors, etc.
DEVICE OPTIONS
NCP4353A
NCP4353B
NCP4354A
NCP4354B
Adjustable
Vmin
No
Yes
Yes
Yes
Current
Regulation
Yes
No
Yes
No
LED Driver
No
No
Yes
Yes
Package
TSOP−6
TSOP−6
SOIC−8
SOIC−8
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 4
1
Publication Order Number:
NCP4353/D
NCP4353, NCP4354
Current
Regulation
VCC
Sink only
VCC
management
IBIASV
Power
RESET
VDD
ISNS
OTA
VREFC
SW3
VDD
VREF
DRIVE
Sink only
Voltage
Regulation
Power
RESET
VSNS
OTA
VREF
0.9 x VREF
IDRIVEOFF
IBIASV
Enabling
SW1
Q
S
Q
R
Off Mode
Detection
VCC
10%VCC
OFFDET
GND
Power RESET
NCP4353A
VCC
VCC
management
IBIASV
Power
RESET
VDD
SW3
VDD
VREF
DRIVE
Sink only
Voltage
Regulation
Power
RESET
VSNS
OTA
VREF
0.9 x VREF
I DRIVEOFF
IBIASV
Enabling
SW1
Q
S
Q
R
Off Mode
Detection
VCC
10%VCC
OFFDET
VMIN
GND
Power RESET
Min Output
Voltage
VREFM
NCP4353B
Figure 1. Simplified Block Diagrams NCP4353A and NCP4353B
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2
NCP4353, NCP4354
Current
Regulation
VCC
V CC
management
IBIASV
Power
RESET
VDD
ISNS
OTA
Sink only
VREFC
SW3
VDD
VREF
DRIVE
Voltage
Regulation
Power
RESET
VSNS
OTA
Sink only
VREF
0.9 x VREF
IDRIVEOFF
IBIASV
Enabling
SW1
Q
S
Q
R
Off Mode
Detection
VCC
10%VCC
LED
OFFDET
SW2
1 kHz, 12% D.C.
Oscillator
VMIN
GND
Power RESET
Min Output
Voltage
VREFM
NCP4354A
VCC
VCC
management
I BIASV
Power
RESET
SW3
VDD
V DD
VREF
FBC
Sink only
Voltage
Regulation
Power
RESET
ON/OFF
VSNS
OTA
VREF
0.9 x VREF
I DRIVEOFF
IBIASV
Enabling
SW1
Q
S
Q
R
Off Mode
Detection
VCC
10%VCC
LED
OFFDET
SW2
1 kHz, 12% D.C.
Oscillator
VMIN
GND
Power RESET
Min Output
Voltage
VREFM
NCP4354B
Figure 2. Simplified Block Diagrams NCP4354A and NCP4354B
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3
NCP4353, NCP4354
PIN FUNCTION DESCRIPTION
NCP4353A
NCP4353B
NCP4354A
NCP4354B
Pin Name
1
1
8
8
VCC
Supply voltage pin
Description
2
2
7
7
GND
Ground
6
6
1
1
VSNS
Output voltage sensing pin, connected to output
voltage divider
5
5
2
2
OFFDET
OFF mode detection input. Voltage divider provides adjustable off mode detection threshold
−
4
3
3
VMIN
Minimum output voltage adjustment
4
−
4
−
ISNS
Current sensing input for output current regulation,
connect it to shunt resistor in ground branch.
−
−
5
4
LED
PWM LED driver output. Connected to LED cathode with current define by external serial resistance
−
−
−
6
FBC
Output of current sinking OTA amplifier or amplifiers driving feedback optocoupler’s LED. Connect
here compensation network (networks) as well.
−
−
−
5
ON/OFF
OFF mode current sink. This output keeps primary
control pin at low level in off mode.
3
3
6
−
DRIVE
Combination of FBC and ON/OFF pins
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
−0.3 to 40
V
VDRIVE, VONOFF,
VFBC, VLED
−0.3 to VCC + 0.3
V
VSNS, VISNS,
VOFFDET, VMIN
−0.3 to 10
V
ILED
10
mA
RqJA
315
324
260
277
°C/W
Junction Temperature
TJ
−40 to 150
°C
Storage Temperature
TSTG
−60 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
250
V
ESD Capability, Charged Device Model (Note 2)
ESDCDM
1000
V
Input Voltage
DRIVE, ON/OFF, FBC, LED Voltage
VSNS, ISNS, OFFDET, VMIN Voltage
LED Current
Thermal Resistance − Junction−to−Air (Note 1)
NCP4353A
NCP4353B
NCP4354A
NCP4354B
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. 50 mm2, 1.0 oz. Copper spreader.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JESD22−A114F
ESD Machine Model tested per JESD22−A115C
ESD Charged Device Model tested per JESD22−C101F
Latchup Current Maximum Rating tested per JEDEC standard: JESD78D.
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NCP4353, NCP4354
ELECTRICAL CHARACTERISTICS
0°C ≤ TJ ≤ 125°C; VCC = 15 V; unless otherwise noted. Typical values are at TJ = +25°C.
Parameter
Test Conditions
Symbol
Maximum Operating Input Voltage
Min
Typ
VCC
VCC UVLO
VCCUVLO
VCC rising
VCC falling
VCC UVLO Hysteresis
VCCUVLOHYS
Quiescent Current in Regulation
Quiescent Current in OFF Mode
Unit
36.0
V
V
3.3
3.5
3.7
2.3
2.5
2.7
0.8
1.0
ICC
NCP4353A
Max
V
101
125
NCP4353B
82
105
NCP4354A
118
145
NCP4354B
95
120
110
VSNS < 1.12 V
ICC,OFFmode
90
Transconductance
Sink current only
gmV
1
Reference Voltage
2.8 V ≤ VCC ≤ 36.0 V, TJ = 25°C
VREF
mA
mA
VOLTAGE CONTROL LOOP OTA
2.8 V ≤ VCC ≤ 36.0 V, TJ = 0 − 85°C
2.8 V ≤ VCC ≤ 36.0 V, TJ = 0 − 125°C
Sink Current Capability
In regulation, VDRIVE or VFBC > 1.5 V
ISINKV
In OFF mode, VDRIVE or VFBC > 1.5 V
Inverting Input Bias Current
In regulation, VSNS = VREF
In OFF mode, VSNS > 1.12 V
Inverting Input Bias Current
Threshold
In OFF mode
1.244
1.250
1.256
1.240
1.250
1.264
1.230
1.250
1.270
2.5
1.2
IBIASV
VSNSBIASTH
S
V
mA
1.5
−100
2.0
mA
100
nA
−13
−11
−10
mA
1.07
1.12
1.17
V
CURRENT CONTROL LOOP OTA (NCP435xA only)
Sink current only
Transconductance
gmC
Reference Voltage
Sink Current Capability
Inverting Input Bias Current
3
VREFC
60
VDRIVE or VFBC > 1.5 V
ISINKC
2.5
ISNS = VREFC
IBIASC
−100
VREFM
355
62.5
S
65
mV
mA
100
nA
400
mV
MINIMUM VOLTAGE COMPARATOR (except NCP4353A)
Threshold Voltage
Hysteresis
Output change from logic high to logic low
377
VMINH
40
mV
VOFFDETTH
10% VCC
V
OFF MODE DETECTION COMPARATOR
Threshold Value
2.5 V ≤ VCC ≤ 36.0 V
VCC = 15 V
Hysteresis
1.47
Output change from logic high to logic low
1.50
1.53
VOFFDETH
40
mV
fSWLED
1
kHz
LED DRIVER (NCP4354x only)
Switching Frequency
Duty Cycle
Switch Resistance
DLED
ILED = 5 mA
RSW2
In OFF mode, VDRIVE or VONOFF > 0.6 V
IDRIVEOFF
10.0
12.5
15.0
%
W
50
OFF MODE CONTROL
Sink Current
140
160
180
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCP4353, NCP4354
1.29
1.28
1.28
1.27
1.27
1.26
1.25
1.25
1.24
1.23
1.23
1.22
−20
0
20
40
60
80
100
120
0
24
Figure 4. VREF at TJ = 255C
63
62.9
62.8
62.8
62.7
62.7
62.6
62.5
62.4
62.2
62.1
62.1
40
60
80
100
62
120
0
6
12
18
24
TJ, JUNCTION TEMPERATURE (°C)
VCC (V)
Figure 5. VREFC at VCC = 15 V
Figure 6. VREFC at TJ = 255C
410
410
400
400
390
390
380
370
360
30
36
30
36
62.4
62.3
20
36
62.5
62.2
0
30
62.6
62.3
350
−40
18
Figure 3. VREF at VCC = 15 V
63
−20
12
VCC (V)
62.9
62
−40
6
TJ, JUNCTION TEMPERATURE (°C)
VREFC (mV)
VREFC (mV)
1.26
1.24
1.22
−40
VREFM (mV)
VREF (V)
1.29
VREFM (mV)
VREF (V)
TYPICAL CHARACTERISTICS
380
370
360
−20
0
20
40
60
80
100
350
120
0
6
12
18
24
TJ, JUNCTION TEMPERATURE (°C)
VCC (V)
Figure 7. VREFM at VCC = 15 V
Figure 8. VREFM at TJ = 25 5C
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NCP4353, NCP4354
TYPICAL CHARACTERISTICS
3.8
1.53
3.6
VCCUVLO_R
1.52
VOFFDETTH (V)
VCC (V)
3.4
3.2
3.0
2.8
2.6
2.4
−40
1.50
1.49
1.48
VCCUVLO_F
−20
1.51
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
1.47
−40
120
Figure 9. VCCUVLO
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
120
Figure 10. VOFFDETTH at VCC = 15 V
175
−10
170
−10.2
−10.4
165
IBIASV (mA)
IONOFF (mA)
−10.6
160
155
150
−10.8
−11
−11.2
−11.4
145
−11.6
140
135
−40
−11.8
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
−12
−40
120
150
150
140
140
130
130
120
120
120
110
110
100
100
90
−40
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. IBIASV at VCC = 15 V, VSNS >
VSNSBIASTH
ICC (mA)
ICC (mA)
Figure 11. IONOFF at VCC = 15 V
−20
90
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
120
0
Figure 13. ICC in Regulation at VCC = 15 V for
NCP4354A
6
12
18
VCC (V)
24
30
Figure 14. ICC in Regulation at TJ = 255C for
NCP4354A
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36
NCP4353, NCP4354
120
120
115
115
110
110
105
105
ICC_OFFmode (mA)
ICC_OFFmode (mA)
TYPICAL CHARACTERISTICS
100
95
90
85
100
95
90
85
80
80
75
75
70
−40
70
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
0
120
120
120
115
115
110
110
105
105
100
100
95
90
80
80
75
75
30
36
70
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
120
0
Figure 17. ICC in Regulation at VCC = 15 V for
NCP4354B
6
12
18
VCC (V)
24
30
36
Figure 18. ICC in Regulation at TJ = 255C for
NCP4354B
120
120
115
115
110
110
105
105
ICC_OFFmode (mA)
ICC_OFFmode (mA)
24
90
85
100
95
90
85
100
95
90
85
80
80
75
75
70
−40
18
VCC (V)
95
85
70
−40
12
Figure 16. ICC in OFF Mode at TJ = 255C,
VSNS < VSNSBIASTH, for NCP4354A
ICC (mA)
ICC (mA)
Figure 15. ICC in OFF Mode at VCC = 15 V,
VSNS < VSNSBIASTH, for NCP4354A
6
70
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
120
0
Figure 19. ICC in OFF Mode at VCC = 15 V,
VSNS < VSNSBIASTH, for NCP4354B
6
12
18
VCC (V)
24
30
Figure 20. ICC in OFF Mode at TJ = 255C,
VSNS < VSNSBIASTH, for NCP4354B
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36
NCP4353, NCP4354
TYPICAL CHARACTERISTICS
3.5
2.0
3.4
3.3
1.9
1.8
3.1
ISINKV (mA)
ISINKV (mA)
3.2
3.0
2.9
2.8
1.7
1.6
1.5
1.4
2.7
1.3
2.6
2.5
−40
−20
0
20
40
60
80
100
1.2
−40
120
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Voltage OTA Current Sink
Capability in Regulation
Figure 22. Voltage OTA Current Sink
Capability in OFF Mode
3.5
1.40
3.4
3.3
1.30
fSWLED (kHz)
3.2
3.1
3.0
2.9
2.8
2.7
120
1.20
1.10
1.00
0.90
2.6
2.5
−40
−20
0
20
40
60
80
100
0.80
−40
120
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. Current OTA Current Sink
Capability
Figure 24. LED Switching Frequency at
VCC = 15 V
100
90
80
RSW2 (W)
ISINKC (mA)
−20
TJ, JUNCTION TEMPERATURE (°C)
70
60
50
40
30
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. RSW2 at VCC = 15 V
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120
120
NCP4353, NCP4354
APPLICATION INFORMATION
VOUT
A typical application circuit for NCP435x series is shown
in Figure 28, done with an imaginary IC with all features in
one. Pin functions are available in pin description table.
Simplified typical application circuit for NCP4353B that
shows only available features in this IC is shown in
Figure 27. Figure 29 shows possible connection of the
NCP4353B to flyback primary controller.
IC will be derived in multiple versions with different
features for each of them.
VOUT
R4
R7
R4
VMIN
VSNS
R5
R5
R7
VMIN
VSNS
Power Supply
R6
The NCP435x is designed to operate from a single supply
up to 36 V. It starts to operate when VCC voltage reaches
3.5 V and stops when VCC voltage drops below 2.5 V. VCC
can be supplied by direct connection to the VOUT voltage
of the power supply. It is highly recommended to add a RC
filter (R1 and C3) in series from VOUT to VCC pin to reduce
voltage spikes and drops that are produced at the converter’s
output capacitors. Recommended values for this filter are
220 W and 1 mF.
TYPE 1
Current Regulation Path (A versions only)
The output current is sensed by the shunt resistor R12 in
series with the load. Voltage drop on R12 is compared with
internal precise voltage reference VREFC at ISNS
transconductance amplifier input.
Voltage difference is amplified by gmC to output current
of amplifier, connected to FBC or DRIVE pin.
Compensation network is connected between this pin and
ISNS input to provide frequency compensation for current
regulation path. Resistor R13 separates compensation
network from sense resistor. Compensation network works
into low impedance without this resistor that significantly
decreases compensation network impact.
Current regulation point is set to current given by
Equation 4.
The output voltage is detected on the VSNS pin by the R4,
R5 and R6 voltage divider. This voltage is compared with
the internal precise voltage reference. The voltage
difference is amplified by gmV of the transconductance
amplifier. The amplifier output current is connected to the
FBC or DRIVE pin. The compensation network is also
connected to this pin to provide frequency compensation for
the voltage regulation path. This FBC (DRIVE) pin drives
regulation optocoupler that provides regulation of primary
side. The optocoupler is supplied via direct connection to
VOUT line through resistor R2.
Regulation information is transferred through the
optocoupler to the primary side controller where its FB pin
is usually pulled down to reduce energy transferred to
secondary output.
The VSNS voltage divider is shared with VMIN voltage
divider. The shared voltage divider can be connected in two
ways as shown in Figure 26. The divider type is selected
based on the ratio between VMIN and VOUT. When the
condition of Equation 1 is true, divider type 1 should be
used.
V OUT
V REFM
V REF
I OUTLIM +
R4 ) R5 ) R6
R5 ) R6
R4 ) R5 ) R6
R6
R12
(eq. 4)
OFF mode operation is advantageous for ultra low or zero
output current condition. The very long off time and the ultra
low power mode of the whole regulation system greatly
reduces the overall consumption.
The output voltage is varying between nominal and
minimal in OFF mode. When output voltage decreases
below set (except NCP4353A) minimum level, primary
controller is switched on until output capacitor C1 is charged
again to the nominal voltage.
The OFF mode detection is based on comparison of output
voltage and voltage loaded with fixed resistances (D2, C2,
R8 and R9). Figure 30 shows detection waveforms. When
output voltage is loaded with very low current, primary
controller goes into skip mode (primary controller stops
switching for some time). While output capacitor C1 is
discharged very slowly (no load condition), the capacitor C2
(eq. 1)
(eq. 2)
and for type 2 by Equation 3.
V OUT + V REF
V REFC
OFF Mode Detection
Output voltage for divider type 1 can be computed by
Equation 2
V OUT + V REF
TYPE 2
Figure 26. Shared Dividers Type
Voltage Regulation Path
V MIN u
R6
(eq. 3)
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NCP4353, NCP4354
PWM modulation is used to increase efficiency of LED.
over UVLO level (3), primary controller starts to operate.
VCC capacitor is charged above DSS level from auxiliary
winding, VOUT is slowly rising according to primary
controller start up ramp to nominal voltage (4).
Primary FB pin voltage is above regulation range until
VOUT is at set level. Once VOUT is at set level, the secondary
controller starts to sink current from optocoupler LED’s and
primary FB voltage is stabilized in regulation region. With
nominal output power (without skip mode) OFFDET pin
voltage is higher than VOFFDETTH (typically 10% of VCC).
After some time, the load current decreases to low level
(5) and primary convertor uses skip mode (6) to keep
regulation of output voltage at set level. The skip mode
consists of few switching cycles followed by missing ones
to provide limited energy by light load. The number of
missing cycles allows regulation for any output power.
While both C1 and C2 are discharged during the missing
cycles, C2 discharge will be faster than C1 without output
current, VOFFDET drops below VOFFDETTH and OFF mode
is detected (7). This situation is shown in Figure 30 in detail.
When OFF mode is detected, internal pull−up current
IBIASV is switch on (7), VSNS voltage increases (due to
IBIASV) and voltage amplifier sinks full current to keep
primary FB voltage below skip level until OFF mode is
detected by the primary side controller (8). Current into
ONOFF pin or DRIVE pin begins to flow at the same time,
when entering into OFF mode (7). When OFF mode is
detected by primary side controller (8a), primary FB
injected current decreases to a lower level to reduce overall
power consumption. Optocoupler current, can also be
reduced from that time to keep the level below restart level.
Secondary side controller decreases optocoupler current
(voltage transconductance amplifier stops to sink current)
when VSNS voltage drops below VREF (9) and IBIASV is
also switch off when VSNS is lower than 90% of VREF to
reduce overall consumption. This point is defined by IBIASV
current, R6, R4 and R5 resistors and discharging time of
output capacitor C1. Discharging of C1 continues (10) until
output voltage drops below level set by voltage divider at
VMIN pin (except NCP4353A where minimum VOUT is
defined only by VCC UVLO) (11). ONOFF current stops
and thanks to internal pull−up, the primary FB voltage rises
above restart level (12) and primary controller starts
switching (13). Output capacitor C1 is recharged (14) to set
voltage. If there is still light load condition primary
controller goes to skip mode (15) again and after some time
secondary controller detects OFF mode by very light or no
load condition (16) and whole cycle is repeated.
Operation in OFF Mode Description
Fast Restart From OFF Mode
is discharged through a fixed load, by R8 and R9 faster than
output voltage on C1.
Once OFFDET pin voltage is lower than VOFFDETTH (this
threshold is derived from VOUT), OFF mode is detected. In
OFF mode SW1 is switched on to allow IDRIVEOFF current,
going through ON/OFF pin (NCP4354B) or DRIVE pin, to
keep switch off primary controller.
A higher sink current on primary FB pin is needed to keep
primary controller FB below the skip level until the OFF
mode is detected on primary side.
Despite output voltage on C1 may go down, the current
IBIASV injected into VSNS pin provides the requested offset
(VSNS voltage is higher than VREF). Primary IC should
detect OFF mode before VSNS is lower than 90% of VREF
while IBIASV is switched off to reduce consumption.
This offset, defined by R7 and the internal current source,
should be large enough to secure off mode detection of the
primary controller and avoid restart when VSNS < VREF.
Minimum Output Voltage Detection (Except
NCP4353A)
Minimum output voltage level defines primary controller
restart from OFF mode. It can be set by shared voltage
divider with voltage regulation loop. When VMIN voltage
drops below VREFM, OFF mode is ended and primary
controller restarts.
Minimum voltage level is given by Equation 5 for divider
type 1
V MIN + V REF
R4 ) R5 ) R6
R6
(eq. 5)
and for type 2 by Equation 6.
V MIN + V REF
R4 ) R5 ) R6
R5 ) R6
(eq. 6)
NCP4353A has no external adjustment and uses the
internal minimum voltage level specified by minimum
falling operation supply voltage.
LED Driver (NCP4354x only)
LED driver is active when VCC is higher than VCCMIN
and output voltage is in regulation (driver is off in OFF
mode). LED driver consists of an internal power switch
controlled by a PWM modulated logic signal and an external
current limiting resistor R3. LED current can be computed
by Equation 7.
I LED +
V OUT * V F_LED
R3
(eq. 7)
The IC ends OFF mode when a load is connected to the
output and VOUT is discharged to VMIN level. There exists
another connection that allows transition to normal mode
faster without waiting some time for VOUT to discharge to
VMIN. This schematic is shown at Figure 32. The basic idea
is that C3 is discharged by the IC faster than C1 by output
Operation waveforms in off mode and transition into OFF
mode with NCP1246 primary controller are shown in
Figure 31.
Figure shows waveforms from the first start (1) of the
convertor. At first, primary controller’s DSS charges VCC
capacitor over the UVLO level (2). When primary VCC is
www.onsemi.com
11
NCP4353, NCP4354
load in OFF mode. When an output load is applied, capacitor
C1 is discharged faster and this creates a voltage drop at D8.
When there is enough voltage at D8, T2 is opened and
current is injected into the OFFDET divider through R17.
OFFDET voltage higher than 10% of VCC ends OFF mode
and ON/OFF current stops. Primary controller leaves OFF
mode because voltage at its FB pin rises above OFF mode
end level and switching resumes.
Normal operation waveforms for typical load detection
connection and improved load detection waveforms are
shown in Figure 33.
OFF Supply
D2
D1
C1
R1
C2
VOUT
R4
VCC
C3
VCC
management
IBIASV
Power
RESET
C4
VDD
R10
SW3
VDD
VREF
R7
Feedback
&
ON / OFF
Opto
Sink only
DRIVE
R2
OTA
VSNS
Voltage
Regulation
Power
RESET
VREF
R8
R5
0.9 x VREF
IDRIVEOFF
IBIASV
Enabling
SW1
Q
S
Q
R
VCC
Off Mode
Detection
10%VCC
OFFDET
VMIN
GND
Power RESET
R6
VREFM
Min Output
Voltage
R9
Figure 27. Typical Application Schematic for NCP4353B
OFF Supply
D2
D1
C1
C2
R1
VOUT
R4
Current
Regulation
VCC
ISNS
OTA
Sink only
C3
VCC
management
C5
R11
Feedback
&
ON / OFF
Opto
IBIASV
Power
RESET
C4
VDD
R10
SW3
VDD
R12
VREF
R7
Sink only
FBC
R2
OTA
Voltage
Regulation
Power
RESET
ON/OFF
IBIASV
Enabling
SW1
R3
VSNS
VREF
R8
R5
0.9 x VREF
IDRIVEOFF
ON / OFF
LED
R13
VREFC
Q
S
Q
R
Off Mode
Detection
VCC
10%VCC
OFFDET
LED
SW2
1 kHz, 12% D.C.
Oscillator
VMIN
GND
Power RESET
Min Output
Voltage
VREFM
Figure 28. Typical Application Schematic for All Features
www.onsemi.com
12
R6
R9
NCP4353, NCP4354
D3
VCC
D2
D1
VIN
D4
~
C1
C6
R1
C2
D5
VOUT
R4
R10 C4
C3
D6
DRIVE
R14
OPTO1
D7
HV
DRV
VCC
R8
R6
R9
OFFDET
CS
GND
R15
C7
R5
T1
VCC
VCC
VMIN
R2
FB
NCP4353B
VSNS
R7
GND
C8
Figure 29. Typical Application Schematic for NCP4353B with Flyback
Primary
Controller
Activity
Normal operation
Skip
Off mode
Very low or no load detected,
off mode activated
VOFFDET
10% VOUT(VCC)
IOUT
Figure 30. OFF Mode Detection
www.onsemi.com
13
NCP4353, NCP4354
Figure 31. Typical Application States and Waveforms in OFF Mode with NCP1246 Primary Controller
D2
D1
R16
C1
D8
C2
VOUT
R4
T2
R10 C4
C3
VCC
FBC
VMIN
R8
R2
ON/OFF
OPTO1
R5
OFFDET
LED
LED1
R7
R3
VSNS
GND
R17
NCP4354B
R6
Figure 32. Improved Load Detection Connection
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14
R9
NCP4353, NCP4354
Figure 33. Typical and Improved Load Detection Comparison Waveforms
ORDERING INFORMATION
Marking
Adjustable
Vmin
Current
Regulation
LED
Driver
NCP4353ASNT1G
A53
No
Yes
NCP4353BSNT1G
B53
Yes
NCP4354ADR2G
NCP4354A
NCP4354BDR2G
NCP4354B
Device
Package
Shipping†
No
TSOP−6
(Pb−Free)
3000 / Tape & Reel
No
No
TSOP−6
(Pb−Free)
3000 / Tape & Reel
Yes
Yes
Yes
SOIC−8
(Pb−Free)
2500 / Tape & Reel
Yes
No
Yes
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
15
NCP4353, NCP4354
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE U
D
H
ÉÉÉ
ÉÉÉ
6
E1
1
NOTE 5
5
2
4
L2
GAUGE
PLANE
E
3
L
M
b
A1
SEATING
PLANE
DETAIL Z
e
0.05
C
A
c
DETAIL Z
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
−
0°
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
3.20
0.95
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
16
10°
NCP4353, NCP4354
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
S
J
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP4353/D