AD ADSP-2189MKST-300 Dsp microcomputer Datasheet

a
FEATURES
PERFORMANCE
13.3 ns Instruction Cycle Time @ 2.5 Volts (Internal),
75 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 200 CLKIN Cycle Recovery
from Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible (Easy to Use Algebraic Syntax), with Instruction Set Extensions
192K Bytes of On-Chip RAM, Configured as 32K Words
On-Chip Program Memory RAM and 48K Words OnChip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
SYSTEM INTERFACE
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
All Inputs Tolerate Up to 3.6 V, Regardless of Mode
16-Bit Internal DMA Port for High Speed Access to OnChip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait-State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
DSP Microcomputer
ADSP-2189M
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
MEMORY
DATA ADDRESS
GENERATORS
PROGRAM
SEQUENCER
DAG 1 DAG 2
PROGRAM
MEMORY
32K 3
24 BIT
DATA
MEMORY
48K 3
16 BIT
FULL MEMORY
MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
ADSP-2100 BASE
ARCHITECTURE
TIMER
INTERNAL
DMA
PORT
HOST MODE
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
GENERAL DESCRIPTION
The ADSP-2189M is a single-chip microcomputer optimized
for digital signal processing (DSP) and other high speed numeric processing applications.
The ADSP-2189M combines the ADSP-2100 family base architecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and data
memory.
The ADSP-2189M integrates 192K bytes of on-chip memory
configured as 32K words (24-bit) of program RAM and 48K
words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable
equipment. The ADSP-2189M is available in a 100-lead LQFP
package.
In addition, the ADSP-2189M supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking, for increased flexibility.
ICE-Port is a trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADSP-2189M
The EZ-ICE performs a full range of functions, including:
Fabricated in a high speed, low power, CMOS process, the
ADSP-2189M operates with a 13.3 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
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The ADSP-2189M’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSP-2189M can:
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Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
This takes place while the processor continues to:
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In-target operation
Up to 20 breakpoints
Single-step or full-speed operation
Registers and memory values can be examined and altered
PC upload and download functions
Instruction-level emulation of program booting and execution
Complete assembly and disassembly of instructions
C source-level debugging
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal DMA port
Receive and/or transmit data through the byte DMA port
Decrement timer
Additional Information
This data sheet provides a general overview of ADSP-2189M
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development Tools Data Sheet.
DEVELOPMENT SYSTEM
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports the ADSP-2189M. The System Builder provides a high
level method for defining the architecture of systems under
development. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to
display different portions of the hardware environment.
ARCHITECTURE OVERVIEW
The ADSP-2189M instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single processor cycle. The ADSP-2189M assembly language uses an
algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.
A PROM Splitter generates PROM programmer compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-2189M assembly source
code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.
POWER-DOWN
CONTROL
MEMORY
DATA ADDRESS
GENERATORS
PROGRAM
SEQUENCER
DAG 1 DAG 2
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x-based evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-218x EZ-KIT Lite is a low cost, easy to use hardware platform on which you can quickly get started with your
DSP software design. The EZ-KIT Lite includes the following
features:
PROGRAM
MEMORY
32K 3
24 BIT
DATA
MEMORY
48K 3
16 BIT
FULL MEMORY
MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
• 33 MHz ADSP-218x
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort®
Codec
• RS-232 Interface to PC with Windows 3.1 Control Software
• EZ-ICE Connector for Emulator Control
• DSP Demo Programs
MAC
SHIFTER
SERIAL PORTS
TIMER
SPORT 0 SPORT 1
ADSP-2100 BASE
ARCHITECTURE
INTERNAL
DMA
PORT
HOST MODE
Figure 1. Functional Block Diagram
Figure 1 is an overall block diagram of the ADSP-2189M. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with 40
bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations.
The ADSP-218x EZ-ICE® Emulator aids in the hardware debugging of an ADSP-2189M system. The emulator consists of
hardware, host computer resident software and the target board
connector. The ADSP-2189M integrates on-chip emulation
support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICEs. The ADSP-2189M device need not be removed from the target system when using the EZ-ICE, nor are
any adapters needed. Due to the small footprint of the EZ-ICE
connector, emulation can be supported in final board designs.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
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ADSP-2189M
RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2189M executes looped
code with zero overhead; no explicit jump instructions are required to maintain loops.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2189M provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycles, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
Efficient data transfer is achieved with the use of five internal
buses:
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•
•
The ADSP-2189M incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
Here is a brief list of the capabilities of the ADSP-2189M
SPORTs. For additional information on Serial Ports, refer to
the ADSP-2100 Family User’s Manual, Third Edition.
• SPORTs are bidirectional and have a separate, double-buffered transmit and receive section.
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
Program memory can store both instructions and data, permitting the ADSP-2189M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2189M can fetch an operand from program memory and
the next instruction in the same cycle.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
In lieu of the address and data bus for external memory connection, the ADSP-2189M may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with programmable wait-state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH and BG). One execution mode (Go Mode) allows the
ADSP-2189M to continue running from on-chip memory.
Normal execution mode requires the processor to halt while
buses are granted.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this configuration.
PIN DESCRIPTIONS
The ADSP-2189M will be available in a 100-lead LQFP package. In order to maintain maximum functionality and reduce
package size and pin count, some serial port, programmable
flag, interrupt and external bus pins have dual, multiplexed
functionality. The external bus pins are configured during
RESET only, while serial port pins are software configurable
during program execution. Flag and interrupt functionality is
retained concurrently on multiplexed pins. In cases where pin
The ADSP-2189M can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two levelsensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
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ADSP-2189M
NOTES
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices,
or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.
functionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics.
Common-Mode Pins
Pin
Name(s)
# of
Pins I/O Function
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2
1
1
1
1
1
1
1
1
1
1
1
1
PF7
IRQL0
PF6
IRQL1
PF5
IRQE
PF4
Mode D
1
1
1
1
PF3
Mode C
1
I
I/O
1
PF1
Mode A
I/O
I
I/O
I
I/O
I
I/O
I
I/O
PF2
Mode B
I
I
O
O
O
O
O
O
O
O
O
I
I
I/O
1
PF0
I
I/O
CLKIN, XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0, FI, FO
2
1
5
5
I
O
I/O
I/O
PWD
PWDACK
FL0, FL1, FL2
VDDINT
VDDEXT
1
1
3
2
4
I
O
O
I
I
GND
EZ-Port
10
9
I
I/O
Memory Interface Pins
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt
Requests1
Programmable I/O Pin.
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests1
Programmable I/O Pin
Mode Select Input—Checked Only
During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked Only
During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked Only
During RESET
Programmable I/O Pin During
Normal Operation
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out2
Power-Down Control Input
Power-Down Control Output
Output Flags
Internal VDD (2.5 V) Power
External VDD (2.5 V or 3.3 V)
Power
Ground
For Emulation Use
The ADSP-2189M processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running.
Full Memory Mode Pins (Mode C = 0)
Pin
Name
# of
Pins
I/O
Function
A13:0
14
O
D23:0
24
I/O
Address Output Pins for Program,
Data, Byte and I/O Spaces
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses.)
Host Mode Pins (Mode C = 1)
Pin
Name
# of
Pins
I/O
Function
IAD15:0
A0
16
1
I/O
O
D23:8
16
I/O
IWR
IRD
IAL
IS
IACK
1
1
1
1
1
I
I
I
I
O
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data, or Byte Access1
Data I/O Pins for Program, Data
Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configurable in Mode D; Open Drain
NOTE
1
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2189M provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the
PF7:4 pins). In addition, SPORT1 may be reconfigured for
IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six
external interrupts. The ADSP-2189M also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable
(except power-down and reset). The IRQ2, IRQ0 and IRQ1
input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edgesensitive. The priorities and vector addresses of all interrupts are
shown in Table I.
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REV. 0
ADSP-2189M
Third Edition, “System Interface” chapter, for detailed information about the power-down feature.
Table I. Interrupt Priority and Interrupt Vector Addresses
Source Of Interrupt
Interrupt Vector
Address (Hex)
RESET (or Power-Up with PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
• Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
• Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
200 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start
or stabilize) and letting the oscillator run to allow 200 CLKIN
cycle start up.
• Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit. Interrupt
support allows an unlimited number of instructions to be
executed before optionally powering down. The power-down
interrupt also can be used as a nonmaskable, edge-sensitive
interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
The ADSP-2189M masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the IMASK
register. This does not affect serial port autobuffering or DMA
transfers.
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin indicates when the processor
has entered power-down.
The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop and subroutine
nesting. The following instructions allow global enable or disable servicing of the interrupts (including power-down), regardless of the state of IMASK. Disabling the interrupts does not
affect serial port autobuffering or DMA.
Idle
When the ADSP-2189M is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals
still occur.
Slow Idle
The IDLE instruction is enhanced on the ADSP-2189M to let
the processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction.
ENA INTS;
DIS INTS;
The format of the instruction is:
When the processor is reset, interrupt servicing is enabled.
where n = 16, 32, 64 or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
IDLE (n);
LOW POWER OPERATION
The ADSP-2189M has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2189M will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The ADSP-2189M processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of powerdown features. Refer to the ADSP-2100 Family User’s Manual,
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When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
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ADSP-2189M
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
Clock Signals
The ADSP-2189M can be clocked by either a crystal or a TTLcompatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition for detailed
information on this power-down feature.
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-2189M, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories (mode
selectable). Programmable Wait-State generation allows the
processor connects easily to slow peripheral devices. The
ADSP-2189M also provides four external interrupts and two
serial ports or six external interrupts and one serial port. Host
Memory Mode allows access to the full external data bus, but
limits addressing to a single address bit (A0). Additional system
peripherals can be added in this mode through the use of external hardware to generate and latch address signals.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is connected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2189M uses an input clock with a frequency equal
to half the instruction rate; a 37.50 MHz input clock yields a
15 ns processor cycle (which is equivalent to 77 MHz). Normally, instructions are executed in a single processor cycle. All
device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled.
FULL MEMORY MODE
ADSP-2189M
1/2x CLOCK
OR
CRYSTAL
CLKIN
14
A13-0
ADDR13-0
D23-16
XTAL
24
FL0-2
DATA
DATA23-0
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
BMS
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
SERIAL
DEVICE
Because the ADSP-2189M includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be
connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used.
BYTE
MEMORY
CS
A10-0
WR
ADDR
RD
D23-8
I/O SPACE
DATA (PERIPHERALS)
CS
IOMS
SPORT1
SERIAL
DEVICE
A0-A21
D15-8
2048 LOCATIONS
A13-0
ADDR
D23-0
DATA
PMS
DMS
CMS
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
BR
BG
BGH
PWD
PWDACK
CLKIN
HOST MEMORY MODE
XTAL
CLKOUT
DSP
ADSP-2189M
1/2x CLOCK
OR
CRYSTAL
CLKIN
XTAL
A0
1
FL0-2
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
SPORT1
SERIAL
DEVICE
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SERIAL
DEVICE
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
IDMA PORT
SYSTEM
INTERFACE
OR
mCONTROLLER
16
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15-0
Figure 3. External Crystal Connections
16
DATA23-8
Reset
The RESET signal initiates a master reset of the ADSP-2189M.
The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
BMS
WR
RD
IOMS
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP.
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
Figure 2. ADSP-2189M Basic System Interface
–6–
REV. 0
ADSP-2189M
Table II. ADSP-2189M Modes of Operation
MODE D
MODE C
MODE B
MODE A
Booting Method
X
0
0
0
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Full Memory Mode.1
X
0
1
0
No automatic boot operations occur. Program execution starts at external
memory location 0. Chip is configured in Full Memory Mode. BDMA can
still be used but the processor does not automatically use or wait for these
operations.
0
1
0
0
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode. IACK has active pull-down.
(REQUIRES ADDITIONAL HARDWARE).
0
1
0
1
IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode. IACK has active pull-down.1
1
1
0
0
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode; IACK requires external pulldown. (REQUIRES ADDITIONAL HARDWARE).
1
1
0
1
IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode. IACK requires external pull-down.1
NOTE
1
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
Passive Configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during powerdown, reconfigure PF2 to be an input, as the pull-up or pulldown will hold the pin in a known state and will not switch.
Power Supplies
The ADSP-2189M has separate power supply connections for
the internal (VDDINT) and external (VDDEXT) power supplies.
The internal supply must meet the 2.5 V requirement. The
external supply can be connected to either a 2.5 V or 3.3 V
supply. All external supply pins must be connected to the same
supply. All input and I/O pins can tolerate input voltages up
to 3.6 V regardless of the external supply voltage. This feature provides maximum flexibility in mixing 2.5 V and 3.3 V
components.
Active Configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver’s output
enable should be connected to the DSP’s RESET signal such
that it only drives the PF2 pin when RESET is active (low).
When RESET is deasserted, the driver should three-state, thus
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant
level and will not oscillate should the three-state driver’s level
hover around the logic switching point.
MODES OF OPERATION
Setting Memory Mode
Memory Mode selection for the ADSP-2189M is made during
chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
REV. 0
IACK Configuration
Mode D = 0 and in host mode: IACK is an active, driven signal
and cannot be wire OR-ed.
–7–
ADSP-2189M
PM (MODE B = 0)
PM (MODE B = 1)1
ALWAYS
ACCESSIBLE
AT ADDRESS
030000 – 031FFF
ACCESSIBLE WHEN
PMOVLAY = 0
RESERVED
032000–
033FFF
ACCESSIBLE WHEN
PMOVLAY = 0
032000–
033FFF
032000–
033FFF
INTERNAL
RESERVED
MEMORY
032000–
030000–
RESERVED
033FFF
031FFF2
032000–
030000–
ACCESSIBLE WHEN
ACCESSIBLE WHEN
033FFF2
PMOVLAY = 5
PMOVLAY = 1
031FFF2
032000–
EXTERNAL
ACCESSIBLE WHEN
RESERVED
2
033FFF
MEMORY
PMOVLAY = 1
EXTERNAL
ACCESSIBLE WHEN
1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
MEMORY
PMOVLAY = 2
2SEE TABLE III FOR PMOVLAY BITS
INTERNAL
MEMORY
ACCESSIBLE WHEN
PMOVLAY = 4
PROGRAM MEMORY
MODE B = 0
ADDRESS
033FFF
PROGRAM MEMORY
MODE B = 1
ADDRESS
033FFF
8K INTERNAL
PMOVLAY = 0, 4, 5
OR
8K EXTERNAL
PMOVLAY = 1, 2
8K INTERNAL
PMOVLAY = 0
032000
031FFF
032000
031FFF
8K EXTERNAL
8K INTERNAL
030000
030000
Figure 4. Program Memory
Mode D = 1 and in host mode: IACK is an open source and
requires an external pull-down, but multiple IACK pins can be
wire OR-ed together.
Data Memory
Data Memory, Full Memory Mode is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2189M has 48K words on Data
Memory RAM on-chip. Part of this space is used by 32 memorymapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus. All internal accesses complete in one cycle. Accesses to external memory
are timed using the wait-states specified by the DWAIT register
and the wait-state mode bit.
MEMORY ARCHITECTURE
The ADSP-2189M provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory and I/O. Refer to the following
figures and tables for PM and DM memory allocations in the
ADSP-2189M.
Program Memory
DATA MEMORY
Program Memory, Full Memory Mode is a 24-bit-wide space
for storing both instruction op codes and data. The ADSP-2189M
has 32K words of Program Memory RAM on chip and the
capability of accessing up to two 8K external memory overlay
spaces using the external data bus.
DATA MEMORY
ALWAYS
ACCESSIBLE
AT ADDRESS
032000 – 033FFF
A13
0, 4, 5
1
Internal
External
Overlay 1
2
External
Overlay 2
Not Applicable Not Applicable
0
13 LSBs of Address
Between 0x2000
and 0x3FFF
1
13 LSBs of Address
Between 0x2000
and 0x3FFF
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 6
ACCESSIBLE WHEN
DMOVLAY = 7
A12:0
033FE0
033FDF
032000
031FFF
030000
030000–
031FFF
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 1
EXTERNAL
MEMORY
ADDRESS
033FFF
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 5
INTERNAL
MEMORY
8K INTERNAL
DMOVLAY =
0, 4, 5, 6, 7
OR
EXTERNAL 8K
DMOVLAY = 1, 2
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 4
Table III. PMOVLAY Bits
Memory
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 0
Program Memory, Host Mode allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16-bits wide only.
PMOVLAY
32 MEMORY–
MAPPED
REGISTERS
INTERNAL
8160
WORDS
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 2
Figure 5. Data Memory Map
–8–
REV. 0
ADSP-2189M
Data Memory, Host Mode allows access to all internal
memory. External overlay access is limited by a single external
address line (A0).
I/O Space (Full Memory Mode)
The ADSP-2189M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit-wide data. The lower eleven
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait-state
registers, IOWAIT0–3, which, in combination with the waitstate mode bit, specify up to 15 wait-states to be automatically
generated for each of four regions. The wait-states act on address ranges as shown in Table V.
Table IV. DMOVLAY Bits
PMOVLAY
Memory
A13
A12:0
0, 4, 5, 6, 7
1
Internal
External
Overlay 1
2
External
Overlay 2
Not Applicable Not Applicable
0
13 LSBs of Address
Between 0x2000
and 0x3FFF
1
13 LSBs of Address
Between 0x2000
and 0x3FFF
Table V. Wait-States
Memory Mapped Registers (New to the ADSP-2189M)
The ADSP-2189M has three memory mapped registers that
differ from other ADSP-21xx Family DSPs. The slight modifications to these registers (Wait-State Control, Programmable
Flag and Composite Select Control and System Control) provide the ADSP-2189M’s wait-state and BMS control features.
Address Range
Wait-State Register
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT0 and Wait-State Mode Select Bit
IOWAIT1 and Wait-State Mode Select Bit
IOWAIT2 and Wait-State Mode Select Bit
IOWAIT3 and Wait-State Mode Select Bit
WAIT-STATE CONTROL
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DWAIT
1
IOWAIT3
IOWAIT2
IOWAIT1
Composite Memory Select (CMS)
DM(0x3FFE)
The ADSP-2189M has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory
select signals (PMS, DMS, BMS, IOMS) but can combine
their functionality.
IOWAIT0
WAIT STATE MODE SELECT (ADSP-2189M)
0 = NORMAL MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 7)
1 = 2N+1 MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 15)
Figure 6. Wait-State Control Register (ADSP-2189M)
When set, each bit in the CMSSEL register causes the CMS
signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory, and use either DMS or PMS as the additional
address bit.
PROGRAMMABLE FLAG & COMPOSITE SELECT CONTROL
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BMWAIT
(BIT-15, ADSP-2189M)
CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
DM(0x3FE6)
PFTYPE
0 = INPUT
1 = OUTPUT
(WHERE BIT: 11-IOM, 10BM, 9-DM, 8-PM)
The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
Figure 7. Programmable Flag and Composite Select Control Register
SYSTEM CONTROL
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
RESERVED, ALWAYS = 0
(ADSP-2189M)
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
Byte Memory Select (BMS)
DM(0x3FFF)
The ADSP-2189M’s BMS disable feature combined with the
CMS pin lets you use multiple memories in the byte memory
space. For example, an EPROM could be attached to the BMS
select, and an SRAM could be connected to CMS. Because
BMS is enabled at reset, the EPROM would be used for booting. After booting, software could disable BMS and set the
CMS signal to respond to BMS, enabling the SRAM.
PWAIT
PROGRAM MEMORY
WAIT STATES
DISABLE BMS (ADSP-2189M)
0 = ENABLE BMS
1 = DISABLE BMS, EXCEPT WHEN MEMORY
STROBES ARE THREE-STATED
SPORT1 CONFIGURE
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SPORT1
Figure 8. System Control Register
REV. 0
–9–
ADSP-2189M
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K × 8.
The byte memory space on the ADSP-2189M supports read
and write operations as well as four different data formats. The
byte memory uses data bits 15:8 for data. The byte memory
uses data bits 23:16 and address bits 13:0 to create a 22-bit
address. This allows up to a 4 meg × 8 (32 megabit) ROM or
RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register and the wait-state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
15 14 13 12 11 10
0
0
0
0
0
0
BDMA CONTROL
9 8 7 6 5
0
0
0
BMPAGE
0
0
4
3
2
1
0
0
1
0
0
0
DM (033FE3)
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2189M. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memorymapped control registers. A typical IDMA transfer process is
described as follows:
Table VI. Data Formats
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
8
Full Word
Full Word
MSBs
LSBs
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait-states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory
accesses.
The BMWAIT field, which has four bits on ADSP-2189M,
allows selection of up to 15 wait-states for BDMA transfers.
The BDMA circuit supports four different data formats which
are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to
build the word size selected. Table VI shows the data formats
supported by the BDMA circuit.
Internal
Memory Space
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
Figure 9. BDMA Control Register
BTYPE
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
BTYPE
BDMA
OVERLAY
BITS
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers. If Bit 15 = 1, the
value of bits 7:0 represent the IDMA overlay: Bits 14:8 must
be set to 0. If Bit 15 = 0, the value of bits 13:0 represent the
starting address of internal memory to be accessed and Bit 14
reflects PM or DM for access.
4. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM).
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
–10–
REV. 0
ADSP-2189M
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written while the ADSP-2189M
is operating at full speed.
DMA
PROGRAM MEMORY
OVLAY
ACCESSIBLE WHEN
PMOVLAY = 0
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the IDMA address latch signal
(IAL) or the missing edge of the IDMA select signal (IS) latches
this value into the IDMAA register.
Once the address is stored, data can then be either read from, or
written to, the ADSP-2189M’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2189M that a particular
transaction is required. In either case, there is a one-processorcycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automatically incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-2189M to write the address onto the IAD0-14
bus into the IDMA Control Register. If Bit 15 is set to 0, IDMA
latches the address. If Bit 15 is set to 1, IDMA latches into the
OVLAY register. This register, shown below, is memory
mapped at address DM (0x3FE0). Note that the latched address
(IDMAA) cannot be read back by the host.
IDMA OVERLAY
15 14 13 12 11 10
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0 DM(033FE7)
RESERVED SET TO 0
ID DMOVLAY
ID PMOVLAY
ALWAYS
ACCESSIBLE
AT ADDRESS
032000 – 033FFF
ALWAYS
ACCESSIBLE
AT ADDRESS
030000 – 031FFF
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for
each memory access.
Refer to the following figures for more information on IDMA
and DMA memory maps.
DMA
DATA MEMORY
OVLAY
ACCESSIBLE WHEN
DMOVLAY = 0
032000–
033FFF
032000–
033FFF
ACCESSIBLE WHEN
PMOVLAY = 4
030000–
031FFF
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 4
032000–
033FFF
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 5
ACCESSIBLE WHEN
PMOVLAY = 5
NOTE: IDMA AND BDMA HAVEN SEPARATE
DMA CONTROL REGISTERS
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 6
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 7
Figure 11. Direct Memory Access—PM and DM Memory
Maps
Bootstrap Loading (Booting)
The ADSP-2189M has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting is controlled by the Mode A, B and C configuration
bits.
When the MODE pins specify BDMA booting, the ADSP-2189M
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the
ADSP-2189M. The only memory address bit provided by the
processor is A0.
IDMA Port Booting
IDMA CONTROL (U = UNDEFINED AT RESET)
15 14 13 12 11 10
U
U
U
U
U
9
8
7
6
5
4
3
2
1
0
U
U
U
U
U
U
U
U
U
U DM(033FE0)
IDMAA ADDRESS
IDMAD DESTINATION MEMORY TYPE:
0 = PM
1 = DM
The ADSP-2189M can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2189M boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
Figure 10. IDMA Control/OVLAY Registers
REV. 0
–11–
ADSP-2189M
Bus Request and Bus Grant
• The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic
add instruction, such as AR = AX0 + AY0, resembles a
simple equation.
The ADSP-2189M can relinquish control of the data and address buses to an external device. When the external device
requires access to memory, it asserts the bus request (BR) signal. If the ADSP-2189M is not performing an external memory
access, it responds to the active BR input in the following processor cycle by:
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly language
and is completely source-and-object-code-compatible with
other family members. Programs may need to be relocated to
utilize on-chip memory and conform to the ADSP-2189M’s
interrupt vector and reset vector map.
• Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,
• Asserting the bus grant (BG) signal, and
• Halting program execution.
If Go Mode is enabled, the ADSP-2189M will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the ADSP-2189M is performing an external memory access
when the external device asserts the BR signal, it will not threestate the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
• Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2189M has on-chip emulation support and an ICEPort, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin
plug.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-2189M requires the
external bus for a memory or BDMA access, but is stopped.
The other device can release the bus by deasserting bus request.
Once the bus is released, the ADSP-2189M deasserts BG and
BGH and executes the external memory access.
Flag I/O Pins
The ADSP-2189M has eight general purpose programmable
input/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2189M’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2189M has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining
mode information (as discussed in Setting Memory Modes),
then it does not matter that the mode information is latched by
an emulator reset. However, if using the RESET pin as a
method of setting the value of the mode pins, the effects of an
emulator reset must be taken into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 12. This circuit forces the value located on the Mode
A pin to logic high; regardless if it latched via the RESET or
ERESET pin.
ERESET
RESET
ADSP-2189M
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.
1kV
MODE A/PFO
INSTRUCTION SET DESCRIPTION
The ADSP-2189M assembly language instruction set has an
algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
PROGRAMMABLE I/O
Figure 12. Mode A Pin/EZ-ICE Circuit
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
–12–
REV. 0
ADSP-2189M
The ICE-Port interface consists of the following ADSP-2189M
pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS,
and ELOUT.
Target Memory Interface
These ADSP-2189M pins must be connected only to the EZICE connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the ADSP2189M and the connector must be kept as short as possible, no
longer than three inches.
The following pins are also used by the EZ-ICE: BR, BG,
RESET, and GND.
The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2189M in the target system. This causes the
processor to use its ERESET, EBR, and EBG pins instead of
the RESET, BR, and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 13. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
1
2
3
4
5
6
7
8
9
10
BG
GND
BR
EBG
EBR
EINT
KEY (NO PIN)
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM, and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in this data sheet. The performance of the EZ-ICE
may approach published worst case specification for some memory
access timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing requirements within published limits.
Restriction: All memory strobe signals on the ADSP-2189M
(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
ELIN
ELOUT
ECLK
11
12
13
14
EMS
EE
RESET
ERESET
TOP VIEW
Figure 13. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.
• EZ-ICE emulation ignores RESET and BR when singlestepping.
• EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted by the EZ-ICE board’s DSP.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
REV. 0
–13–
ADSP-2189M–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
Parameter
Min
Max
Min
Max
Unit
VDDINT
VDDEXT
VINPUT1
TAMB
2.37
2.37
VIL = –0.3
0
2.63
3.6
VIH = 3.6
+70
2.25
2.25
–0.03
–40
2.75
3.6
3.6
+85
V
V
V
°C
NOTES
1
The ADSP-2189M is 3.3 V tolerant (always accepts up to 3.6 Volt max V IH), but voltage compliance (on outputs, V OH) depends on the input V DDEXT; because V OH
(max) ≈ VDDEXT (max). This applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7) and Input Only pins (CLKIN,
RESET, BR, DR0, DR1, PWD).
ELECTRICAL CHARACTERISTICS
Parameter
1, 2
VIH, Hi-Level Input Voltage
VIH, Hi-Level CLKIN Voltage
VIL, Lo-Level Input Voltage1, 3
VOH, Hi-Level Output Voltage1, 4 , 5
VOL, Lo-Level Output Voltage1, 4, 5
IIH, Hi-Level Input Current3
IIL, Lo-Level Input Current3
IOZH, Three-State Leakage Current7
IOZL, Three-State Leakage Current7
IDD, Supply Current (Idle)9
IDD, Supply Current (Idle)9
IDD, Supply Current (Dynamic)10
IDD, Supply Current (Dynamic)10
IDD, Supply Current (Power-Down)12, 15
CI, Input Pin Capacitance3, 6, 13
CO, Output Pin Capacitance6, 7, 12, 14
Test Conditions
Min
@
@
@
@
@
@
@
@
@
@
@
@
@
@
1.5
2.0
VDDINT = max
VDDINT = max
VDDINT = min
VDDEXT = min, IOH = –0.5 mA
VDDEXT = 3.0 V, IOH = –0.5 mA
VDDEXT = min, IOH = –100 µA6
VDDEXT = min, IOL = 2 mA
VDDINT = max, VIN = 3.6 V
VDDINT = max, VIN = 0 V
VDDINT = max, VIN = 3.6 V8
VDDINT = max, VIN = 0 V8
VDDINT = 2.5, tCK = 15 ns
VDDINT = 2.5, tCK = 13.3 ns
VDDINT = 2.5, tCK = 15 ns11,
TAMB = +25°C
@ VDDINT = 2.5, tCK = 13.3 ns11,
TAMB = +25°C
Lowest Power Mode
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
K/B Grades
Typ
Max
Unit
9
10
V
V
V
V
V
V
V
µA
µA
µA
µA
mA
mA
32
mA
36
150
mA
µA
0.6
2.0
2.4
VDDEXT – 0.3
0.4
10
10
10
10
8
pF
8
pF
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
Input Only pins: RESET, BR, DR0, DR1, PWD.
3
Input Only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.
5
Although specified for TTL outputs, all ADSP-2189M outputs are CMOS-compatible and will drive to V DDEXT and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
8
0 V on BR.
9
Idle refers to ADSP-2189M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
11
VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
12
See Chapter 9 of the ADSP-2100 Family User’s Manual, Third Edition for details.
13
Applies to LQFP package type.
14
Output pin capacitance is the capacitive load for any three-stated output pin.
15
VDDINT = 2.5 V. T = 25°C.
Specifications subject to change without notice.
–14–
REV. 0
ADSP-2189M
ABSOLUTE MAXIMUM RATINGS 1
Parameter
Internal Supply Voltage (VDDINT)
External Supply Voltage (VDDEXT)
Input Voltage2
Output Voltage Swing3
Operating Temperature Range (Ambient)
Storage Temperature Range
Lead Temperature (5 sec) LQFP
Value
Min
Max
–0.3 V
–0.3 V
–0.5 V
–0.5 V
–40°C
–65°C
+3.0 V
+4.6 V
+4.6 V
VDDEXT + 0.5 V
+85°C
+150°C
+280°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Applies to Bidirectional pins (D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0,
TFS1, A1–A13, PF0–PF7) and Input only pins (CLKIN, RESET, BR, DR0,
DR1, PWD).
3
Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,
A0, DT0, DT1, CLKOUT, FL2-0, BGH).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-2189M features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMING PARAMETERS
ESD SENSITIVE DEVICE
MEMORY TIMING SPECIFICATIONS
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the processor operates correctly with other devices.
REV. 0
WARNING!
The table below shows common memory device specifications
and the corresponding ADSP-2189M timing parameters, for
your convenience.
Memory
Device
Specification
Timing
Parameter
Parameter Definition1
Address Setup to
Write Start
Address Setup to
Write End
Address Hold Time
tASW
Data Setup Time
tDW
tAW
tWRA
Data Hold Time
tDH
OE to Data Valid
tRDD
Address Access Time tAA
NOTE
1
xMS = PMS, DMS, BMS, CMS or IOMS.
–15–
A0–A13, xMS Setup before
WR Low
A0–A13, xMS Setup before
WR Deasserted
A0–A13, xMS Hold before
WR Low
Data Setup before WR
High
Data Hold after WR High
RD Low to Data Valid
A0–A13, xMS to Data Valid
ADSP-2189M
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
Output Drive Currents
Figure 14 shows typical I-V characteristics for the output drivers
on the ADSP-2189M. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Example: tCKH = 0.5tCK – 7 ns = 0.5 (15 ns) – 7 ns = 0.5 ns
ENVIRONMENTAL CONDITIONS 1
Rating Description
Symbol
Value
Thermal Resistance
(Case-to-Ambient)
(Junction-to-Ambient)
(Junction-to-Case)
θCA
θJA
θJC
48°C/W
50°C/W
2°C/W
80
60
VDDEXT = 3.6V @ –408C
SOURCE CURRENT – mA
tCK is defined as 0.5tCKI. The ADSP-2189M uses an input clock
with a frequency equal to half the instruction rate: a 37.50 MHz
input clock (which is equivalent to 28 ns) yields a 13 ns processor cycle (equivalent to 75 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing parameters to obtain the specification value.
40
VOH
VDDEXT = 3.3V @ +258C
20
VDDEXT = 2.5V @ +858C
0
–20
VDDEXT = 3.6V @ –408C
VOL
–40
VDDEXT = 2.5V @ +858C
VDDEXT = 3.3V @ +258C
–60
NOTE
1
Where the ambient temperature rating (T AMB) is:
TAMB = TCASE – (PD × θCA)
TCASE = Case temperature in °C
PD = Power dissipation in W.
–80
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE – V
3.0
3.5
4.0
Figure 14. Typical Output Driver Characteristics
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:
Assumptions:
• External data memory is accessed every cycle with 50% of
the address pins switching.
• External data memory writes occur every other cycle with
50% of the data pins switching.
• Each address and data pin has a 10 pF total load at the pin.
• The application operates at VDDEXT = 3.3 V and tCK = 15 ns.
Total Power Dissipation = PINT + (C × VDDEXT2 × f)
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 15).
(C × VDDEXT2 × f) is calculated for each output:
Parameters
Address, DMS
Data Output, WR
RD
CLKOUT
# of ⴛ
Pins C
8
9
1
1
10 pF
10 pF
10 pF
10 pF
ⴛ
ⴛ
VDDEXT2 f
2
3.3 V
3.32 V
3.32 V
3.32 V
PD
33.3 MHz
29.0 mW
16.67 MHz 16.3 mW
16.67 MHz 1.8 mW
33.3 MHz
3.6 mW
50.7 mW
Total power dissipation for this example is PINT + 50.7 mW.
–16–
REV. 0
ADSP-2189M
CAPACITIVE LOADING
2189L POWER, INTERNAL1, 2, 3
115
Figure 16 and Figure 17 show the capacitive loading characteristics of the ADSP-2189M.
110mW
110
VDD = 2.65V
100
30
95mW
T = +858C
VDD = 0V TO 2.0V
95
90
85
25
VDD = 2.5V
82mW
82mW
RISE TIME (0.4V–2.4V) – ns
POWER (PINT) – mW
105
80
75
VDD = 2.35V
70mW
70
65
61mW
60
55
50
55
60
65
1/tCK – MHz
70
75
80
POWER, IDLE1, 2, 4
20
15
10
5
30
28mW
0
VDD = 2.65V
24mW
24mW
24
50
100
22
20mW
20mW
20
16
60
65
1/tCK – MHz
70
75
80
POWER, IDLE n MODES 2
26
24mW
IDLE
24
VDD = 2.65V
22
12
10
8
6
4
2
NOMINAL
–2
–4
20
–6
18
14
12
50
300
14
20mW
16
250
16
18
55
200
18
VDD = 2.35V
14
40
150
CL – pF
Figure 16. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
VDD = 2.5V
16.5mW
POWER (PIDLEn) – mW
0
26
VALID OUTPUT DELAY OR HOLD – ns
POWER (PIDLE) – mW
28
VDD = 2.5V
VDD = 2.35V
55
60
65
1/tCK – MHz
50
IDLE (16)
IDLE (128)
15.7mW
70
100
150
200
250
CL – pF
15mW
14.25mW
0
16.4mW
75
Figure 17. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
80
900
VALID FOR ALL TEMPERATURE GRADES.
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 TYPICAL POWER DISSIPATION AT 2.5V V
DDINT AND +258C EXCEPT
WHERE SPECIFIED.
3I
DD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM
INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION
(TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE
IDLE INSTRUCTIONS.
4 IDLE REFERS TO ADSP-2189M STATE OF OPERATION DURING EXECUTION
OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD
OR GND.
800
CURRENT – mA
700
Figure 15. Power vs. Frequency
TEMP = +858C
772mA
TEMP = +708C
475mA
TEMP = +258C
161mA
657mA
600
500
393mA
400
300
200
131mA
100
0
2.25
2.35
2.5
VDD INTERNAL – Volts
2.65
Figure 18. IDD Power-Down
REV. 0
–17–
2.75
ADSP-2189M
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
REFERENCE
SIGNAL
tMEASURED
tENA
VOH
(MEASURED)
The decay time, tDECAY, is dependent on the capacitive load,
CL, and the current load, iL, on the output pin. It can be approximated by the following equation:
t DECAY =
tDIS
VOH
(MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
OUTPUT
C L × 0.5 V
VOL
(MEASURED)
VOL
(MEASURED)
tDECAY
iL
OUTPUT
STARTS
DRIVING
OUTPUT STOPS
DRIVING
from which
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
Figure 20. Output Enable/Disable
IOL
INPUT
OUTPUT
1.5V
2.0V
1.5V
0.8V
TO
OUTPUT
PIN
+1.5V
50pF
Figure 19. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
IOH
Figure 21. Equivalent Device Loading for AC Measurements (Including All Fixtures)
–18–
REV. 0
ADSP-2189M
TIMING PARAMETERS
Parameter
Min
Max
Unit
80
ns
ns
ns
Clock Signals and Reset
Timing Requirements:
tCKI
tCKIL
tCKIH
CLKIN Period
CLKIN Width Low
CLKIN Width High
26.6
13
13
Switching Characteristics:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
0.5tCK – 2
0.5tCK – 2
0
Control Signals
Timing Requirements:
tRSP
tMS
tMH
RESET Width Low
Mode Setup before RESET High
Mode Hold after RESET High
5tCK1
2
5
13
ns
ns
ns
ns
ns
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(3:0)*
tMS
tMH
RESET
*PF3 IS MODE D, PF2 IS MODE C, PF0 IS MODE A
Figure 22. Clock Signals
REV. 0
–19–
ADSP-2189M
Parameter
Min
Interrupts and Flags
Timing Requirements:
tIFS
tIFH
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
0.25tCK + 10
0.25tCK
Switching Characteristics:
tFOH
tFOD
Flag Output Hold after CLKOUT Low5
Flag Output Delay from CLKOUT Low5
0.5tCK – 5
Max
Unit
ns
ns
0.5tCK + 4
ns
ns
NOTES
1
If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further
information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag Outputs = PFx, FL0, FL1, FL2, Flag_out4.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 23. Interrupts and Flags
–20–
REV. 0
ADSP-2189M
Parameter
Min
Bus Request–Bus Grant
Timing Requirements:
tBH
BR Hold after CLKOUT High1
BR Setup before CLKOUT Low1
tBS
0.25tCK + 2
0.25tCK + 10
Switching Characteristics:
tSD
tSDB
tSE
tSEC
tSDBH
tSEH
0
0
0.25tCK – 3
0
0
CLKOUT High to xMS, RD, WR Disable
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
xMS, RD, WR Disable to BGH Low2
BGH High to xMS, RD, WR Enable2
Max
Unit
ns
ns
0.25tCK + 8
ns
ns
ns
ns
ns
ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
tSD
tSEC
tSDB
tSE
tSDBH
tSEH
Figure 24. Bus Request–Bus Grant
REV. 0
–21–
ADSP-2189M
Parameter
Min
Memory Read
Timing Requirements:
tRDD
tAA
tRDH
RD Low to Data Valid
A0–A13, xMS to Data Valid
Data Hold from RD High
0
Switching Characteristics:
tRP
tCRD
tASR
tRDA
tRWR
RD Pulsewidth
CLKOUT High to RD Low
A0–A13, xMS Setup before RD Low
A0–A13, xMS Hold after RD Deasserted
RD High to RD or WR Low
0.5tCK – 3 + w
0.25tCK – 2
0.25tCK – 3
0.25tCK – 3
0.5tCK – 3
Max
Unit
0.5tCK – 5 + w
0.75tCK – 6 + w
ns
ns
ns
0.25tCK + 4
ns
ns
ns
ns
ns
w = wait-states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0 – A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tCRD
tRP
tRWR
D
tAA
tRDD
tRDH
WR
Figure 25. Memory Read
–22–
REV. 0
ADSP-2189M
Parameter
Memory Write
Switching Characteristics:
tDW
tDH
tWP
tWDE
tASW
tDDR
tCWR
tAW
tWRA
tWWR
Min
Data Setup before WR High
Data Hold after WR High
WR Pulsewidth
WR Low to Data Enabled
A0–A13, xMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0–A13, xMS, Setup before WR Deasserted
A0–A13, xMS Hold after WR Deasserted
WR High to RD or WR Low
Max
0.5tCK – 4 + w
0.25tCK – 1
0.5tCK – 3 + w
0
0.25tCK – 3
0.25tCK – 3
0.25tCK – 2
0.75tCK – 5 + w
0.25tCK – 1
0.5tCK – 3
w = wait-states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tASW
tWWR
tWP
tAW
tDH
tCWR
D
tDW
tWDE
RD
Figure 26. Memory Write
REV. 0
–23–
tDDR
0.25tCK + 4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2189M
Parameter
Min
Serial Ports
Timing Requirements:
tSCK
tSCS
tSCH
tSCP
SCLK Period
DR/TFS/RFS Setup before SCLK Low
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
26.67
4
7
12
Switching Characteristics:
tCC
tSCDE
tSCDV
tRH
tRD
tSCDH
tTDE
tTDV
tSCDD
tRDV
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero) to DT Valid
0.25tCK
0
CLKOUT
tCC
Max
ns
ns
ns
ns
0.25tCK + 6
12
0
12
0
0
12
12
12
tCC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCK
SCLK
tSCP
tSCS
tSCP
tSCH
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFSOUT
ALTERNATE
FRAME MODE
tRDV
RFSOUT
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
TFSIN
tTDE
tTDV
ALTERNATE
FRAME MODE
RFSIN
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
tRDV
Figure 27. Serial Ports
–24–
REV. 0
ADSP-2189M
Parameter
IDMA Address Latch
Timing Requirements:
tIALP
tIASU
tIAH
tIKA
tIALS
tIALD
Min
Duration of Address Latch1, 2
IAD15–0 Address Setup before Address Latch End2
IAD15–0 Address Hold after Address Latch End2
IACK Low before Start of Address Latch2, 3
Start of Write or Read after Address Latch End2, 3
Address Latch Start after Address Latch End1, 2
10
5
3
0
3
2
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
tIALD
IAL
tIALP
tIALP
IS
IAD15–0
tIASU
tIAH
tIASU
RD OR WR
Figure 28. IDMA Address Latch
REV. 0
–25–
tIAH
tIALS
Max
Unit
ns
ns
ns
ns
ns
ns
ADSP-2189M
Parameter
Min
IDMA Write, Short Write Cycle
Timing Requirements:
IACK Low before Start of Write1
tIKW
tIWP
Duration of Write1, 2
tIDSU
IAD15–0 Data Setup before End of Write2, 3, 4
IAD15–0 Data Hold after End of Write2, 3, 4
tIDH
0
10
3
2
Switching Characteristics:
tIKHW
Start of Write to IACK High
Max
Unit
ns
ns
ns
ns
10
ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
4
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDSU
IAD 15–0
tIDH
DATA
Figure 29. IDMA Write, Short Write Cycle
–26–
REV. 0
ADSP-2189M
Parameter
Min
IDMA Write, Long Write Cycle
Timing Requirements:
IACK Low before Start of Write1
tIKW
tIKSU
IAD15–0 Data Setup before End of Write2, 3, 4
tIKH
IAD15–0 Data Hold after End of Write2, 3, 4
0
0.5tCK + 5
0
Switching Characteristics:
tIKLW
tIKHW
Start of Write to IACK Low4
Start of Write to IACK High
Max
Unit
ns
ns
ns
1.5tCK
10
ns
ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
3
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD15–0
Figure 30. IDMA Write, Long Write Cycle
REV. 0
–27–
ADSP-2189M
Parameter
Min
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
End of Read after IACK Low2
tIRK
0
2
Switching Characteristics:
tIKHR
tIKDS
tIKDH
tIKDD
tIRDE
tIRDV
tIRDH1
tIRDH2
IACK High after Start of Read1
IAD15–0 Data Setup before IACK Low
IAD15–0 Data Hold after End of Read2
IAD15–0 Data Disabled after End of Read2
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
IAD15–0 Previous Data Hold after Start of Read (PM2)4
Max
ns
ns
10
0.5tCK – 2
0
10
0
11
2tCK – 3
tCK – 5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRK
IRD
tIKDH
tIKDS
tIRDE
PREVIOUS
DATA
IAD15–0
READ
DATA
tIRDV
tIKDD
tIRDH
Figure 31. IDMA Read, Long Read Cycle
–28–
REV. 0
ADSP-2189M
Parameter
Min
IDMA Read, Short Read Cycle
Timing Requirements:
IACK Low before Start of Read1
tIKR
tIRP
Duration of Read
0
10
Switching Characteristics:
tIKHR
tIKDH
tIKDD
tIRDE
tIRDV
IACK High after Start of Read1
IAD15–0 Data Hold after End of Read2
IAD15–0 Data Disabled after End of Read2
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
10
10
0
10
IACK
tIKR
tIKHR
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
DATA
IAD15–0
tIRDV
tIKDD
Figure 32. IDMA Read, Short Read Cycle
REV. 0
–29–
Unit
ns
ns
0
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
IS
Max
ns
ns
ns
ns
ns
ADSP-2189M
A5/IAD4
1
2
A4/IAD3
78 D18
77 D17
76 D16
80 GND
79 D19
82 D21
81 D20
84 D23
83 D22
86 FL1
85 FL2
87 FL0
89 PF2 [MODE C]
88 PF3
91 PWD
90 VDDEXT
92 GND
94 PF0 [MODE A]
93 PF1 [MODE B]
96 PWDACK
95 BGH
98 A1/IAD0
97 A0
100 A3/IAD2
99 A2/IAD1
100-Lead LQFP Package Pinout
75 D15
74 D14
PIN 1
IDENTIFIER
GND
3
73 D13
A6/IAD5
4
A7/IAD6
5
72 D12
71 GND
A8/IAD7
A9/IAD8
6
A10/IAD9
8
A11/IAD10
9
70 D11
69 D10
7
68 D9
67 VDDEXT
A12/IAD11 10
66 GND
A13/IAD12 11
GND 12
65 D8
64 D7/IWR
ADSP-2189M
CLKIN 13
63 D6/IRD
TOP VIEW
(Not to Scale)
XTAL 14
VDDEXT 15
62 D5/IAL
61 D4/IS
60 GND
59 VDD INT
58 D3/IACK
CLKOUT 16
GND 17
VDDINT 18
WR 19
RD 20
57 D2/IAD15
BMS 21
DMS 22
55 D0/IAD13
54 BG
PMS 23
53 EBG
52 BR
56 D1/IAD14
IOMS 24
CMS 25
–30–
EINT 50
ELIN 49
ELOUT 48
EMS 45
EE 46
ECLK 47
RESET 44
ERESET 43
GND 41
SCLK1 42
RFS1 39
DR1 40
DT1 37
TFS1 38
DR0 34
SCLK0 35
VDDEXT 36
TFS0 32
RFS0 33
IRQ2+PF7 30
DT0 31
GND 28
IRQL1+PF6 29
IRQE+PF4 26
IRQL0+PF5 27
51 EBR
REV. 0
ADSP-2189M
The ADSP-2189M package pinout appears in the following table. Pin names in bold text replace the plain text named functions
when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed
in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.
PIN CONFIGURATION
LQFP
Number
Pin Name
LQFP
Number
Pin Name
LQFP
Number
Pin Name
LQFP
Number
Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A4/IAD3
A5/IAD4
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
CLKIN
XTAL
VDDEXT
CLKOUT
GND
VDDINT
WR
RD
BMS
DMS
PMS
IOMS
CMS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IRQE + PF4
IRQL0 + PF5
GND
IRQL1 + PF6
IRQ2 + PF7
DT0
TFS0
RFS0
DR0
SCLK0
VDDEXT
DT1
TFS1
RFS1
DR1
GND
SCLK1
ERESET
RESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
EBR
BR
EBG
BG
D0/IAD13
D1/IAD14
D2/IAD15
D3/IACK
VDDINT
GND
D4/IS
D5/IAL
D6/IRD
D7/IWR
D8
GND
VDDEXT
D9
D10
D11
GND
D12
D13
D14
D15
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D16
D17
D18
D19
GND
D20
D21
D22
D23
FL2
FL1
FL0
PF3 [Mode D]
PF2 [Mode C]
VDDEXT
PWD
GND
PF1 [Mode B]
PF0 [Mode A]
BGH
PWDACK
A0
A1/IAD0
A2/IAD1
A3/IAD2
REV. 0
–31–
ADSP-2189M
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3605–2.5–7/99
100-Lead Metric Thin Plastic Quad Flatpack
(ST-100)
0.638 (16.20)
0.630 (16.00) TYP SQ
0.622 (15.80)
0.553 (14.05)
0.551 (14.00) TYP SQ
0.549 (13.95)
0.063 (1.60) MAX
0.030 (0.75)
0.024 (0.60) TYP
128
0.020 (0.50)
TYP
SEATING
PLANE
0.472 (12.00) BSC
100
1
76
75
TOP VIEW
(PINS DOWN)
0.003
(0.08)
MAX LEAD
COPLANARITY
08 – 78
68 ± 48
25
26
0.007 (0.177)
0.005 (0.127) TYP
0.003 (0.077)
51
50
0.020 (0.50)
BSC
0.011 (0.27)
0.009 (0.22) TYP
0.007 (0.17)
LEAD PITCH
LEAD WIDTH
NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08) 0.0032 FROM
ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED
ORDERING GUIDE
Part Number
Ambient Temperature Range
Instruction Rate
Package Description*
Package Option
ADSP-2189MKST-300
ADSP-2189MBST-266
0°C to +70°C
–40°C to +85°C
75 MHz
66 MHz
100-Lead LQFP
100-Lead LQFP
ST-100
ST-100
PRINTED IN U.S.A.
*In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labelled TQFP packages
(1.6 mm thick) are now designated as LQFP.
–32–
REV. 0