LINER LTM8062IVPBF 32vin, 2a î¼module power tracking battery charger Datasheet

LTM8062
32VIN, 2A µModule Power
Tracking Battery Charger
FEATURES
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DESCRIPTION
Complete Battery Charger System
Input Supply Voltage Regulation Loop for Peak
Power Tracking in MPPT (Maximum Peak Power
Tracking) Solar Applications
Wide Input Voltage Range: 4.95V to 32V
(40V Abs Max)
2A Charge Current
Resistor Programmable Float Voltage Up to 14.4V
Accommodates Li-Ion/Polymer, LiFePO4, SLA
Integrated Input Reverse Voltage Protection
User Selectable Termination: C/10 or Termination
Timer
0.75% Float Voltage Reference Accuracy
9mm × 15mm × 4.32mm LGA Package
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The LTM8062 employs an input voltage regulation loop,
which reduces charge current if the input voltage falls below
a programmed level, set with a resistor divider. When the
LTM8062 is powered by a solar panel, this input regulation
loop is used to maintain the panel at peak output power.
The LTM8062 also features preconditioning trickle charge,
bad battery detection, a choice of termination schemes
and automatic restart.
The LTM8062 is packaged in a thermally enhanced, compact (9mm × 15mm × 4.32mm) over-molded land grid
array (LGA) package suitable for automated assembly
by standard surface mount equipment. The LTM8062 is
RoHS compliant.
APPLICATIONS
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The LTM®8062 is a complete 32VIN, 2A μModule® power
tracking battery charger. The LTM8062 provides a constant-current/constant-voltage charge characteristic, a 2A
maximum charge current, and employs a 3.3V float voltage
feedback reference, so any desired battery float voltage up
to 14.4V can be programmed with a resistor divider.
Industrial Handheld Instruments
12V to 24V Automotive and Heavy Equipment
Desktop Cradle Chargers
Solar Power Battery Charging
L, LT, LTC, LTM, Linear Technology, the Linear logo and μModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
2A LiFePO4 μModule Battery Charger
Charge Current vs Battery Voltage
2500
VINA
LTM8062
VIN
4.7μF
BAT
BIAS
VINREG
CHRG
RUN
FAULT
TMR
ADJ
NTC
274k
2.87M
GND
1-CELL
LiFePO4
(3.6V)
CHARGING CURRENT (mA)
VIN
6V TO 32V
NORMAL CHARGING
2000
1500
1000
500
PRECONDITION
8062 TA01a
TERMINATION
0
0
1
3
2
BATTERY VOLTAGE (V)
4
8062 TA01b
8062f
1
LTM8062
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VINA, VIN ...................................................................40V
VINREG, RUN, CHRG, FAULT ......................VIN + 0.5, 40V
TMR, NTC ................................................................2.5V
BAT ...........................................................................15V
BIAS ..........................................................................10V
ADJ .............................................................................5V
Maximum Internal Operating Temperature
(Note 2)................................................................. 125°C
Maximum Body Solder Temperature..................... 245°C
TOP VIEW
BIAS ADJ FAULT CHRG GND
7
BAT
NTC TMR RUN VINREG
BANK 2
6
5
VINA
BANK 3
4
BANK 1
3
GND
BANK 4
2
VIN
1
A
B
C
D
E
F
G
H
J
K
L
LGA PACKAGE
77-LEAD (15mm s 9mm s 4.32mm)
TJMAX = 125°C, θJA = 17.0°C/W, θJCbottom = 6.1°C/W,
θJCtop = 16.2°C/W, θJB = 11.2°C/W, WEIGHT = 1.7g
θ VALUES DETERMINED PER JEDEC 51-9, 51-12
ORDER INFORMATION
LEAD FREE FINISH
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTM8062EV#PBF
LTM8062EV#PBF
LTM8062V
77-Lead (15mm × 9mm × 4.32mm) LGA
–40°C to 125°C
LTM8062IV#PBF
LTM8062IV#PBF
LTM8062V
77-Lead (15mm × 9mm × 4.32mm) LGA
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
8062f
2
LTM8062
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C. RUN = 2V.
PARAMETER
CONDITIONS
MIN
TYP
VIN Maximum Operating Voltage
32
l
VIN Start Voltage
VIN OVLO Threshold
VIN Rising
7.5
32
VIN OVLO Hysteresis
VIN UVLO Threshold
VIN Rising
VIN UVLO Hysteresis
VINA to VIN Diode Forward Voltage Drop
VINA Current = 2A
Maximum BAT Float Voltage
IBAT = 2A
Input Supply Current
Standby Mode
RUN = 0, VIN Reg Open
Maximum BAT Charging Current
(Note 3)
ADJ Float Reference Voltage
(Note 4)
35
V
40
V
1
V
4.6
V
0.3
V
0.55
V
14.7
1.8
3.275
3.25
UNITS
V
85
18
l
ADJ Recharge Threshold Voltage
MAX
3.3
V
μA
μA
2.1
A
3.325
3.34
V
V
Threshold Relative to ADJ Float Reference (Note 3)
82.5
ADJ Precondition Threshold Voltage
ADJ Rising (Note 4)
2.3
V
ADJ Precondition Threshold Hysteresis Voltage
Relative to ADJ Precondition Threshold (Note 4)
95
mV
ADJ Input Bias Current
Charging Terminated
CV Operation (Note 5)
65
110
nA
nA
VINREG Reference Voltage
ADJ = 3V, IBAT = 1A
l
2.61
2.7
mV
2.83
V
VINREG Bias Current
VINREG = VINREG Reference
35
100
nA
NTC Range Limit (High) Voltage
VNTC Rising
1.25
1.36
1.45
V
NTC Range Limit (Low) Voltage
VNTC Falling
0.27
0.29
0.315
V
250
500
NTC Disable Impedance
NTC Bias Current
VNTC = 0.8V
45
NTC Threshold Hysteresis
For Both High and Low Range Limits
RUN Threshold Voltage
VRUN Rising
20
1.15
RUN Hysteresis Voltage
1.20
25
TMR Disable Threshold Voltage
Operating Frequency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM8062E is guaranteed to meet performance specifications
from 0°C to 125°C internal. Specifications over the full –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM8062I is guaranteed to meet specifications over the full –40°C to
nA
0.4
TMR Charge/Discharge Current
1
V
μA
0.25
0.85
V
mV
–10
10mA Load
μA
%
1.25
120
RUN Input Bias Current
CHRG, FAULT Output Low Voltage
kΩ
53
V
1.15
MHz
125°C internal operating temperature range. Note that the maximum
internal temperature is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 3: The maximum BAT charging current is reduced by thermal
foldback. See the Typical Performance Characteristics for details.
Note 4: ADJ voltages measured through 250k equivalent series resistance.
Note 5: Output battery float voltage programming resistor divider
equivalent resistance = 250k compensates for input bias current.
8062f
3
LTM8062
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs IBAT, 4.2V Float
Efficiency vs IBAT, 7.2V Float
84
Efficiency vs IBAT, 8.4V Float
87
82
88
VINA = 12V
86
VINA = 12V
87
VINA = 24V
85
VINA = 24V
78
76
86
84
EFFICIENCY (%)
EFFICIENCY (%)
80
EFFICIENCY (%)
TA = 25°C, unless otherwise noted.
VINA = 24V
83
85
VINA = 12V
84
74
82
83
72
81
82
70
80
0
500
1000
IBAT (mA)
1500
2000
81
500
0
1000
IBAT (mA)
1500
8062 G01
2000
0
500
1500
1000
IBAT (mA)
2000
8062 G02
Efficiency vs IBAT, 14.4V Float
8062 G03
ADJ Float Voltage vs Temperature
IBIAS vs IBAT, 4.2V Float
25
3.280
90
2500
89
VINA = 24V
20
87
86
85
84
VINA = 12V
3.275
IBIAS (mA)
ADJ FLOAT VOLTAGE (V)
EFFICIENCY (%)
88
15
10
3.270
VINA = 24V
5
83
82
0
500
1000
IBAT (mA)
1500
2000
3.265
–50
0
–25
25
50
75
0
TEMPERATURE (°C)
0
125
IBIAS vs IBAT, 7.2V Float
IBIAS vs IBAT, 8.4V Float
45
40
45
40
35
40
VINA = 12V
30
25
20
5
0
0
0
500
1000
IBAT (mA)
1500
2000
8062 G07
25
20
15
VINA = 24V
10
5
VINA = 24V
30
15
VINA = 24V
10
VINA = 12V
IBIAS (mA)
IBIAS (mA)
30
2000
35
35
15
1500
IBIAS vs IBAT, 14.4V Float
50
20
1000
IBAT (mA)
8062 G06
45
25
500
8062 G05
8062 G04
IBIAS (mA)
100
10
5
0
500
1000
IBAT (mA)
1500
2000
8062 G08
0
0
500
1000
IBAT (mA)
1500
2000
8062 G09
8062f
4
LTM8062
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs IBAT, 4.2V Float
Input Current vs IBAT, 7.2V Float
Input Current vs IBAT, 8.4V Float
1400
900
800
1600
1400
1200
VINA = 12V
VINA = 12V
600
INPUT CURRENT (mA)
VINA = 12V
500
400
300
VINA = 24V
200
INPUT CURRENT (mA)
700
INPUT CURRENT (mA)
TA = 25°C, unless otherwise noted.
1000
800
600
400
VINA = 24V
200
100
0
500
1500
1000
IBAT (mA)
2000
1000
800
600
VINA = 24V
400
200
0
0
1200
0
0
500
1000
IBAT (mA)
1500
8062 G10
2000
0
500
1500
1000
IBAT (mA)
2000
8062 G11
Input Current vs IBAT, 14.4V Float
8062 G12
Maximum IBAT vs ADJ
IQ vs VINA, RUN = 0V, VINREG Open
1400
2500
250
2500
200
2000
MAXIMUM IBAT (mA)
1000
150
800
IQ (μA)
INPUT CURRENT (mA)
1200
VINA = 24V
600
100
400
1500
1000
500
50
200
0
0
0
0
500
1500
1000
IBAT (mA)
2000
0
10
20
VINA (V)
30
8062 G13
2000
1600
20
TEMPERATURE RISE (°C)
25
CHARGE CURRENT (mA)
2000
1200
800
400
500
0
2
3
2.5
3.5
VINREG (V)
8062 G16
1.5
2
2.5
ADJ VOLTAGE (V)
3
0
–40 –20
3.5
Temperature Rise vs IBAT,
4.2V Float Voltage
2500
1000
1
8062 G15
Maximum Charge Current
vs Temperature
1500
0.5
8062 G14
Maximum IBAT vs VINREG
MAXIMUM IBAT (mA)
0
40
15
VINA = 24V
10
VINA = 12V
5
0
0
20 40 60 80 100 120
TEMPERATURE (°C)
8062 G17
0
500
1000
IBAT (mA)
1500
2000
8062 G18
8062f
5
LTM8062
TYPICAL PERFORMANCE CHARACTERISTICS
Temperature Rise vs IBAT,
8.4V Float Voltage
30
30
25
25
TEMPERATURE RISE (°C)
TEMPERATURE RISE (°C)
Temperature Rise vs IBAT,
7.2V Float Voltage
TA = 25°C, unless otherwise noted.
20
VINA = 24V
15
VINA = 12V
10
VINA = 12V
20
15
VINA = 24V
10
5
5
0
0
0
500
1000
IBAT (mA)
1500
0
2000
500
1000
IBAT (mA)
1500
8062 G20
8062 G19
Temperature Rise vs IBAT,
14.4V Float Voltage
VIN Standby Mode Current
vs Temperature
40
6
VIN STANDBY MODE CURRENT (mA)
35
TEMPERATURE RISE (°C)
2000
30
25
VINA = 24V
20
15
10
5
0
0
500
1000
IBAT (mA)
1500
2000
8062 G21
5
4
VINA = 12V
3
VINA = 24V
2
1
0
–50
0
50
TEMPERATURE (°C)
100
8062 G22
PIN FUNCTIONS
GND (Bank 1, Pin L7): Power and Signal Ground Return.
BAT (Bank 2): Battery Charge Current Output Bus. The charge
function operates to achieve the final float voltage at this pin.
The auto-restart feature initiates a new charging cycle when
the voltage at the ADJ pin falls 2.5% below the float voltage.
Once the charge cycle is terminated, the input bias current of
the BAT pin is reduced to minimize battery discharge while
the charger remains connected.
VINA (Bank 3): Anode of input reverse protection Schottky
diode. Connect the input power here if input reverse voltage
protection is desired.
VIN (Bank 4): Charger Input Supply. Decouple with at least
4.7μF to GND. Connect the input power here if no input reverse
voltage protection is needed.
BIAS (Pin G7): The BIAS pin connects to the internal power bus.
In most cases connect to VBAT. If this is not desirable, connect
to a power source greater than 2.8V and less than 10V.
CHRG (Pin K7): Open-Collector Charger Status Output; typically pulled up through a resistor to a reference voltage. This
status pin can be pulled up to voltages as high as VIN and can
sink currents up to 10mA. During a battery charging cycle,
CHRG is pulled low. When the charge current falls below C/10,
8062f
6
LTM8062
PIN FUNCTIONS
the CHRG pin becomes high impedance. If the internal timer
is used for termination, the pin stays low during the charging cycle until the charge current drops below a C/10 rate,
approximately 200mA, even though the charger will continue
to top off the battery until the end-of-charge timer terminates
the charge cycle. A temperature fault also causes this pin to
be pulled low (see the Applications Information section).
NTC (Pin H6): Battery Temperature Monitor Pin. This pin
is the input to the NTC (negative temperature coefficient)
thermistor temperature monitoring circuit. This function is
enabled by connecting a 10kΩ, B = 3380 NTC thermistor
from the NTC pin to ground. The pin sources 50μA, and
monitors the voltage across the 10kΩ thermistor. When the
voltage on this pin is above 1.36V (T < 0°C) or below 0.29V
(T > 40°C), charging is disabled and the CHRG and FAULT
pins are both pulled low. If the internal timer termination is
being used, the timer is paused, suspending the charging
cycle. Charging resumes when the voltage on NTC returns to
within the 0.29V to 1.36V active region. There is approximately
5°C of temperature hysteresis associated with each of the
temperature thresholds. The temperature monitoring function remains enabled while thermistor resistance to ground
is less than 250kΩ. If this function is not desired, leave the
NTC pin unconnected.
ADJ (Pin H7): Battery Float Voltage Feedback Input. The charge
function operates to achieve a final float voltage of 3.3V on this
pin. The output battery float voltage (VBAT(FLT)) is programmed
using a resistor divider. VBAT(FLT) can be programmed up to
14.4V. The auto-restart feature initiates a new charging cycle
when the voltage at the ADJ pin falls 2.5% below the float
voltage reference. The ADJ pin input bias current is 110nA.
Using a resistor divider with an equivalent input resistance
at the ADJ pin of 250k compensates for input bias current
error. Required resistor values to program desired VBAT(FLT)
follow the equations:
R1=
R2 =
VBAT(FLT) • 2.5 • 10
5
3.3
R1• 2.5 • 105
R1− (2.5 • 105 )
(Ω)
(Ω)
R1 is connected from BAT to ADJ, and R2 is connected from
ADJ to ground.
pin can be pulled up to voltages as high as VIN and can sink
currents up to 10mA. This pin indicates charge cycle fault
conditions during a battery charging cycle. A temperature
fault causes this pin to be pulled low. If the internal timer is
used for termination, a bad battery fault also causes this pin
to be pulled low. If no fault conditions exist, the FAULT pin
remains high impedance (see the Applications Information
section).
TMR (Pin J6): End-Of-Cycle Timer Programming Pin. If a timerbased charge termination is desired, connect a capacitor from
this pin to ground. Full charge end-of cycle time (in hours) is
programmed with this capacitor following the equation:
tEOC = CTIMER • 4.4 • 106
A bad battery fault is generated if the battery does not reach
the precondition threshold voltage within one-eighth of tEOC,
or:
tPRE = CTIMER • 5.5 • 105
A 0.68μF capacitor is often used, which generates a timer EOC
at three hours, and a precondition limit time of 22.5 minutes.
If a timer-based termination is not desired, the timer function
can be disabled by connecting the TMR pin to ground. With the
timer function disabled, charging terminates when the charge
current drops below a C/10 rate, approximately 200mA.
VINREG (Pin L6): Input Voltage Regulation Reference. The
maximum charge current is reduced when this pin is below
2.7V. Connecting a resistor divider from VIN to this sets the
minimum operational VIN voltage. This is typically used to
program the peak power voltage for a solar panel. The LTM8062
servos the maximum charge current required to maintain the
programmed operational VIN voltage, through maintaining the
voltage on VINREG at or above 2.7V. If the voltage regulation
feature is not used, connect the pin to VIN.
RUN (Pin K6): Precision Threshold Enable Input Pin. The
RUN threshold is 1.25V (rising), with 120mV of input hysteresis. When in shutdown mode, all charging functions are
disabled. The precision threshold allows use of the RUN pin
to incorporate UVLO functions. If the RUN pin is pulled below
0.4V, the IC enters a low current shutdown mode where the
VIN pin current is reduced to 15μA. Typical RUN pin input
bias current is 10nA. If the shutdown function is not desired,
connect the pin to the VIN pin.
FAULT (Pin J7): Open-Collector Fault Status Output; typically
pulled up through a resistor to a reference voltage. This status
8062f
7
LTM8062
BLOCK DIAGRAM
VINA
VIN
8.2μH
0.1μF
0.1μF
SENSE
RESISTOR
BAT
10μF
BIAS
VINREG
RUN
INTERNAL
COMPENSATION
ADJ
CURRENT
MODE
BATTERY
MANAGEMENT
CONTROLLER
ADJ
TMR
NTC
GND
FAULT
CHRG
8062 BD
OPERATION
The LTM8062 is a complete monolithic, mid-power, power
tracking battery charger, addressing high input voltage applications with solutions that use a minimum of external
components. The product can be programmed for float
voltages between 3.3V and 14.4V with just two external
resistors, operating under a 1MHz fixed frequency, average
current mode step-down architecture. A 2A power Schottky
diode is integrated within the μModule for reverse input
voltage protection. A wide input range allows the operation
to full charge from an input voltage up to 32V. A precision
threshold on the RUN pin allows the implementation of
a UVLO feature by using a simple resistor network. The
charger can also be put into a low current shutdown mode,
in which the input supply bias is reduced to only 15μA.
The LTM8062 employs an input voltage regulation loop,
which reduces charge current if a monitored input voltage falls below a programmed level. When the LTM8062
is powered by a solar panel, the input regulation loop
is used to maintain the panel at peak output power. The
LTM8062 automatically enters a battery precondition mode
if the sensed battery voltage is very low. In this mode,
the charge current is reduced to 300mA. Once the battery voltage climbs above the internally set precondition
threshold (2.3V at the ADJ pin), the μModule automatically increases the maximum charge current to the full
programmed value.
The LTM8062 can use a charge current based C/10 termination scheme, which ends a charge cycle when the battery
charge current falls to one-tenth the programmed charge
current. The LTM8062 also contains an internal charge cycle
control timer, for timer-based termination. When using the
internal timer, the charge cycle can continue beyond the
C/10 level to top-off the battery. The charge cycle terminates
when the programmed time elapses, about three hours for
a 0.68μF timer capacitor. The CHRG status pin continues
to signal charging at a C/10 or greater rate, regardless of
8062f
8
LTM8062
OPERATION
which termination scheme is used. When the timer-based
scheme is used, the LTM8062 also supports bad battery
detection, which triggers a system fault if a battery stays
in precondition mode for more than one-eighth of the total
programmed charge cycle time.
Once charging terminates and the LTM8062 is not actively
charging, the charger automatically enters a low current
standby mode in which supply bias currents are reduced
to 85μA. If the battery voltage drops 2.5% from the full
charge float voltage, the LTM8062 engages an automatic
charge cycle restart. The IC also automatically restarts a
new charge cycle after a bad-battery fault once the failed
battery is removed and replaced with another battery.
The LTM8062 contains a battery temperature monitoring
circuit. This feature, using a thermistor, monitors battery
temperature and will not allow charging to begin, or will
suspend charging, and signal a fault condition if the battery temperature is outside a safe charging range. The
LTM8062 contains two digital open-collector outputs,
CHRG and FAULT, which provide charger status and signal
fault conditions. These binary coded pins signal battery
charging, standby or shutdown modes, battery temperature
faults and bad battery faults. For reference, C/10 and TMR
based charging cycles are shown in Figures 1 and 2.
FLOAT VOLTAGE
RECHARGE THRESHOLD
BATTERY VOLTAGE
PRECONDITION THRESHOLD
MAXIMUM CHARGE CURRENT
BATTERY CHARGE
CURRENT
PRECONDITION CURRENT
C/10
0 AMPS
1
CHRG
0
1
FAULT
0
1
0
RUN
8062 F01
Figure 1. Typical C/10 Terminated Charge Cycle (TMR Grounded, Time Not to Scale)
FLOAT VOLTAGE
RECHARGE THRESHOLD
BATTERY VOLTAGE
PRECONDITION THRESHOLD
MAXIMUM CHARGE CURRENT
BATTERY CHARGE
CURRENT
PRECONDITION CURRENT
C/10 CURRENT
1
CHRG
0
1
0
1
FAULT
RUN
0
< tEOC /8
tEOC
AUTOMATIC
RESTART
8062 F02
Figure 2. Typical EOC (Timer-Based) Terminated Charge Cycle
(Capacitor Connected to TMR, Time Not to Scale)
8062f
9
LTM8062
APPLICATIONS INFORMATION
For most applications, the design process is straight
forward, summarized as follows:
1. Look at Table 1 and find the row that has the desired
input voltage range and battery float voltage.
2. Apply the recommended CIN and RADJ values.
Reverse Protection Diode
The LTM8062 integrates a high voltage power Schottky
diode to provide input reverse voltage protection. The
anode of this diode is connected to VINA, and the cathode
is connected to VIN. There is a small mount of capacitance
at each end; please see the Block Diagram.
3. Connect BIAS as indicated.
While these component combinations have been tested
for proper operation, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions. Bear in mind that the
maximum output current is limited by junction temperature, the relationship between the input and output voltage
magnitude and polarity and other factors. Please refer to
the graphs in the Typical Performance Characteristics
section for guidance.
Table 1. Recommended Component Values and Configuration
(TA = 25°C)
VIN RANGE (V)*
VBAT (V)
CIN
RADJ1
TOP
(kΩ)
6 to 32
3.6
4.7μF 1206 X7R 50V
274
2870
6 to 32
4.1
4.7μF 1206 X7R 50V
312
1260
RADJ2
BOTTOM
(kΩ)
6 to 32
4.2
4.7μF 1206 X7R 50V
320
1150
6.25 to 32
4.7
4.7μF 1206 X7R 50V
357
835
9.5 to 32
7.05
4.7μF 1206 X7R 50V
530
464
9.75 to 32
7.2
4.7μF 1206 X7R 50V
549
459
11 to 32
8.2
4.7μF 1206 X7R 50V
626
417
11.5 to 32
8.4
4.7μF 1206 X7R 50V
642
412
12.75 to 32
9.4
4.7μF 1206 X7R 50V
715
383
16.5 to 32
12.3
4.7μF 1206 X7R 50V
942
344
17 to 32
12.6
4.7μF 1206 X7R 50V
965
340
18.25 to 32
13.5
4.7μF 1206 X7R 50V
1020
328
19 to 32
14.08
4.7μF 1206 X7R 50V
1090
332
19.5 to 32
14.42
4.7μF 1206 X7R 50V
1110
328
Input Supply Voltage Regulation
The LTM8062 contains a voltage monitor pin that enables
programming a minimum operational voltage. Connecting a resistor divider from VIN to the VINREG pin enables
programming of minimum input supply voltage, typically
used to program the peak power voltage for a solar panel.
Maximum charge current is reduced when the VINREG pin
is below the regulation threshold of 2.7V.
If the VINREG function is not used, and if the input supply
cannot provide enough power to satisfy the requirements
of an LTM8062 charger, the input supply voltage will collapse. A minimum operating supply voltage can thus be
programmed by monitoring the supply through a resistor
divider, such that the desired minimum voltage corresponds
to 2.7V at the VINREG pin. The LTM8062 servos the maximum output charge current to maintain the voltage on
VINREG at or above 2.7V.
Programming of the desired minimum voltage is accomplished by connecting a resistor divider as shown in
Figure 3. The ratio of RIN1/RIN2 for a desired minimum
voltage (VIN(MIN)) is:
RIN1/RIN2 = (VIN(MIN) /2.7) – 1
If the voltage regulation feature is not used, connect the
VINREG pin to VIN.
INPUT SUPPLY
VIN
RIN1
* Input bulk capacitance is required.
VIN Input Supply
The LTM8062 is biased directly from the charger input supply through the VIN pin. This pin provides large switched
currents, so a high quality low ESR decoupling capacitor is
recommended to minimize voltage glitches on VIN. 4.7μF
is typically adequate for most charger applications.
LTM8062
VINREG
RIN2
8062 F03
Figure 3. Resistive Divider Sets Minimum VIN
BIAS Pin Considerations
The BIAS pin is used to provide drive power for the internal power switching stage and operate other internal
8062f
10
LTM8062
APPLICATIONS INFORMATION
circuitry. For proper operation, it must be powered by at
least 2.8V and no more than the absolute maximum rating of 10V. In most applications, connect BIAS to BAT. If
there is no BIAS supply available or the battery voltage is
below 2.8V, the internal switch requires more headroom
from VIN for proper operation. Please refer to the Typical
Performance Characteristics curves for minimum start and
running requirements under various battery conditions.
When charging a 2-cell battery using a relatively high input
voltage, the LTM8062 power dissipation can be reduced by
connecting BIAS to a voltage between 2.8V and 3.3V.
Output Capacitance
In many applications, the internal BAT capacitance of the
LTM8062 is sufficient for proper operation. There are cases,
however, where it may be necessary to add capacitance or
otherwise modify the output impedance of the LTM8062.
Case 1: the μModule is physically located far from the
battery and the added line impedance may interfere with
the control loop. Case 2: the battery ESR is very small or
very large; the LTM8062 controller is designed for a wide
range, but some battery packs have an ESR outside of this
range. Case 3: there is no battery at all. As the charger is
designed to work with the ESR of the battery, the output
may oscillate if no battery is present.
The optimum ESR is about 100mΩ, but ESR values both
higher and lower will work. Table 2 shows a sample of
parts successfully tested by Linear Technology:
Table 2
PART NUMBER
DESCRIPTION
MANUFACTURER
16TQC22M
22μF, 16V, POSCAP
Sanyo
35SVPD18M
18μF, 35V, OS-CON
Sanyo
TPSD226M025R0100
22μF, 25V Tantalum
AVX
T495D226K025AS
22μF, 25V, Tantalum
Kemet
TPSC686M006R0150
68μF, 6V, Tantalum
AVX
TPSB476M006R0250
47μF, 6V, Tantalum
AVX
APXE100ARA680ME61G
68μF, 10V Aluminum
Nippon Chemicon
APS-150ELL680MHB5S
68μF, 25V Aluminum
Nippon Chemicon
If system constraints preclude the use of electrolytic capacitors, a series R-C network may be used. Use a ceramic
capacitor of at least 22μF and an equivalent resistance of
100mΩ. An example of this is shown in the Typical Applications section.
MPPT Temperature Compensation
A typical solar panel is comprised of a number of series-connected cells, each cell being a forward-biased p-n junction.
As such, the open-circuit voltage (VOC) of a solar cell has
a temperature coefficient that is similar to a common p-n
diode, or about –2mV/°C. The peak power point voltage
(VMP) for a crystalline solar panel can be approximated as
a fixed voltage below VOC, so the temperature coefficient
for the peak power point is similar to that of VOC.
Panel manufacturers typically specify the 25°C values for
VOC, VMP, and the temperature coefficient for VOC, making
determination of the temperature coefficient for VMP of
a typical panel straight forward. The LTM8062 employs
a feedback network to program the VIN input regulation
voltage. Manipulation of the network makes for efficient
implementation of various temperature compensation
schemes for a maximum peak power tracking (MPPT)
application. As the temperature characteristic for a typical
solar panel VMP voltage is highly linear, a simple solution
for tracking that characteristic can be implemented using a
Linear Technology LM234 3-terminal temperature sensor.
This creates an easily programmable, linear temperature
dependent characteristic.
In the circuit shown in Figure 4,
R IN1 = –RSET • (TC • 4405), and
R IN2 =
RIN1
VMP (25°C) + RIN1 • (0.0674 / RSET )
VINREG − 1
where TC = temperature coefficient (in V/°C), and
VMP(25°C) = maximum power voltage at 25°C.
VIN
LINEAR
TECHNOLOGY
LM234
V+
RIN1
V–
R
RSET
VIN
VINREG
RIN2
LTM8062
8062 F04
Figure 4. MPPT Temperature Compensation Network
8062f
11
LTM8062
APPLICATIONS INFORMATION
For example, given a common 36-cell solar panel that has
the following specified characteristics:
Open Circuit Voltage (VOC) = 21.7V
Maximum Power Voltage (VMP) = 17.6V
Open-Circuit Voltage Temperature Coefficient (VOC)
= –78mV/°C
As the temperature coefficient for VMP is similar to that
of VOC, the specified temperature coefficient for VOC
(TC) of –78mV/°C and the specified peak power voltage
(VMP(25°C)) of 17.6V can be inserted into the equations
to calculate the appropriate resistor values for the temperature compensation network in Figure 4. With RSET
equal to 1k, then:
RSET = 1k
In a manner similar to the MPPT temperature correction
outlined previously, implementation of linear battery charge
voltage temperature compensation can be accomplished by
incorporating a Linear Technology LM234 into the output
feedback network. For example, a 6-cell lead acid battery
has a float charge voltage that is commonly specified at
2.25V/cell at 25°C, or 13.5V, and a –3.3mV/°C per cell
temperature coefficient, or –19.8mV/°C. Using the feedback
network shown in Figure 5, with the desired temperature
coefficient (TC) and 25°C float voltage (VFLOAT (25°C))
specified, and using a convenient value of 2.4k for RSET,
necessary resistor values follow the relations:
RFB1 = –RSET • (TC • 4405)
= –2.4k • (–0.0198 • 4405) = 210k
RFB2 =
R IN1 = −1k • (−0.078 • 4405) = 344k
344k
= 24.4k
17.6 + 344k • (0.0674 / 1k)
−1
2.7
Battery Voltage Temperature Compensation
R IN2 =
RFB1
VFLOAT (25°C) + RFB1 • (0.0674 / RSET )
−1
VFB
210k
13.5 + 210k • (0.0674 / 2.4k)
−1
3.3
= 43k
=
Some battery chemistries have charge voltage requirements that vary with temperature. Lead-acid batteries in
particular experience a significant change in charge voltage requirements as temperature changes. For example,
manufacturers of large lead-acid batteries recommend a
float charge of 2.25V/cell at 25°C. This battery float voltage,
however, has a temperature coefficient which is typically
specified at –3.3mV/°C per cell.
RFB3 = 250k – RFB1||RFB2
= 250k – 210k||43k = 215k
(see the Battery Float Voltage Programming section)
While the circuit in Figure 5 creates a linear temperature characteristic that follows a typical –3.3mV/°C per
cell lead-acid specification, the theoretical float charge
14.3
14.2
14.0
BAT
LTM8062
RFB3
215k
RSET
2.4k
R
V+ LINEAR
TECHNOLOGY
V– LM234
+
–19.8mV/°C
13.8
6-CELL
LEAD-ACID
BATTERY
ADJ
VFLOAT (V)
RFB1
210k
13.6
13.4
13.2
RFB2
43k
13.0
8062 F05a
12.8
12.6
–10
0
20
30
10
40
TEMPERATURE (°C)
50
60
8062 F05b
Figure 5. Lead-Acid 6-Cell Float Charge Voltage vs Temperature with a –19.8mV/°C
Temperature Coefficient Using LM234 with the Feedback Network
8062f
12
LTM8062
APPLICATIONS INFORMATION
14.8
14.6
14.4
14.2
196k
LTM8062
198k
69k
6-CELL
LEAD-ACID
BATTERY
+
22k
B = 3380
VFLOAT (V)
BAT
14.0
THEORETICAL VFLOAT
13.8
13.6
13.4
ADJ
13.2
69k
8062 F06a
PROGRAMMED VBAT(FLOAT)
13.0
12.8
–10
0
20
30
10
40
TEMPERATURE (°C)
50
60
8062 F06b
Figure 6. Thermistor-Based Temperature Compensation Network Programs VFLOAT
to Closely Match Ideal Lead-Acid Float Charge Voltage for 6-Cell Charger
voltage characteristic is slightly nonlinear. This nonlinear
characteristic follows the relation:
VFLOAT = 4 • 10–5 (T2) – 6 • 10–3(T) + 2.375
(with a 2.18V minimum)
where T = temperature in °C. A thermistor-based network
can be used to approximate the nonlinear ideal temperature characteristic across a reasonable operating range,
as shown in Figure 6.
Status Pins
The LTM8062 reports charger status through two opencollector outputs, the CHRG and FAULT pins. These pins
can be pulled up as high as VIN, and can sink up to 10mA.
The CHRG pin indicates that the charger is delivering
current at greater than a C/10 rate, or one-tenth of the
programmed charge current. The FAULT pin signals badbattery and NTC faults. These pins are binary coded, as
shown in Table 3.
Table 3. Status Pin State
CHRG
FAULT
STATUS
High
High
Not Charging—Standby or Shutdown Mode
High
Low
Bad-Battery Fault (Precondition Timeout/EOC Failure)
Low
High
Normal Charging at C/10 or Greater
Low
Low
NTC Fault (Pause)
If the battery is removed from an LTM8062 charger that is
configured for C/10 termination, a low amplitude sawtooth
waveform appears at the charger output, due to cycling
between termination and recharge events. This cycling
results in pulsing at the CHRG output. An LED connected
to this pin will exhibit a blinking pattern, indicating to the
user that a battery is not present. The frequency of this
blinking pattern is dependent on the output capacitance.
C/10 Charge Termination
The LTM8062 supports a low current based termination
scheme, where a battery charge cycle terminates when
the charge current falls below one-tenth the programmed
charge current, or approximately 200mA. This termination
mode is engaged by shorting the TMR pin to ground. When
C/10 termination is used, an LTM8062 charger sources
battery charge current as long as the average current level
remains above the C/10 threshold. As the full-charge float
voltage is achieved, the charge current falls until the C/10
threshold is reached, at which time the charger terminates
and the LTM8062 enters standby mode. The CHRG status
pin follows the charger cycle and is high impedance when
the charger is not actively charging. There is no provision
for bad-battery detection if C/10 termination is used.
Timer Charge Termination
The LTM8062 supports a timer-based termination scheme,
where a battery charge cycle terminates after a specific
amount of time elapses. Timer termination is engaged
when a capacitor (CTIMER) is connected from the TMR pin
to ground. The timer cycle time span (tEOC) is determined
by CTIMER in the equation:
CTIMER = tEOC • 2.27 • 10–7 (Hours)
8062f
13
LTM8062
APPLICATIONS INFORMATION
When charging at a 1C rate, tEOC is commonly set to three
hours, which requires a 0.68μF capacitor.
The CHRG status pin continues to signal charging, regardless of which termination scheme is used. When timer
termination is used, the CHRG status pin is pulled low
during a charge cycle until the charge current falls below
the C/10 threshold. The charger continues to top off the
battery until timer EOC, when the LTM8062 terminates the
charge cycle and enters standby mode.
Termination at the end of the timer cycle only occurs if the
charge cycle was successful. A successful charge cycle
occurs when the battery is charged to within 2.5% of the
full-charge float voltage. If a charge cycle is not successful at EOC, the timer cycle resets and charging continues
for another full timer cycle. When VBAT drops 2.5% from
the full-charge float voltage, whether by battery loading
or replacement of the battery, the charger automatically
resets and starts charging.
Preconditioning and Bad-Battery Fault
The LTM8062 has a precondition mode, where the charge
current is limited to 15% of the maximum charge current, or
approximately 300mA. Precondition mode is engaged if the
voltage on the BAT pin is below the precondition threshold,
or approximately 70% of the float voltage. Once the BAT
voltage rises above the precondition threshold, normal fullcurrent charging can commence. The LTM8062 incorporates
90mV hysteresis to avoid spurious mode transitions.
Bad-battery detection is engaged when the internal timer
is used for termination (capacitor tied to TMR). This fault
detection feature is designed to identify failed cells. A
bad-battery fault is triggered when the voltage on BAT
remains below the precondition threshold for greater than
one-eighth of a full timer cycle (one-eighth EOC). A badbattery fault is also triggered if a normally charging battery
re-enters precondition mode after one-eighth EOC.
When a bad-battery fault is triggered, the charge cycle
is suspended, and the CHRG status pin becomes high
impedance. The FAULT pin is pulled low to signal that a
fault has been detected.
Cycling the charger’s power or shutdown function initiates
a new charge cycle, but the LTM8062 charger does not
require a manual reset. Once a bad-battery fault is detected,
a new timer charge cycle initiates if the BAT pin exceeds
the precondition threshold voltage. During a bad-battery
fault, a small current is sourced from the charger; removing
the failed battery allows the charger output voltage to rise
above the preconditioning threshold voltage and initiate a
charge cycle reset. A new charge cycle is started by connecting another battery to the charger output.
Battery Temperature Fault: NTC
The LTM8062 can accommodate battery temperature
monitoring by using an NTC (negative temperature
coefficient) thermistor close to the battery pack. The
temperature monitoring function is enabled by connecting a 10kΩ, β ≈ 3380 NTC thermistor from the NTC pin
to ground. If the NTC function is not desired, leave the
pin open. The NTC pin sources 50μA, and monitors the
voltage dropped across the 10kΩ thermistor. When the
voltage on this pin is above 1.36V (0°C) or below 0.29V
(40°C), the battery temperature is out of range, and the
LTM8062 triggers an NTC fault. The NTC fault condition
remains until the voltage on the NTC pin corresponds to
a temperature within the 0°C to 40°C range. Both hot and
cold thresholds incorporate 20% hysteresis, which equates
to about 5°C. If higher operational charging temperatures
are desired, the temperature range can be expanded by
adding series resistance to the 10k NTC resistor. Adding
a 909Ω resistor will increase the effective temperature
threshold to 45°C, for example.
During an NTC fault, charging is halted and both status
pins are pulled low. If timer termination is enabled, the
timer count is suspended and held until the fault condition is cleared.
Thermal Foldback
The LTM8062 contains a thermal foldback protection feature
that reduces charge current as the IC junction temperature
approaches 125°C. In most cases, on-chip temperatures
servo such that any overtemperature conditions are relieved
with only slight reductions in maximum charge current.
In some cases, the thermal foldback protection feature
can reduce charge currents below the C/10 threshold.
In applications that use C/10 termination (TMR = 0V), the
LTM8062 will suspend charging and enter standby mode
until the overtemperature condition is relieved.
8062f
14
LTM8062
APPLICATIONS INFORMATION
ADJ
BAT
NTC
FAULT
TMR
CHRG
GND
(OPTIONAL)
RUN VINREG
CBAT
VINA
GND
CIN
VIN
8062 F07
THERMAL VIAS
Figure 7. Suggested Layout and Via Placement
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
LTM8062 integration. The LTM8062 is nevertheless
a switching power supply, and care must be taken to
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 7
for a suggested layout. Ensure that the grounding and
heat sinking are acceptable.
1. Place the CIN capacitor as close as possible to the VIN
and GND connection of the LTM8062.
2. If used, place the CBAT capacitor as close as possible
to the BAT and GND connection of the LTM8062.
3. Place the CIN and CBAT (if used) capacitors such that their
ground current flows directly adjacent or underneath
the LTM8062.
4. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8062.
5. For good heat sinking, use vias to connect the GND copper area to the board’s internal ground planes. Liberally
distribute these GND vias to provide both a good ground
connection and thermal path to the internal planes of the
printed circuit board. Pay attention to the location and
density of the thermal vias in Figure 5. The LTM8062
can benefit from the heat-sinking afforded by vias that
connect to internal GND planes at these locations, due to
their proximity to internal power handling components.
The optimum number of thermal vias depends upon
the printed circuit board design. For example, a board
might use very small via holes. It should employ more
thermal vias than a board that uses larger holes.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8062. However, these capacitors
can cause problems if the LTM8062 is plugged into a
live input supply (see Application Note 88 for a complete
discussion). The low loss ceramic capacitor combined
with stray inductance in series with the power source
forms an underdamped tank circuit, and the voltage at the
VIN pin of the LTM8062 can ring to more than twice the
nominal input voltage, possibly exceeding the LTM8062’s
rating and damage the part. If the input supply is poorly
controlled or the user will be plugging the LTM8062 into
an energized supply, the input network should be designed
to prevent this overshoot. This can be accomplished by
installing a small resistor in series with VIN, but the most
popular method of controlling input voltage overshoot is
8062f
15
LTM8062
APPLICATIONS INFORMATION
to add an electrolytic bulk capacitor to the VIN net. This
capacitor’s relatively high equivalent series resistance
damps the circuit and eliminates the voltage overshoot.
The extra capacitor improves low frequency ripple filtering and can slightly improve the efficiency of the circuit,
though it is physically large.
Thermal Considerations
The thermal performance of the LTM8062 is given in the
Typical Performance Characteristics section. These curves
were generated by the LTM8062 mounted to a 58cm2
4-layer FR4 printed circuit board. Boards of other sizes
and layer count can exhibit different thermal behavior, so
it is incumbent upon the user to verify proper operation
over the intended system’s line, load and environmental
operating conditions.
For increased accuracy and fidelity to the actual application,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration section of the data sheet
typically gives four thermal coefficients:
1. θJA: Thermal resistance from junction to ambient.
2. θJCbottom : Thermal resistance from junction to the bottom of the product case.
3. θJCtop : Thermal resistance from junction to top of the
product case.
4. θJB: Thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased below:
1. θJA is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted to
a JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
2. θJCbottom is the junction-to-board thermal resistance
with all of the component power dissipation flowing
through the bottom of the package. In the typical
μModule, the bulk of the heat flows out the bottom
of the package, but there is always heat flow out into
the ambient environment. As a result, this thermal resistance value may be useful for comparing packages
but the test conditions don’t generally match the user’s
application.
3. θJCtop is determined with nearly all of the component
power dissipation flowing through the top of the package. As the electrical connections of the typical μModule
are on the bottom of the package, it is rare for an application to operate such that most of the heat flows
from the junction to the top of the part. As in the case
of θJCbottom, this value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
4. θJB is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
μModule and into the board, and is really the sum of the
θJCbottom and the thermal resistance of the bottom of the
part through the solder joints and through a portion of
the board. The board temperature is measured a specified distance from the package, using a two sided, two
layer board. This board is described in JESD 51-9.
The most appropriate way to use the coefficients is when
running a detailed thermal analysis, such as FEA, which
considers all of the thermal resistances simultaneously.
None of them can be individually used to accurately predict the thermal performance of the product, so it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature versus load graphs
given in the LTM8033 data sheet.
A graphical representation of these thermal resistances
is given in Figure 8.
The blue resistances are contained within the μModule,
and the green are outside.
The die temperature of the LTM8062 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM8062. The bulk of the heat flow out of the LTM8062
is through the bottom of the module and the LGA pads
into the printed circuit board. Consequently a poor printed
circuit board design can cause excessive heating, resulting in impaired performance or reliability. Please refer to
the PCB Layout section for printed circuit board design
suggestions.
8062f
16
LTM8062
APPLICATIONS INFORMATION
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
80421 F08
μMODULE DEVICE
Figure 8. Thermal Resistances Among μModule Device
Printed Circuit Board and Ambient Environment
TYPICAL APPLICATIONS
Basic 2A, 2-Cell LiFePO4 Battery Charger with C/10 Termination
VIN
9.5V TO 32VDC
VINA
LTM8062
VIN
4.7μF
BAT
+
BIAS
VINREG
CHRG
RUN
FAULT
TMR
ADJ
NTC
2-CELL
LiFePO4
(2× 3.6V)
BATTERY
549k
(OPTIONAL
ELECTROLYTIC
CAPACITOR)
459k
GND
8062 TA02
2A Solar Panel Power Manager with 8.4V Lithium Ion Battery Pack and 16V Peak Power Tracking
VIN
SOLAR
POWER UNIT
VINA
LTM8062
VIN
499k
4.7μF
100k
BAT
BIAS
VINREG
CHRG
RUN
FAULT
TMR
ADJ
NTC
642k
+
(OPTIONAL
ELECTROLYTIC
CAPACITOR)
2-CELL
Li-ION
(2× 4.2V)
BATTERY
NTC
10k
B = 3380
412k
GND
8062 TA03
8062f
17
0.9525
1.5875
4
2.540
15
BSC
Y
aaa Z
3.95 – 4.05
DETAIL A
0.635 ±0.025 SQ. 76x
0.27 – 0.37
SUBSTRATE
eee S X Y
DETAIL B
MOLD
CAP
DETAIL B
4.22 – 4.42
6.350
5.080
3.810
2.540
1.270
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
SYMBOL TOLERANCE
aaa
0.15
bbb
0.10
eee
0.05
6. THE TOTAL NUMBER OF PADS: 77
5. PRIMARY DATUM -Z- IS SEATING PLANE
LAND DESIGNATION PER JESD MO-222, SPP-010
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
X
0.000
SUGGESTED PCB LAYOUT
TOP VIEW
2.540
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
3.810
1.270
2.540
3.810
5.080
6.350
PACKAGE TOP VIEW
1.270
PAD 1
CORNER
9
BSC
0.000
aaa Z
4.1275
3.4925
3.810
0.9525
1.5875
1.270
(Reference LTC DWG # 05-08-1856 Rev A)
Z
18
// bbb Z
LGA Package
77-Lead (15mm × 9mm × 4.32mm)
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
3
PADS
SEE NOTES
1.27
BSC
12.70
BSC
7
5
7.62
BSC
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
PAD 1
DIA (0.635)
LGA 77 0909 REV A
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
MModule
PACKAGE BOTTOM VIEW
6
DETAIL A
LTM8062
PACKAGE DESCRIPTION
8062f
LTM8062
PACKAGE DESCRIPTION
Table 3. Pin Assignment Table
(Arranged by Pin Number)
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
A1
GND
B1
GND
C1
GND
D1
GND
E1
GND
F1
GND
A2
GND
B2
GND
C2
GND
D2
GND
E2
GND
F2
GND
A3
GND
B3
GND
C3
GND
D3
GND
E3
GND
F3
GND
A4
GND
B4
GND
C4
GND
D4
GND
E4
GND
F4
GND
A5
GND
B5
GND
C5
GND
D5
GND
E5
GND
F5
GND
A6
BAT
B6
BAT
C6
BAT
D6
BAT
E6
BAT
F6
BAT
A7
BAT
B7
BAT
C7
BAT
D7
BAT
E7
BAT
F7
BAT
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
G1
GND
H1
GND
J1
GND
K1
VIN
L1
VIN
G2
GND
H2
GND
J2
GND
K2
VIN
L2
VIN
G3
GND
H3
GND
J3
GND
K3
VIN
L3
VIN
G4
GND
H4
GND
J4
GND
K4
VINA
L4
VINA
G5
GND
H5
GND
J5
GND
K5
VINA
L5
VINA
G6
GND
H6
NTC
J6
TMR
K6
RUN
L6
VINREG
G7
BIAS
H7
ADJ
J7
FAULT
K7
CHRG
L7
GND
PACKAGE PHOTO
8062f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTM8062
TYPICAL APPLICATION
2A Solar Panel Power Manager for Charging 2-Cell 8.4V Lithium-Ion Battery, Featuring Three Hour
Charge Time and 16V Peak Power Tracking. Battery Powers Two μModule Regulators
VIN
SOLAR
POWER UNIT
VINA
LTM8062
VIN
499k
4.7μF
0.68μF
100k
BAT
LTM8023
VOUT
LTM8021
VOUT
BIAS
VINREG
CHRG
RUN
FAULT
TMR
ADJ
NTC
642k
2-CELL
Li-Ion
(2s 4.2V)
BATTERY
NTC
10k
B = 3380
412k
GND
8062 TA04
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM4600
10A DC/DC μModule Regulator
Basic 10A DC/DC μModule, 15mm × 15mm × 2.8mm LGA
LTM4600HVMPV
Military Plastic 10A DC/DC μModule Regulator
–55°C to 125°C Operation, 15mm × 15mm × 2.8mm LGA
LTM4601/
LTM4601A
12A DC/DC μModule Regulator with PLL, Output
Tracking/Margining and Remote Sensing
Synchronizable, PolyPhase Operation, LTM4601-1 Version has no Remote
Sensing
LTM4602
6A DC/DC μModule Regulator
Pin Compatible with the LTM4600
LTM4603
6A DC/DC μModule Regulator with PLL and Output Synchronizable, PolyPhase Operation, LTM4603-1 Version has no Remote
Tracking/Margining and Remote Sensing
Sensing, Pin Compatible with the LTM4601
LTM4604A
4A Low VIN DC/DC μModule Regulator
2.375V ≤ VIN ≤ 5V, 0.8V ≤ VOUT ≤ 5V, 9mm × 15mm × 2.3mm LGA
LTM4608A
8A Low VIN DC/DC μModule Regulator
2.375V ≤ VIN ≤ 5V, 0.8V ≤ VOUT ≤ 5V, 9mm × 15mm × 2.8mm LGA
LTM8020
200mA, 36V DC/DC μModule Regulator
EN55022 Class B Compliant, Fixed 450kHz Frequency, 1.25V ≤ VOUT ≤ 5V,
6.25mm × 6.25mm × 2.32mm LGA
LTM8022
1A, 36V DC/DC μModule Regulator
Adjustable Frequency, 0.8V ≤ VOUT ≤ 5V, 9mm × 11.25mm × 2.82mm LGA,
Pin Compatible to the LTM8023
LTM8023
2A, 36V DC/DC μModule Regulator
Adjustable Frequency, 0.8V ≤ VOUT ≤ 5V, 9mm × 11.25mm × 2.82mm LGA,
Pin Compatible to the LTM8022
LTM8025
3A, 36V DC/DC μModule Regulator
0.8V ≤ VOUT ≤ 24V, 9mm × 15mm × 4.32mm LGA
LTM8021
500mA, 36V DC/DC μModule Regulator
EN55022 Class B Compliant, Fixed 1.1MHz Frequency, 0.8V ≤ VOUT ≤ 5V,
6.25mm × 11.25mm × 2.82mm LGA
8062f
20 Linear Technology Corporation
LT 0810 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
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