ON NCP5214MNR2 2-in-1 notebook ddr power controller Datasheet

NCP5214
Product Preview
2−in−1 Notebook DDR
Power Controller
The NCP5214 2−in−1 Notebook DDR Power Controller is
specifically designed as a total power solution for notebook DDR
memory system. This IC combines the efficiency of a PWM
controller for the VDDQ supply with the simplicity of linear
regulators for the VTT termination voltage and the buffered low
noise reference. This IC contains a synchronous PWM buck
controller for driving two external NFETs to form the DDR memory
supply voltage (VDDQ). The DDR memory termination regulator
output voltage (VTT) and the buffered VREF are internally set to
track at the half of VDDQ. An internal power good voltage monitor
tracks VDDQ output and notifies the user whether the VDDQ output
is within target range. Protective features include soft−start
circuitries, undervoltage monitoring of supply voltage, VDDQ
overcurrent protection, VDDQ overvoltage and undervoltage
protections, and thermal shutdown. The IC is packaged in DFN−22.
Features
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Incorporates VDDQ, VTT Regulator, Buffered VREF
Adjustable VDDQ Output
VTT and VREF Track VDDQ/2
Operates from Single 5.0 V Supply
Supports VDDQ Conversion Rails from 5.0 V to 24 V
Power−saving Mode for High Efficiency at Light Load
Integrated Power FETs with VTT Regulator Sourcing/Sinking 1.5 A
DC and 2.4 A Peak Current
Buffered Low Noise 15 mA VREF Output
All External Power MOSFETs are N−channel
<5.0 A Current Consumption During Shutdown
Fixed Switching Frequency of 400 kHz
Soft−start Protection for VDDQ and VTT
Undervoltage Monitor of Supply Voltage
Overvoltage Protection and Undervoltage Protection for VDDQ
Short−circuit Protection for VDDQ and VTT
Thermal Shutdown
Housed in DFN−22
Typical Applications
• Notebook DDR/DDR2 Memory Supply and Termination Voltage
• Active Termination Busses (SSTL−18, SSTL−2, SSTL−3)
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MARKING
DIAGRAM
22
DFN−22
MN SUFFIX
CASE 506AF
1
NCP5214
AWLYYWW
1
NCP5214
A
WL
YY
WW
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
VDDQEN
VTTEN
FPWM
SS
VTTGND
VTT
VTTI
FBVTT
AGND
DDQREF
VCCA
PGND
BGDDQ
VCCP
SWDDQ
TGDDQ
BOOST
OCDDQ
PGOOD
VTTREF
FBDDQ
COMP
(Top View)
NOTE: Pin 23 is the thermal pad on
the bottom of the device.
ORDERING INFORMATION
Device
Package
Shipping†
NCP5214MNR2
DFN−22
2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
 Semiconductor Components Industries, LLC, 2005
April, 2005 − Rev. P0
1
Publication Order Number:
NCP5214/D
NCP5214
CL1
VDDQEN
VDDQEN
RL1
VTTEN
VTTEN
OCDDQ
FPWM
FPWM
5VCC
SS
BOOST
CSS
VIN
VCCP
5VCC
PWRGD
M1
PGOOD
0.9 V, 2.4 Apk
TGDDQ
VTT
FBVTT
BGDDQ
VTTGND
PGND1
M2
COUT1
POSCAP
150 F x2
5VCC
COMP
VCCA
CZ1
0.9 V, 15 mA
CP1
RZ1
VREF
VTTREF
CZ2
R1
RZ2
FBDDQ
R2
DDQREF
AGND
VTTI
Figure 1. Typical Application Diagram
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1.8 V, 10 A
1.8 H
SWDDQ
NCP5214
VDDQ
L
VTT
COUT2
Ceramic
22 F x2
5 V to 24 V
(Battery/
Adapter)
NCP5214
5VCC
VIN
VREF
VREFGD
THERMAL
SHUTDOWN
TSD
VDDQEN
VTTEN
VTTEN
CBULK
5VCC
VCCP
FPWM
FPWM
VOCDDQGD
VCCA
VCCP
CONTROL
LOGIC
VCCAGD
VCCA
VBOOST
BOOST
FAULT
+
−
ILIM
VOFFSET
+
−
RL1
+
−
VREF
INREGDDQ
IREF
OCDDQ
VBOOST
VOCDDQ
VREF
CDCPL
VDDQEN
CBOOST
VOLTAGE &
CURRENT
REFERENCE
VDDQ
PWM
LOGIC
+
−
M3
TGDDQ
FBDDQ
L
SWDDQ
VDDQEN
VCCA
VTTEN
SS
Power−
Saving
Loop
Control
SWDDQ
VCCP
NEGATIVE CURRENT
DETECTION
5VCC
BGDDQ
PGND
PGND
VREF
PGOOD
+ −
+
−
UVLO
COUT1
M4
+
−
PWM−
COMP
VFBDDQ
OVLO
VFBDDQ
+
−
VREF
OSC
COMP
PGND
VREF
VOCDDQ
Adaptive
Ramp
A
CZ1
+
−
CZ2
CP1
RZ1
RZ2
R1
FBDDQ
R2
+
−
DDQREF
Current
Limit &
Soft−Start
VCCA
M1
SC2PWR
VTT
VTTI
VTTREF
Deadband
Control
+
−
VTTI
VDDQEN
VTTEN
INREGDDQ
VTT
Regulation
Control
VTTGND
VTT
VCCA
COUT2
M2
+
−
VTTREF
COUT3
VDDQ
SC2GND
PGND
VTTGND
VTTGND
VTTGND
FBVTT
GND
AGND
VTTGND
Figure 2. Detailed Block Diagram
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NCP5214
PIN FUNCTION DESCRIPTION
Pin
Symbol
Description
1
VDDQEN
2
VTTEN
VTT regulator enable input. High to enable.
3
FPWM
Forced PWM enable input. Low to enable forced PWM mode and disable power−saving mode.
VDDQ regulator enable input. High to enable.
4
SS
5
VTTGND
VDDQ Soft−start capacitor connection to ground.
6
VTT
VTT regulator output.
7
VTTI
Power input for VTT regulator which is normally connected to the VDDQ output of the buck regulator.
8
FBVTT
VTT regulator feedback pin for closed loop regulation.
9
AGND
Analog ground connection and remote ground sense.
10
DDQREF
11
VCCA
5.0 V supply input for the IC’s control and logic section, which is monitored by undervoltage lock out
circuitry.
12
COMP
VDDQ error amplifier compensation node.
13
FBDDQ
VDDQ regulator feedback pin for closed loop regulation.
14
VTTREF
DDR reference voltage output.
15
PGOOD
Power good signal open−drain output.
16
OCDDQ
Overcurrent sense and program input for the high−side FET of VDDQ regulator. Also the battery
voltage input for the internal ramp generator to implement the voltage feedforward rejection to the input
voltage variation.
17
BOOST
Positive supply input for high−side gate driver of VDDQ regulator and boost capacitor connection.
18
TGDDQ
Gate driver output for VDDQ regulator high−side N−Channel power FET.
19
SWDDQ
VDDQ regulator inductor driven node, return for high−side gate driver, and current limit sense input.
20
VCCP
Power supply for the VDDQ regulator low−side gate driver and also supply voltage for the bootstrap
capacitor of the VDDQ regulator high−side gate driver supply.
21
BGDDQ
22
PGND
Power ground for the VDDQ regulator.
23
THPAD
Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground plane
under the IC.
Power ground for the VTT regulator.
External reference input which is used to regulate VTT and VTTREF to 1/2VDDQREF.
Gate driver output for VDDQ regulator low−side N−Channel power FET.
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NCP5214
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCCA, VCCP
−0.3, 6.0
V
VBOOST−VSWDDQ,
VTGDDQ−VSWDDQ
−0.3, 6.0
V
VIO
−0.3, 6.0
V
Overcurrent Sense Input (Pin 16) to AGND (Pin 9)
VOCDDQ
27
V
Switch Node (Pin 19)
VSWDDQ
−4.0 (<100 ns),
0.3 (dc), 32
V
PGND (Pin 22), VTTGND (Pin 5) to AGND (Pin 9)
VGND
−0.3, 0.3
V
Thermal Characteristics
DFN−22 Plastic Package
Thermal Resistance, Junction−to−Ambient
RJA
35
C/W
Operating Junction Temperature Range
TJ
0 to +150
C
Operating Ambient Temperature Range
TA
−40 to +85
C
Storage Temperature Range
Tstg
−55 to +150
C
Moisture Sensitivity Level
MSL
2
−
Power Supply Voltage (Pin 11, 20) to AGND (Pin 9)
High−Side Gate Drive Supply: BOOST (Pin 17) to SWDDQ (Pin 19)
High−Side FET Gate Drive Voltage: TGDDQ (Pin 18) to SWDDQ (Pin 19)
Input/Output Pins to AGND (Pin 9)
Pins 1−4, 6−8, 10, 12−15, 21
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) ≤2.0 kV per JEDEC standard: JESD22–A114.
Machine Model (MM) ≤200 V per JEDEC standard: JESD22–A115.
2. Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78.
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NCP5214
ELECTRICAL CHARACTERISTICS (VIN = 12 V, TA = −40 to 85C, VCCA = VCCP = VBOOST − VSWDDQ = 5.0 V, L = 1.8 H,
COUT1 = 150 F x 2, COUT2 = 22 F x 2, RL1 = 1.0 k, R1 = 4.3 k, R2 = 3.3 k, RZ1 = 6.2 k, RZ2 = 130 , CP1 = 100 pF, CZ1 = 2.2 nF,
CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at TA = 25C.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
VIN
−
4.5
−
24
V
VCCA Operating Voltage
VCCA
−
4.5
5.0
5.5
V
VCCP Operating Voltage
VCCP
−
4.5
5.0
5.5
V
VCCA Quiescent Supply Current in S0
IVCCA_S0
VDDQEN = 5.0 V, VTTEN = 5.0 V
−
5.0
10
mA
VCCA Quiescent Supply Current in S3
IVCCA_S3
VDDQEN = 5.0 V, VTTEN = 0 V
−
−
5.0
mA
VCCA Shutdown Current
IVCCA_SD
VDDQEN = 0 V, VTTEN = 0 V
−
−
4.0
A
VCCP Quiescent Supply Current in S0
IVCCP_S0
VDDQEN = 5.0 V, VTTEN = 5.0 V,
TGDDQ and BGDDQ Open
−
−
20
mA
VCCP Quiescent Supply Current in S3
IVCCP_S3
VDDQEN = 5.0 V, VTTEN = 0 V,
TGDDQ and BGDDQ Open
−
−
20
mA
VCCP Shutdown Current
IVCCP_SD
VDDQEN = 0 V, VTTEN = 0 V
−
−
1.0
A
VCCAUV−
Falling Edge
−
3.7
4.1
V
SUPPLY VOLTAGE
Input Voltage
SUPPLY CURRENT
UNDERVOLTAGE MONITOR
VCCA UVLO Lower Threshold
VCCA UVLO Hysteresis
VCCAUVHYS
−
−
0.35
−
V
VOCDDQ UVLO Upper Threshold
VOCDDQUV+
Rising Edge
−
3.5
−
V
VOCDDQUVHYS
−
−
0.2
−
V
VOCDDQ UVLO Hysteresis
THERMAL SHUTDOWN
TSD
(Note 3)
−
150
−
C
TSDHYS
(Note 3)
−
25
−
C
VFBDDQ
TA = 25°C
TA = −40 to 85°C
0.788
0.780
0.8
0.8
0.812
0.820
V
Ifb
VFBDDQ = 0.8 V
−
−
1.0
A
Oscillator Frequency
FSW
−
340
400
460
kHz
Ramp Amplitude Voltage
Vramp
VIN = 5.0 V (Note 3)
−
1.25
−
V
dVRAMP/dVIN
−
−
45
−
mV/V
IOC
VOCDDQ = 4.0 V
23
35
47
A
OCDDQ Pin Current Sink Temperature
Coefficient
TCIOC
TA = −40 to 85°C
−
3200
−
ppm/
C
Minimum On Time
tonmin
−
−
150
−
ns
Maximum Duty Cycle
Dmax
VIN = 5.0 V
VIN = 15 V
VIN = 24 V
−
−
−
90
50
32
−
−
−
%
Iss
VDDQEN = 5.0 V, Vss = 0 V
3.5
5.0
6.5
A
Overvoltage Trip Threshold
FBOVPth
With Respect to Error
Comparator Threshold of 0.8 V
115
130
−
%
Undervoltage Trip Threshold
FBUVPth
With Respect to Error
Comparator Threshold of 0.8 V
−
65
75
%
Thermal Trip Point
Hysteresis
VDDQ SWITCHING REGULATOR
FBDDQ Feedback Voltage, Control Loop in
Regulation
Feedback Input Current
Ramp Amplitude to VIN Ratio
OCDDQ Pin Current Sink
Soft−Start Current
3. Guaranteed by design, not tested in production.
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NCP5214
ELECTRICAL CHARACTERISTICS (continued) (VIN = 12 V, TA = −40 to 85C, VCCA = VCCP = VBOOST − VSWDDQ = 5.0 V,
L = 1.8 H, COUT1 = 150 F x 2, COUT2 = 22 F x 2, RL1 = 1.0 k, R1 = 4.3 k, R2 = 3.3 k, RZ1 = 6.2 k, RZ2 = 130 , CP1 = 100 pF,
CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at TA = 25C.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
GAIN
(Note 4)
−
70
−
dB
Unity Gain Bandwidth
Ft
COMP_GND = 220 nF,
1.0 in Series (Note 4)
−
2.0
−
MHz
Slew Rate
SR
(Note 4)
−
3.0
−
V/S
TGDDQ Gate Pull−HIGH Resistance
RH_TG
VBOOST − VSWDDQ = 5.0 V,
VTGDDQ − VSWDDQ = 4.0 V
−
1.8
−
TGDDQ Gate Pull−LOW Resistance
RL_TG
VBOOST − VSWDDQ = 5.0 V,
VTGDDQ − VSWDDQ = 1.0 V
−
1.8
−
BGDDQ Gate Pull−HIGH Resistance
RH_BG
VCCP = 5.0 V, VBGDDQ = 4.0 V
−
1.8
−
BGDDQ Gate Pull−LOW Resistance
RL_BG
VCCP = 5.0 V, VBGDDQ = 1.0 V
−
0.9
−
dVTT0
1/2VDDQREF – VTT,
VDDQREF = 2.5 V,
IVTT = 0 to 2.4 A
(Sink Current)
IVTT = 0 to –2.4 A
(Source Current)
ERROR AMPLIFIER
DC Gain
GATE DRIVERS
VTT ACTIVE TERMINATOR
VTT with Respect to 1/2VDDQREF
1/2VDDQREF – VTT,
VDDQREF = 1.8 V,
IVTT = 0 to 2.0 A
(Sink Current)
IVTT = 0 to –2.0 A
(Source Current)
DDQREF Input Resistance
mV
−30
−
−
−
−
30
mV
−30
−
−
−
−
30
DDQREF_R
−
−
50
−
k
Source Current Limit
ILIMVTsrc
−
2.5
3.0
−
A
Sink Current Limit
ILIMVTsnk
−
2.5
3.0
−
A
Soft−Start Source Current Limit
ILIMVTSS
−
−
1.0
−
A
Maximum Soft−Start Time
tssvttmax
−
−
1.0
−
ms
VTTREF Source Current
IVTTR
VDDQREF = 1.8 V or 2.5 V
15
−
−
mA
VTTREF Accuracy Referred to 1/2VDDQREF
dVTTR
1/2VDDQREF – VTTR,
VDDQREF = 2.5 V,
IVTTR = 0 mA to 15 mA
−25
−
25
mV
1/2VDDQREF – VTTR,
VDDQREF = 1.8 V,
IVTTR = 0 mA to 15 mA
−18
−
18
mV
VTTREF OUTPUT
4. Guaranteed by design, not tested in production.
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NCP5214
ELECTRICAL CHARACTERISTICS (continued) (VIN = 12 V, TA = −40 to 85C, VCCA = VCCP = VBOOST − VSWDDQ = 5.0 V,
L = 1.8 H, COUT1 = 150 F x 2, COUT2 = 22 F x 2, RL1 = 1.0 k, R1 = 4.3 k, R2 = 3.3 k, RZ1 = 6.2 k, RZ2 = 130 , CP1 = 100 pF,
CZ1 = 2.2 nF, CZ2 = 4.7 nF, for min/max values unless otherwise noted. Typical values are at TA = 25C.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
VDDQEN Pin Threshold High
VDDQEN_H
−
1.4
−
−
V
VDDQEN Pin Threshold Low
VDDQEN_L
−
−
−
0.5
V
VDDQEN Pin Input Current
IIN_
VDDQEN
VDDQEN = 5.0 V
−
−
0.5
A
VTTEN Pin Threshold High
VTTEN_H
−
1.4
−
−
V
VTTEN Pin Threshold Low
VTTEN_L
−
−
−
0.5
V
VTTEN Pin Input Current
IIN_VTTEN
VDDQEN = VTTEN = 5.0 V
−
−
0.5
A
PGOOD Pin ON Resistance
PGOOD_R
I_PGOOD = 5.0 mA
−
80
−
PGOOD Pin OFF Current
PGOOD_LK
−
−
−
1.0
A
thold
(Note 5)
−
−
200
s
CONTROL SECTION
PGOOD LOW−to−HIGH Hold Time, for S5 to S0
5. Guaranteed by design, not tested in production.
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NCP5214
DETAILED OPERATING DESCRIPTION
General
VDDQ output voltage is divided down and fed back to the
inverting input of an internal error amplifier through
FBDDQ pin to close the loop at VDDQ = VFBDDQ ×
(1 + R2/R1). This amplifier compares the feedback voltage
with an internal VREF (= 0.800 V) to generate an error
signal for the PWM comparator. This error signal is further
compared with a fixed frequency RAMP waveform
derived from the internal oscillator to generate a
pulse−width−modulated signal. This PWM signal drives
the external N−Channel Power FETs via the TGDDQ and
BGDDQ pins. External inductor L and capacitor COUT1
filter the output waveform. The VDDQ output voltage
ramps up at a pre−defined soft−start rate when the IC enters
state S0 from S5. When in normal mode, and regulation of
VDDQ is detected, signal INREGDDQ will go HIGH to
notify the control logic block.
Input voltage feedforward is implemented to the RAMP
signal generation to reject the effect of wide input voltage
variation. With input voltage feedforward, the amplitude of
the RAMP is proportional to the input voltage.
For enhanced efficiency, an active synchronous switch is
used to eliminate the conduction loss contributed by the
forward voltage of a diode or Schottky diode rectifier.
Adaptive non−overlap timing control of the
complementary gate drive output signals is provided to
reduce large shoot−through current that degrades
efficiency.
The NCP5214 2−in−1 Notebook DDR Power Controller
combines the efficiency of a PWM controller for the
VDDQ supply, with the simplicity of using a linear
regulator for the VTT termination voltage power supply.
The VDDQ output can be adjusted through the external
potential divider, while the VTT is internally set to track
half VDDQ.
The inclusion of VDDQ power good voltage monitor,
soft−start, VDDQ overcurrent protection, VDDQ
overvoltage and undervoltage protections, supply
undervoltage monitor, and thermal shutdown makes this
device a total power solution for high current DDR memory
system. The IC is packaged in DFN−22.
Control Logic
The internal control logic is powered by VCCA. The IC
is enabled whenever VDDQEN is high (exceed 1.4 V). An
internal bandgap voltage, VREF, is then generated. Once
VREF reaches its regulation voltage, an internal signal
VREFGD will be asserted. This transition wakes up the
supply undervoltage monitor blocks, which will assert
VCCAGD if VCCA voltage is within certain preset levels.
The control logic accepts external signals at VCCA,
OCDDQ, VDDQEN, VTTEN, and FPWM pins to control
the operating state of the VDDQ and VTT regulators in
accordance with Table 1. A timing diagram is shown in
Figure 3.
Tolerance of VDDQ
VDDQ Switching Regulator in Normal Mode (S0)
The tolerance of VFBDDQ and the ratio of external
resistor divider R1/R2 both impact the precision of VDDQ.
With the control loop in regulation, VDDQ = VFBDDQ ×
(1 + R1/R2). With a worst case (for all valid operating
conditions) VFBDDQ tolerance of 1.5%, a worst case
range of 2.5% for VDDQ = 1.8 V will be assured if the
ratio R1/R2 is specified as 1.2500 1%.
The VDDQ regulator is a switching synchronous
rectification buck controller directly driving two external
N−Channel power FETs. An external resistor divider sets
the nominal output voltage. The control architecture is
voltage mode fixed frequency PWM with external
compensation and with switching frequency fixed at
400 kHz 15%. As can be observed from Figure 1, the
Table 1. State, Operation, Input and Output Condition Table
Input Conditions
Operating Conditions
Output Conditions
Mode
VCCA
VOCDDQ
VDDQEN
VTTEN
FPWM
VDDQ
VTTREF
VTT
TGDDQ
BGDDQ
PGOOD
S5
Low
X
X
X
X
H−Z
H−Z
H−Z
Low
Low
Low
S5
X
Low
X
X
X
H−Z
H−Z
H−Z
Low
Low
Low
S0
High
High
High
High
X
Normal
Normal
Normal
Normal
Normal
H−Z
S3
High
High
High
Low
High
Standby
Normal
H−Z
Standby
(Power−
saving)
Standby
(Power−
saving)
H−Z
S3
High
High
High
Low
Low
Normal
Normal
H−Z
Normal
Normal
H−Z
S5
X
X
Low
X
X
H−Z
H−Z
H−Z
Low
Low
Low
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NCP5214
VDDQ Regulator in Standby Mode (S3)
This regulator is stable with any value of output capacitor
greater than 30 F. The VTT regulator will have an internal
soft−start when it is transited from disable to enable.
During the VTT soft−start, a current limit is used as a
current source to charge up the VTT output capacitor. The
current limit is initially 1.0 A during VTT soft−start. It is
then increased to 2.5 A after 1.0 ms or VTT output is in
regulation, whichever is earlier.
During state S3, a power−saving mode is activated when
the FPWM pin is pulled to VCCA. In power−saving mode,
the switching frequency is reduced with the VDDQ output
current and the low−side FET is turned off after the
detection of negative inductor current, so as to enhance the
efficiency of the VDDQ regulator at light loads. The
switching frequency can be reduced smoothly until it
reaches the minimum frequency at about 15 kHz.
Therefore, perceptible audible noise can be avoided at light
load condition.
In power−saving mode, the low−side MOSFET is turned
off after the detection of negative inductor current and the
converter cannot sink current. The power−saving mode can
be disabled by pulling the FPWM pin to ground. Then, the
converter operates in forced−PWM mode with fixed
switching frequency and ability to sink current.
VTT Active Terminator in Standby Mode (S3)
VTT output is high−impedance in S3 mode.
Fault Protection of VTT Active Terminator
To provide protection for the internal FETs, bidirectional
current limit is implemented, preset at the minimum of
2.5 A magnitude.
Thermal Consideration of VTT Active Terminator
The VTT terminator is designed to handle large transient
output currents. If large currents are required for very long
duration, then care should be taken to ensure the maximum
junction temperature is not exceeded. The 5x6 DFN−22 has
a thermal resistance of 35C/W (dependent on air flow,
grade of copper, and number of vias). In order to take full
advantage from this thermal capability of this package, the
thermal pad underneath must be soldered directly onto a
PCB metal substrate to allow good thermal contact.
Fault Protection of VDDQ Regulator
During state S0 and S3, external resistor (RL1) sets the
current limit for the high−side switch. An internal 35 A
current sink (IOC) at OCDDQ pin establishes a voltage
drop across this resistor. Besides, an offset voltage at the
magnitude of RL1xIOC is also developed at the
non−inverting input of the current limit comparator. The
voltage at the non−inverting input is compared to the
voltage at SWDDQ pin when the high−side gate drive is
high after a fixed period of blanking time (150 ns) to avoid
false current limit triggering. When the voltage at SWDDQ
is lower than that at the non−inverting input for a
consecutive 15 internal clock cycles, an overcurrent
condition occurs, during which, all outputs will be latched
off to protect against a short−to−ground condition on
SWDDQ or VDDQ. The IC will be reset once VCCA or
VDDQEN is cycled.
VTTREF Output
The VTTREF output tracks VDDQREF/2 at 2%
accuracy. It has source current capability of up to 15 mA.
VTTREF should be bypassed to analog ground of the
device by 1.0 F ceramic capacitor for stable operation.
The VTTREF is turned on as long as VDDQEN is pulled
high. In S0 mode, VTTREF soft−starts with VDDQ and
tracks VDDQREF/2. In S3 mode, VTTREF is kept on with
VDDQ. VTTREF is turned off only in S4/S5 like VDDQ
output.
Feedback Compensation of VDDQ Regulator
The compensation network is shown in Figure 2.
Supply Voltage Undervoltage Monitor
VTT Active Terminator in Normal Mode (S0)
The IC continuously monitors VCCA and VIN through
VCCA pin and OCDDQ pin respectively. VCCAGD is set
HIGH if VCCA is higher than its preset threshold (derived
from VREF with hysteresis). The IC will enter S5 state if
VCCA fails while in S0 and both VDDQEN and VTTEN
remain HIGH.
The VTT active terminator is a two−quadrant linear
regulator with two internal N−channel power FETs. It is
capable of sinking and sourcing at least 1.5 A continuous
current and up to 2.4 A transient peak current. It is activated
in normal mode in state S0 when the VTTEN pin is HIGH
and VDDQ is in regulation. Its input power path is from
VDDQ with the internal FETs gate drive power derived
from VCCA. The VTT internal reference voltage is derived
from the DDQREF pin. The VTT output is set to VDDQ/2
when VTT output is connecting to the FBVTT pin directly.
Thermal Shutdown
When the chip junction temperature exceeds 150C, the
entire IC is shutdown. The IC resumes normal operation
only after the junction temperature dropping below 125C.
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NCP5214
APPLICATION INFORMATION
Overcurrent Protection
To avoid false triggering the overcurrent protection in
normal operating load range, calculate the RL1 value from
the above equation with the following condition:
1. The minimum IOC value from the specification
table,
2. The maximum Rds(on) of the MOSFET used at
the highest junction temperature,
3. Determine ILIMIT for ILIMIT > IOUT(MAX) + IL/2.
The OCP circuit is configured to set the current limit for
the current flowing through the high−side FET and
inductor during S0 and S3. The overcurrent tripping level
is programmed by an external resistor RL1 connected
between the OCDDQ pin and drain of the high−side FET.
An internal 35 A current sink (IOC) at pin OCDDQ
establishes a voltage drop across the resistor RL1 at a
magnitude of RL1xIOC. Besides, an additional offset
voltage VOFFSET of 25 mV is developed at the
non−inverting input of the current limit comparator. The
voltage at the non−inverting input is then compared to the
voltage at SWDDQ pin when the high−side gate drive is
high after a fixed period of blanking time (150 ns) to avoid
false current limit triggering. When the voltage at SWDDQ
is lower than the voltage at the non−inverting input of the
current limit comparator for a consecutive 15 internal clock
cycles, an overcurrent condition occurs, during which, all
outputs will be latched off to protect against a
short−to−ground condition on SWDDQ or VDDQ. i.e., the
voltage drop across the Rds(on) of high−side FET developed
by the drain current is larger than the voltage drop across
RL1 plus the additional offset voltage, the OCP is triggered
and the device will be latched off.
The overcurrent protection will trip when a peak inductor
current hit the ILIMIT determined by the equation:
ILIMIT Besides, a decoupling capacitor CDCPL should be added
closed to the lead of the current limit setting resistor RL1
which connected to the drain of the high−side MOSFET.
Soft−Start
A VDDQ soft−start feature is incorporated in the device
to prevent surge current from power supply and output
voltage overshot during power up. When VDDQEN,
VCCA, and VOCDDQ rise above their respective upper
threshold voltages, the external soft−start capacitor Css
will be charged up by a constant current source, Iss. When
the soft−start voltage (Vcss) rises above the SS_EN voltage
(50 mV), the BGDDQ and TGDDQ will start switching
and VDDQ output will ramp up. When the soft−start
voltage reaches the SS_OK voltage (Vref + 50 mV), the
soft− start of VDDQ is finished. The Css will continue to
charge up until it reaches about 2.5 V to 3.0 V.
The soft−start time tss can be programmed according to
the following equation:
RL1 IOC VOFFSET
Rds(on)
tss Since the MOSFET Rds(on) varies with temperature as
current flows through the MOSFET increases, the OCP trip
point will also varies with the MOSFET Rds(on)
temperature variation. The IOC temperature coefficient of
3200 ppm is used to compensate the Rds(on) temperature
variation.
0.8 Css
Iss
Ceramic capacitors with low tolerance and low
temperature coefficient, such as B, X5R, X7R ceramic
capacitors are recommended to be used as the Css. Ceramic
capacitors with Y5V temperature characteristic are not
recommended.
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11
NCP5214
VCCA
VIN
(VOCDDQ)
VDDQEN
VTTEN is
Don’t Care
in S5
VTTEN
VDDQ
VDDQ
Soft−start
10
ms
VTT Soft−start
1.0 ms
VTT
VTT in H−Z
VTT Soft−start
1.0 ms
S3
S0
VTTREF
PGOOD
thold 200 s
Operating
Mode
S5
VCCA goes
above 4.4 V to
enable the IC.
VDDQEN goes HIGH,
VDDQ and VTTREF
are enabled but not
activated until VIN
goes above threshold
of 3.5 V. VTTEN goes
HIGH, VTT is enabled
but not activated until
VDDQ is good.
S0
PGOOD
goes HIGH.
VTTEN goes LOW
to activate S3 mode
and to turn off VTT.
INREGDDQ goes
HIGH, VTT goes into
normal mode.
VTTEN goes
HIGH, VTT goes
into normal mode.
VIN goes above the
threshold, the VDDQ
and VTTREF go into
normal mode.
Figure 3. Powerup and Powerdown Timing Diagram
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12
S5
Both VDDQEN and
VTTEN go LOW to
trigger S5 mode;
VDDQ, VTT, VTTREF
are disabled, then
INREGDDQ and
PGOOD goes LOW.
NCP5214
PACKAGE DIMENSIONS
DFN−22
MN SUFFIX
CASE 506AF−01
ISSUE O
A
D
B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINALS AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1 LOCATION
E
0.15 C
0.15 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.10 C
A
0.08 C
SIDE VIEW
A1
(A3)
C
SEATING
PLANE
D2
22 X
22 X
L
1
e
11
E2
K
22
12
22 X
b
0.10 C A B
0.05 C NOTE 3
BOTTOM VIEW
SOLDERING FOOTPRINT
4.200
0.165
0.8050
0.0316
5.310
0.209
3.700
0.146
0.280
0.011
0.5000
0.0196
SCALE 8:1
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13
mm inches
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
6.00 BSC
3.98
4.28
5.00 BSC
2.98
3.28
0.50 BSC
0.20
−−−
0.50
0.60
NCP5214
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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NCP5214/D
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