MOTOROLA MCM69C433 16k x 64 cam Datasheet

Freescale Semiconductor, Inc.
MOTOROLA
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SEMICONDUCTOR TECHNICAL DATA
MCM69C433
SCM69C433
16K x 64 CAM
Freescale Semiconductor, Inc...
The MCM69C433 is a flexible content–addressable memory (CAM) that can
contain 16K entries of 64 bits each. The widths of the match field and the output
field are programmable, and the match time is designed to be 240 ns. As a result,
the MCM69C433 is well suited for datacom applications such as Virtual Path
Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to
OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup
in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C433 is
user–defined, with a trade–off between the time between the match request rate
and the rate of new entries added to the CAM per second.
•
•
•
•
•
•
•
•
•
•
•
•
•
16K Entries
240 ns Match Time
Mask Register to “Don’t Care” Selected Bits
O
Depth Expansion by Cascading Multiple Devices
IC
66 MHz Maximum Clock Rate
EM
S
Programmable Match and Output Field Widths
LE
Concurrent Matching of Virtual Path Circuits and Virtual Connection
A
Circuits in ATM Mode
SC
Separate Ports for Control and Match Operations E
E is Empty
450 ns Insertion Time if 1 of 14 Entry Queue Locations
FR
120 ms Initialization Time After Fast Insertion
(at Power–Up Only)
BY
Single 3.3 V ±5% Supply
ED
IEEE Standard 1149.1 Test Port
(JTAG)
V
I
100–Pin TQFP Package H
Related Products
R,
O
CT
U
ND
C
IN
.
TQ PACKAGE
TQFP
CASE 983A–01
C
AR
— MCM69C232, MCM69C432, MCM69C233 (CAMs)
CONTROL PORT
MATCH PORT
14 x 64
ENTRY QUEUE
MQ31 – MQ0
A2 – A0
DQ15 – DQ0
SEL
STATUS/
CONTROL
LOGIC
WE
IRQ
DTACK
RESET
16K x 64
CAM
TABLE
K
G
LH/SM
LL
INPUT REG
KMODE
MC
MS
VPC
REV 3
6/11/01

Motorola, Inc. 2001
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MQ9
MQ8
VSS
VDD
MQ7
MQ6
MQ5
MQ4
VSS
VDD
MQ3
MQ2
MQ1
MQ0
VSS
VDD
DQ15
DQ14
DQ13
DQ12
VSS
VDD
DQ11
DQ10
DQ9
DQ8
VDD
VSS
DQ7
DQ6
CH
R
A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ED
V
I
BY
EE
R
F
LE
A
SC
S
O
IC
EM
MQ22
MQ23
VSS
VDD
MQ24
MQ25
MQ26
MQ27
VSS
VDD
MQ28
MQ29
MQ30
MQ31
VSS
VDD
MC
VPC
MS
G
VSS
VDD
DTACK
IRQ
RESET
TDO
VDD
VSS
TCK
TMS
R,
O
CT
U
ND
C
IN
.
DQ5
DQ4
VDD
VSS
DQ3
DQ2
DQ1
DQ0
K
VSS
VDD
A2
A1
A0
WE
SEL
KMODE
VDD
TRST
TDI
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MQ10
MQ11
VSS
VDD
MQ12
MQ13
MQ14
MQ15
LL
VDD
VSS
LH/SM
MQ16
MQ17
MQ18
MQ19
VDD
VSS
MQ20
MQ21
PIN ASSIGNMENT
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PIN DESCRIPTIONS
Pin Locations
Symbol
Type
42 – 44
A2 – A0
Input
58
DTACK
Output
17 – 20, 23 – 26,
29 – 32, 35 – 38
DQ15 – DQ0
I/O
Description
3–bit control port address bus.
Control port data transfer acknowledge (Open Drain).
16–bit bidirectional control port data bus.
61
G
Input
57
IRQ
Output
39
K
Input
Interface Clock, max frequency of 66 MHz.
47
KMODE
Input
See Note.
89
LH/SM
Input
Latch High/Start Match. Initiates match sequence on match data present on
MQ31 – MQ0.
92
LL
Input
Latch Low. Latches low order bits if match width is > 32 bits.
64
MC
67 – 70, 73 – 76,
79 – 82, 85 – 88,
93 – 96, 99, 100,
1, 2, 5 – 8, 11 – 14
MQ31 – MQ0
62
MS
56
RESET
46
SEL
52
TCK
50
TDI
55
TDO
TMS
CH
R
A TRST
51
49
Output Enable control of MQ31 – MQ0.
Control port interrupt (Open Drain).
C
IN
.
R,
O
CT
Output
Match Complete (Open Drain).
U
D
I/O
32–bit common I/O CAM data. N
Used for input of match RAM and data RAM
O
values.
IC
M
SE
E
Output
Match Successful
L (Open Drain).
A
Input
Resets
SCchip to a known state.
E
Input
EControl port chip select, active low.
R
Input F
Test Clock, part of JTAG interface.
Y
BInput
Test Data In, part of JTAG interface.
ED Output
V
I
Test Data Out, part of JTAG interface.
Input
Test Mode Select, part of JTAG interface.
Input
Tap Reset part of JTAG interface.
63
VPC
Output
Virtual Path Circuit. Used in ATM mode to indicate a virtual path circuit match has
occurred (Open Drain).
45
WE
Input
Control port Write Enable.
4, 10, 16, 22, 27, 33,
41, 48, 54, 59, 65, 71,
77, 84, 91, 97
VDD
Supply
Power Supply: 3.3 V ±5%.
3, 9, 15, 21, 28, 34,
40, 53, 60, 66, 72,
78, 83, 90, 98
VSS
Supply
Ground.
NOTE: Assert KMODE 1 clock cycle after RESET is deasserted.
K
RESET
KMODE
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ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating
Symbol
Value
Unit
VDD
4.6
V
Voltage Relative to VSS (see Note 2)
Vin
–0.5 to VDD + 3 V
V
Output Current per Pin
Iout
±20
mA
Package Power Dissipation (see Note 3)
PD
—
W
Temperature Under Bias (see Note 3)
Commercial
Industrial
Tbias
Supply Voltage (see Note 2)
Operating Temperature
Commercial
Industrial
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Storage Temperature
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
°C
–10 to 85
–40 to 85
TA
0 to 70
–40 to 85
°C
Tstg
–55 to 125
°C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability will be dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
O
IC
EM
R,
O
CT
U
ND
S
E
L
DC OPERATING CONDITIONS
CA AND CHARACTERISTICS
(VDD = 3.3 V ±5%, TS
< 120°C, Unless Otherwise Noted)
J
EE
R
RECOMMENDED OPERATING CONDITIONSF(Voltages Referenced to VSS = 0 V)
Y
Symbol
Min
Parameter B
D
E
Power Supply Voltage
VDD
3.1
IV
H
Operating Temperature (Junction)
T
—
J
C
R
Input Low Voltage
VIL
–0.5*
A
C
IN
Typ
.
Max
Unit
3.3
3.5
V
—
120
°C
0
0.8
V
3
5.5
V
Symbol
Min
Max
Unit
Active Power Supply Current
IDDA
—
300
mA
Input Leakage Current (0 V
Ilkg(I)
—
±1
µA
Ilkg(O)
—
±1
µA
Output Low Voltage (IOL = 8 mA)
VOL
—
0.4
V
Output High Voltage (IOH = –4 mA)
VOH
2.4
—
V
Input High Voltage
* VIL (min) = –3.0 V ac (pulse width
VIH
v 20 ns).
2.2
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
v Vin v VDD)
Output Leakage Current (0 V v Vin v VDD)
PACKAGE THERMAL CHARACTERISTICS
Symbol
Max
Unit
Thermal Resistance Junction to Ambient (200 lfpm, 4 Layer Board) (see Note 2)
Rating
RθJA
36
°C/W
Thermal Resistance Junction to Board (Bottom) (see Note 3)
RθJB
19
°C/W
Thermal Resistance Junction to Case (Top) (see Note 4)
RθJC
8
°C/W
NOTES:
1. RAM junction temperature is a function of on–chip power dissipation, package thermal impedance, mounting site temperature, and
mounting site thermal impedance.
2. Per SEMI G38–87.
3. Indicates the average thermal impedance between the die and the mounting surface.
4. Indicates the average thermal impedance between the die and the case top surface. Measured via the cold plate method (MIL SPEC–883
Method 1012.1).
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CAPACITANCE (Periodically Sampled Rather Than 100% Tested)
Symbol
Min
Max
Unit
Input Capacitance
Parameter
Cin
—
5
pF
I/O Capacitance
CI/O
—
8
pF
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JUNCTION TO AMBIENT THERMAL CHARACTERISTICS
Board
Air (LFPM)
θJA (°C/W)
1 Layer
0
43
1 Layer
200
36
4 Layer
0
33
4 Layer
200
29
C
IN
.
R,
O
AC OPERATING CONDITIONS AND CHARACTERISTICS
CT
U
(VDD = 3.3 V ±5%, TJ < 120°C, Unless Otherwise
D Noted)
N
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing
COReference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
I
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Output
MLoad . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
SE
LE
CONTROL PORT TIMINGS
A
(Voltages Referenced to VSS = 0 V, Max’s are tKHKH Dependent
SCand Listed Values are for tKHKH = 15 ns)
E
E
Parameter
Symbol
Min
Max
Unit
Notes
FR
Address Valid to SEL Low
tAVSL
0
—
ns
BY
D
DTACK Low to Address Invalid
tDTLAX
0
—
ns
VE
I
Data Valid to Select Low
tDVSL
0
—
ns
CH
R
DTACK Low to Data Invalid
tDTLDX
0
—
ns
A
Output Valid to DTACK Low
tQVDTL
2
—
ns
WE Valid to Select Low
tWVSL
0
—
ns
DTACK Low to WE High
tDTLWH
0
—
ns
WE High to Output Active
tWHQX
2
—
ns
Select Low to DTACK Low
tSLDTL
10
—
ns
Select High to DTACK High
tSHDTH
10
—
ns
tDTLIL
10
—
ns
tILIH
20
—
ns
DTACK Low to Select High
tDTLSH
0
—
ns
DTACK High to Select Low
tDTHSL
0
—
ns
Address Valid to Output Valid
tAVQV
—
8
ns
Select High to Output High Impedance
tSHQZ
—
8
ns
RESET Low to RESET High
tRLRH
2 x tKHKH
—
ns
DTACK Low to IRQ Low
IRQ Low to IRQ High
1
NOTE:
1. DTACK is delayed when a write is attempted during certain operations. See Functional Description.
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MATCH PORT TIMINGS
(Voltages Referenced to VSS = 0 V, Max’s are tKHKH Dependent and Listed Values are for tKHKH = 15 ns)
Parameter
Symbol
Min
Max
Unit
Clock Cycle Time
tKHKH
15
250
ns
Clock High Time
tKHKL
6
244
ns
Clock Low Time
tKLKH
6
244
ns
LHSM or LL Low to Clock High
tLLKH
3
—
ns
Clock High to LHSM or LL High
tKHLH
1
—
ns
tMQVKH
8
—
ns
—
ns
13
ns
10
ns
7
ns
MQ Input Data Valid to Clock High
Clock High to Match Data Invalid
Clock High to MQ Valid
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Clock High to MC High
Clock High to MC Low
Clock High to MS Low
Clock High to MS High
Clock High to VPC Low
Clock High to VPC High
G Low to MQ Active
G High to MQ High Impedance
LH/SM Low to LH/SM Low
CH
R
A
IN
,
tKHMQV
R —
O
tKHMCH
—
CT
U
tKHMCL
—
ND
tKHMQX
ED
V
I
BY
EE
R
F
LE
A
SC
S
O
IC
EM
2
C.
tKHMSL
—
8
ns
tKHMSH
—
5
ns
tKHVPL
—
8
ns
tKHVPH
—
5
ns
tGLMQX
—
3.8
ns
tGHMQZ
—
5
ns
tSMSM
22
—
cycles
RL = 50 Ω
OUTPUT
Z0 = 50 Ω
VL = 1.5 V
Figure 1. AC Test Load
3.3 V
RH
MCM69C433 OUTPUT PIN
FANOUT TO LOAD DEVICES
NOTES:
1. For IRQ, DTACK, MS, MC, and VPC; RH = 200 Ω .
2. If multiple MCM69C433s are used, RH should be placed as
close to the load devices as possible.
Figure 2. Pullup for Open Drain Outputs
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FUNCTIONAL DESCRIPTION
the initialization operation is run if required. Normal matching
operations can then begin. A delete operation is provided to
remove stale data from the CAM table.
Several error codes are defined in the details of the
instruction set. When an error occurs, its corresponding code
is written into the error register and the error bit in the flag
register is set. The error bit is cleared and the error register is
set to FFFF16 by the next write to the operation register.
The MCM69C433 is a flexible content–addressable
memory (CAM) that can contain 16K entries of 64 bits each.
The widths of the match field and the output field are programmable, and the match time is designed to be 240 ns. As
a result, the MCM69C433 is well suited for datacom
applications such as Virtual Path Identifier/Virtual Circuit
Identifier (VPI/VCI) translation in ATM switches up to OC12
(622 Mbps) data rates and Media Access Control (MAC) adPROGRAMMING MODEL
dress lookup in Ethernet/Fast Ethernet bridges. The match
duty cycle of the MCM69C433 is determined by the user,
Three types of registers are accessible through the
with a trade–off between the match request rate and the rate
MCM69C433’s control port: I/O registers, an operation regof entries added to/deleted from the CAM. With the minimum
ister, and result/condition code registers.
Each register is
C.
required 60 ns of idle time between matches, a typical value
16 bits in length.
N
of 370 insertions or deletions per second can be made. See
,I
R
Figure 3 for a graph of the relationship between insertion/
ADDRESS
TO BIT NUMBER
deletion pairs and match duty cycle.
REGISTER NAME
OFFSET
C
In its basic operating mode, the MCM69C433 reads a data
15
0
U
D
input word through MQ bus and compares it to all the entries
I/O REGISTER 0N
0
O
in its CAM table. The MC pin is always asserted after the
IC 1
comparisons have been made. If a match is found, the MS
I/O REGISTER
1
M
E
pin is asserted, and the data associated with the matching
S
entry is output on the MQ bus. If no match is found, the MQ
2
E I/O REGISTER 2
bus remains in a high–impedance state to facilitate depth ex-AL
pansion via the cascading of multiple CAMs.
I/O REGISTER 3
3
SC
E
Before the basic operating mode can be entered,Eseveral
R width
start–up functions must be performed. First, theFoutput
OPERATION REGISTER
4
and match width must be designated Y
by setting the
B must be made
global–mask register. Second, a choice
FLAG REGISTER
5
D
between buffered–entry mode and E
fast–entry mode. Next,
IVmust be loaded into the
the 64–bit match/output data pairs
ERROR CODE REGISTER
6
H
table. Depending on the entry
mode of choice, the table may
C
have to be initialized. Optionally,
the “almost full” point may
AR
INTERRUPT REGISTER
7
be set to provide warning of impending table overflow.
The input bits to be compared are defined by the global–
FLAG BIT DEFINITIONS
mask register. The mask bits that are 0 correspond to the bits
that are used in the match operation.Typically, the bits that
Bit 0: 1 = At least one interrupt enabled,
are used in matching are the high order bits in the 64–bit
0 = No interrupts enabled
CAM table entries, and the bits that are used as outputs are
Bit 1: 1 = Last control port match successful,
the low order bits. While any of the bits can be defined as
0 = Last match unsuccessful
match bits, the low order 32 bits of an entry are always driven
Bit 2: 1 = Table initialized, 0 = Table not initialized
on the MQ bus as output data.
Bit 3: 1 = Buffered–entry mode, 0 = Fast–entry mode
The choice of entry mode is a trade–off between speed of
Bit 4: 1 = Entry queue empty,
entry and latency before matching operations can begin. In a
0 = Entry queue not empty
typical application, the fast–entry mode will be used to load
Bit 5: 1 = Entry queue full, 0 = Entry queue not full
the initial values into the CAM table. Subsequently, the
Bit 6: 1 = CAM table full, 0 = CAM table not full
initialize–table operation, which takes 120 ms, must be
Bit 7: 1 = Error condition set, 0 = No error
executed to establish the required linkages and relationships
Bit 8: 1 = Table almost full, 0 = Table not almost full
among the entries. After match operations have begun, the
Bit 9: 1 = ATM mode, 0 = Standard mode
buffered–entry mode should be used to enter new values
Bit 10: 1 = Last operation complete, 0 = Not yet complete
dynamically; even one addition in fast–entry mode will disable matching until the table is reinitialized. Table insertions
ERROR CODES
using the buffered–entry mode and the fast–entry mode
actually take the same amount of time unless the entry
FFFF
No error
queue is full. The capacity of the queue is 14 entries.
FFFD
Invalid instruction
After the entry mode choice is made, the table can be
FFFC
Queue not empty for read
loaded. Each 64–bit entry is constructed by writing a 16–bit
FFFB
Table not initialized
value to each of the four I/O registers in the control port of the
FFFA
Queue not empty for write
MCM69C433. The insertion can then be processed. After all
FFF9
CAM table full
the start–up entries have been loaded into the CAM table,
FFF8
Entry queue full
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INTERRUPT BIT DEFINITIONS
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Bit 6:
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Bit 7:
INSTRUCTION SET DETAILS
1 = Enable interrupt on insert with full entry
queue
1 = Enable interrupt on insert with full table
1 = Enable interrupt on completion of
CHECK–FOR–VALUE instruction
1 = Enable interrupt on completion of
INITIALIZE–TABLE instruction
1 = Enable interrupt on failed attempt to enter
fast–entry mode
1 = Enable interrupt on CAM table reaching
almost–full point
1 = Enable interrupt on fast read with non–empty
queue
1 = Enable interrupt on illegal instruction
Operation
INSERT VALUE
DELETE VALUE
CHECK FOR VALUE
INITIALIZE TABLE
FAST–ENTRY MODE
BUFFERED–ENTRY MODE
SET ATM MODE
ED
V
I
The MCM69C433 is prepared for match operations by
writing data and instructions via the control port. In the general case, required data is loaded into I/O registers 0 – 3,
then an instruction is issued by writing an operation code to
the operation register. As a result of running an instruction,
the CAM table can be modified, bit(s) can be set in the flag
register, error codes can be returned in the error code register, and an interrupt can be generated if enabled. For a particular condition to generate an interrupt, the interrupt
register bit specific to that condition must be set. The user
should verify that the last operation complete bit (bit 10) of
the flag register is set before executing the next instruction, if
the instruction just executed modifies
C.I/O registers. See the
N
Simultaneous Port OperationsI section for any exceptions.
R,
O
T
Table 1. MCM69C433 Operation Summary C
U
ND
Description
OP Code (Base 16)
O
C
I
Loads a new entry into the CAM table
0000 or 000F
M
E
Removes an entry fromS
the CAM table
0001 or 000E
E
L
Runs a match cycle via the control port
0006
A
C
Prepares CAM
table
for
matching
000B
ES
E
Selects
0004
R entry mode suited for initial CAM table load
F
Selects entry mode suited for simultaneous loading
0005
BY and matching
CH
RETURN ENTRYR
COUNT
A
Enter mode that provides concurrent VPC/VCC
search
0008
Determines number of entries in CAM
0003
SET GLOBAL–MASK REGISTER
Determines match bits to be checked in a match
operation
SET ALMOST–FULL POINT
Defines CAM almost–full condition
0007
SET FAST–READ REGISTER
Defines table entry that is output by the fast–read
operation
0009
FAST READ
Outputs one CAM table entry
000A
INSERT VALUE
This instruction is used to load a new match/output value
into the CAM. The contents of I/O registers 0 – 3 are concatenated, with bit 15 of register 3 as the most significant bit,
and bit 0 of register 0 as the least significant bit.
If the MCM69C433 is running in the buffered–entry mode,
the resulting 64–bit value is written to the first available location in the entry queue, and is immediately available for
matching. If a buffered insert–value instruction is attempted
when the entry queue is full (indicated by bit 5 of the flag register = 1), no value is written, an error code of FFF816 is returned in the error code register, and the error–condition flag
(bit 7) is set in the flag register. An interrupt is generated, if
enabled by bit 0 of the interrupt register being set.
If the MCM69C433 is running in the fast–entry mode, the
concatenated 64–bit value is written directly to the CAM
array. If an insert–value instruction is attempted when in
fast–entry mode and the table is full, no value is written, an
error code of FFF916 is returned in the error code register,
MCM69C433•SCM69C433
8
0002 or 000D
and the error–condition flag (bit 7) is set in the flag register.
(The table–full condition is indicated by bit 6 of the flag register being set.) An interrupt is generated, if enabled by bit 1 of
the interrupt register being set.
Only one entry is allowed for a given match pattern. If an
entry is made in the table that duplicates an existing match
pattern, it will overwrite the entry already in the CAM table, if
the CAM is in buffered–entry mode. The user must ensure
that no entries with the same match pattern are inserted in
fast–entry mode.
DELETE VALUE
This instruction is used to remove a match/output value
from the CAM. The contents of I/O registers 0 – 3 are concatenated, with bit 15 of register 3 as the most significant bit,
and bit 0 of register 0 as the least significant bit. The bits that
have a 0 in the corresponding bit of the global–mask register
are used to find a matching entry in the CAM table. If such an
entry is found, it is invalidated. Note that any bit that is not a
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
match bit as defined by the mask register is ignored for this
operation. The operation of the MCM69C433 guarantees
that no more than one matching entry can exist in the table,
unless they were accidently loaded using fast–entry mode.
This must be avoided by the user, as the results of subsequent matches and deletes will be undefined.
Example: I/O Register 0 =
I/O Register 1 =
I/O Register 2 =
I/O Register 3 =
Concatenated value =
Global–Mask Register =
302016
000016
543A16
FE5516
FE55543A0000302016
C0000000FFFFFFFF16
Of the high–order 32 bits, the rightmost 30 bits
are cared by the global–mask register. Therefore,
the MCM69C433 will delete an entry, if it exists,
which has a value of 3E55543A16 in bits 61 – 32.
Freescale Semiconductor, Inc...
CHECK FOR VALUE
interrupt is generated if enabled by bit 4 of the interrupt
register.
If this mode is used to enter data, the initialize–table operation must be executed before matching operations can
begin. The entry–mode bit and the table–initialized bit of the
flag register are cleared by this operation.
BUFFERED–ENTRY MODE
This instruction is used to enter the buffered–entry mode.
When the MCM69C433 is in this mode, insert–value and
delete–value operations utilize the entry queue. This mode
can be entered at any time. Table entries are available for
match operations immediately, without running the initialize–
table operation, if all entries are made
C.in this mode. Note that
N
if both the buffered–entry and fast–entry
modes have been
,I
used to input data, none R
of the entries are available for
matching until the initialize–table
operation is executed. ConTO
C
flicting table and queue
values are resolved in favor of the
U
latest entry in the
NDqueue. For example, if there is an entry in
the CAM, aO
corresponding delete–entry in the queue, and a
IC
later insert–entry
in the queue (all with the same match data),
M insert–entry
theE
queued
will return a match value.
This instruction checks for a matching value in the CAM
table via the control port. The contents of I/O registers 0 – 3
are concatenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. The
S
bits that have a 0 in the corresponding bit of the global–mask LE RETURN ENTRY COUNT
register are used to find a matching entry in the CAM table.CIfA
This operation is used to determine the number of valid ensuch an entry is found, the last–match–successful bit ofSthe
E
tries in the MCM69C433. The value is returned in I/O register
flag register is set. In addition, the matching entry is E
written to
R
0, and reflects the sum of the number of valid entries in the
I/O registers 0 – 3, with bit 15 of register 3 as theFmost signifiY
CAM table and the inserts in the entry queue.
cant bit, and bit 0 of register 0 as the leastBsignificant
bit
If no match is found, the last–match–successful
bit is
D
E
SET GLOBAL–MASK REGISTER
cleared. An interrupt is generatedV
regardless
of the result, if
I
enabled by bit 2 of the interrupt
Hregister, when the operation
This operation is used to indicate the bits to be used in perCoperation
has been completed. The
of the MCM69C433
R
forming matches. A 1 indicates that a bit should be ignored in
Athan one matching entry can exist
guarantees that no more
the match operation, while a 0 indicates that a bit should be
in the table. If uninterrupted by match port activity, the check
used in the match operation.
for value instruction will finish in 16 clock cycles. NOTE: If
When this operation is executed, the contents of I/O regisboth the control and matching ports are utilized simultaters 0 – 3 are concatenated, with bit 15 of register 3 as the
neously, see the Simultaneous Port Operations section.
most significant bit, and bit 0 of register 0 as the least signifiINITIALIZE TABLE
If fast–entry mode has been used to load the CAM table,
the initialize–table operation must be used to establish the
needed relationships and linkages between the entries in the
table before matching can proceed. Upon completion, this
operation sets the table–initialized bit in the flag register, and
generates an interrupt if enabled by bit 3 of the interrupt register. It also sets the buffered–entry mode bit in the flag register. This operation makes the programming model’s registers
read–only for up to 120 ms after the acknowledgment of the
op code write cycle.
FAST–ENTRY MODE
This instruction is used to enter the fast–entry mode.
When the MCM69C433 is in this mode, insert–value operations bypass the entry queue and write new table entries
directly to the CAM table. The fast–entry mode can only be
entered while the entry queue is empty, as reflected by the
queue–empty flag being set (bit 4 of the flag register.) If this
operation is attempted while the entry queue is not empty,
the value FFFA16 is written to the error code register, the
error–condition flag (bit 7) is set in the flag register, and an
MOTOROLA FAST SRAM
cant bit. The resulting 64–bit value is written to the global–
mask register.
This operation should be executed before entering required values into the CAM table. Otherwise, the initialize–
table instruction must be executed if the global–mask
register is changed after data is loaded into the CAM.
SET ALMOST–FULL POINT
This operation is used to define the “almost–full” condition
in the CAM table. The 14 low–order bits of I/O register 0 are
copied to the almost–full–point register. If an entry is added
to the MCM69C433 (via the insert–value operation) that
causes the valid–entry count to equal the almost–full point,
then bit 8 of the flag register is set, and an interrupt is generated if enabled by bit 5 of the interrupt register. The value of
the almost–full register can be changed dynamically during
match operations. For example, it could first be set to 8192 to
generate an interrupt when the table is half full. When that
point is reached, the register could be reprogrammed to
12,288 to provide warning that the table has become three–
quarters full. The almost–full interrupt is generated, if
enabled, based on the number of entries in the CAM table.
Entries in the queue are not included in the count.
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MCM69C433•SCM69C433
9
Freescale Semiconductor, Inc.
SET FAST–READ REGISTER VALUE
This operation defines the table address that is output by
the fast–read operation. The least significant 14 bits of I/O
register 0 are copied to the fast–read register. The queue
must be empty when this instruction is executed.
Bits 60 – 63 may be used for matching in ATM mode if the
application requires extra bits. The use of bits 0 – 31 for
matching is not supported in ATM mode.
MATCH DUTY CYCLE
At 66 MHz, the MCM69C433 completes a match 240 ns,
or 16 clock cycles, after assertion of the SM signal. HowThis operation is used to output the contents of one entry
ever, if entries need to be added to or deleted from the CAM,
in the CAM table. The fast–read register is used to specify
idle time is needed between match output and match
the appropriate entry, and is then auto–incremented. As a rerequests for control port insertions and deletions. At 66 MHz,
sult, successive execution of multiple fast–read operations
the match duty cycle should be defined at least at 20 clock
will provide access to contiguous entries in the CAM table.
cycles (300 ns), leaving 2 clock cycles for insertions/
The CAM entry is copied to I/O registers 0 – 3, with bit 15
deletions. The additional clock cycles. are used for holding
C
of register 3 as the most significant bit, and bit 0 of register 0
the match data on the MQ bus.N
Therefore,
every 20 clock
I
as the least significant bit.
,
cycles, when a match operation
and data output are comThe fast–read instruction can only be executed while the
pleted, SM can be asserted.
OR
T
entry queue is empty, as reflected by the queue–empty flag
Entries are stored from
C least value at the top of the table to
Uthe
being set (bit 4 of the flag register.) If this operation is atthe highest valueDat
bottom. If an entry with a match data
tempted while the entry queue is not empty, the value
value smallerN
than any other entry is continually added or
O
FFFC16 is written to the error code register, the error–condidroppedIC
from the table, worst–case scenario occurs causing
tion flag (bit 7) is set in the flag register, and an interrupt is
shifting
Mof all other entries. The idle time, in terms of the numgenerated if enabled by bit 7 of the interrupt register.
ber
SEcycles, needed to perform a worst–case insertion and/or
LE deletion is given by the formula 32,768 x MDC / (MDC – 18)
SET ATM MODE
A
cycles, where MDC is the match duty cycles. For example, if
C
S
match requests are occurring every 20 clock cycles:
When the MCM69C433 is placed in ATM mode, it provides
Freescale Semiconductor, Inc...
FAST READ
E
E and
simultaneous searching for virtual path circuits (VPCs)
FR when
virtual connection circuits (VCCs). A VCC is detected
Y
both the virtual path identifier (VPI) andBthe virtual circuit
D
identifier (VCI) of an incoming cellEmatch an entry in the
V VPI of an incoming cell
CAM. A VPC match occurs whenIthe
H
matches the VPI field of a CAM
entry
that has all 1s as its
C by the assertion
R
VCI. A VPC match is signalled
of the VPC
A
pin along with the MS pin. At 66 MHz, a match is completed
in 240 ns, whether the applied VPI/VCI belongs to a VCC or
a VPC.
The VCI match field must be defined as bits 32 – 47 of
each entry. The VPI match data must occupy bits 48 – 59.
The VPI can be limited to bits 48 – 55, if the switch handles
only User–Network Interface (UNI) protocols. The mask register should be used to “don’t care” any unused bits beyond
the VPI field. Entering ATM mode will set bit 9 of the flag register.
To load a VPC into the CAM table, the desired VPI value is
written (right justified) to I/O register 3, FFFF16 is written to
I/O register 2 as the VCI field, the upper half of the desired
output word is written to I/O register 1, and the lower half of
the desired output word is written to I/O register 0. Then, the
“INSERT VALUE” instruction is written to the operation register.
When performing a match operation, the VCI must be
placed in bits 0 – 15 of the MQ port. The VPI is expected on
bits 16 – 27, or bits 16 – 23 in the UNI case.
Buffered–entry mode insertions and deletions are modified
in the following way when the MCM69C433 is in ATM mode.
If you try to add a VCC with the same VPI as an existing
VPC, you overwrite the VPC. If you try to delete a VCC when
the VCC is not in the table, but a VPC with that VPI is in the
table, the VPC will be deleted.
The CAM table should never contain, simultaneously, a
VCC entry and VPC entry with matching VPIs. Violation of
this requirement may lead to unpredictable behavior.
MCM69C433•SCM69C433
10
32,768 x 20 clock cycles
= 327,680 clock cycles
20 clock cycles – 18
At 66 MHz (15 ns per cycle)
= 0.0049152 sec per insert or deletion.
If both insertions and deletions are occurring
= 102 insertion/deletion pairs per sec (worst–case).
More typical cases consist of insertions occurring at one
end of the table and deletions occurring at the other end, or
when insertions and/or deletions take place toward the
middle of the table. The latter scenario would consist of
approximately half the total entries being shifted. The idle
time, in terms of the number of cycles, needed to perform a
typical insertion and/or deletion is given by the formula
16,384 x MDC / (MDC – 18) cycles, where MDC is the match
duty cycles. For example, if match requests are occurring
every 20 clock cycles:
16,384 x 20 clock cycles
= 163,840 clock cycles
20 clock cycles – 18
At 66 MHz (15 ns per cycle)
= 0.0024576 sec per insert or deletion.
If both insertions and deletions are occurring
= 203 insertion/deletion pairs per sec (typical case).
The number of insertion/deletion pairs for both cases are
depicted in Figure 3. In general, the time for an insertion or
deletion is proportional to its distance from the end of the
CAM table. That is, entries with the largest match value take
the least time to insert or delete, while entries with the smallest values take the most time. Therefore, the effective rate of
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Freescale Semiconductor, Inc.
INSERTION – DELETION
PAIRS / SEC
2,500
TYPICAL
2,000
1,500
WORST CASE
1,000
500
0
20
30
40
50
60
70
80
MATCH DUTY CYCLE AT 66 MHz INPUT CLOCK
C
IN
100
.
R,
O
match has been found,T
the MS output is also asserted. If the
C circuit match in ATM mode, the VPC
match is a virtual path
U
D
output will be asserted
with the MS output. Output data, if
Nby
any, is enabled
the assertion of the G input.
O
C
If the Imatch
is greater than 32 bits, the lower bits are
M intowidth
firstElatched
the MCM69C433 by the LL input. The match
S
Figure 3. Connections per Second vs Match Cycle Time
Freescale Semiconductor, Inc...
90
insertion and deletion is maximized if the longest–lived entries are placed near the beginning of the table and the shortest–lived entries are placed near the end of the table. For an
ATM application, this would correspond to the assignment of
small VPI values to permanent virtual circuits and large VPI
values to switched virtual circuits.
Note that at start–up, when entries are loaded into the
is then initiated as specified in the previous paragraph.
E cycle
CAM via the fast–entry mode, the process is dominated by L
Two alternative timing diagrams are presented to describe
CA the Match Port timing. In the first, LH/SM must meet setup
the time it takes to execute the initialization instruction that
S
follows. The resulting effective rate of loading the CAM
and hold specs across two consecutive clock cycles, while
EE at
start–up is approximately 136,500 entries per second.
the MQ bus need only be valid for a single cycle. In the seR
F
cond diagram, LH/SM need only be asserted for a single
RESET
BY
clock cycle, while the MQ bus must be held valid with
D
constant data across two clock cycles.
E from the CAM table
Asserting RESET removes all entries
V
and entry queue. The flag register
HI is set to 1C16 (setting the
C
queue empty, buffered–entry
mode, and table initialized bits).
ARto FFFF16, indicating no errors.
The error register is set
Finally, the almost–full register is set to 3FFF16.
TIMING OVERVIEW
CONTROL PORT
The control port of the MCM69C433 is asynchronous.
Data transfers, both read and write, are initiated by the
assertion of the SEL signal. Address values should be valid
and WE should be high, when SEL is asserted to begin
a read cycle. All values (address, WE, and SEL) should be
held until the MCM69C433 asserts DTACK to signal the end
of the read cycle.
Address and data values should be valid and WE should
be low, when SEL is asserted to begin a write cycle. Address,
data, WE, and SEL values should be held until the
MCM69C433 asserts DTACK to signal the end of the write
cycle.
MATCH PORT
The MCM69C433’s match port is synchronous in operation. When the match width is 32 bits, a match cycle can be
initiated by presenting the match data on MQ31 – MQ0 and
asserting the LH/SM signal with the appropriate setup time
relative to the rising edge of the clock. The assertion of the
MC output signifies the completion of the match cycle. If a
v
MOTOROLA FAST SRAM
SIMULTANEOUS PORT OPERATIONS
When the control and match ports are utilized simultaneously, certain procedures must be followed. If a CHECK
FOR VALUE command is issued, both the last operation
complete bit (bit 10) and the entry queue empty bit (bit 4) in
the flag register should be set prior to executing the CHECK
FOR VALUE command in order to receive valid results. However, matching on the match port can be done directly after
the last operation complete flag is set.
The match port has priority over the control port during
simultaneous operations.
DEPTH EXPANSION
Multiple CAMs can be cascaded to increase the depth of
the match table. The hardware requirements are very
straightforward, as the following pins on each device are simply wired in parallel: A2 – A0, DQ15 – DQ0, WE, IRQ,
DTACK, MQ31 – MQ0, K, G, LH/SM, MC, MS, and VPC.
Four CAMs can be easily cascaded. Simulations show that
eight devices can be cascaded if care is taken to minimize
the length of the PC board traces connecting the CAMs.
The buffered–entry mode prevents multiple matching
entries in a single CAM. The check for value instruction
should be used to verify that multiple matching entries will
not result from a potential new entry. If a match is found in
CAM 1, for example, the new value should be placed in CAM 1,
where it will replace the existing entry.
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MCM69C433•SCM69C433
11
Freescale Semiconductor, Inc.
DEPTH EXPANSION EXAMPLE
CASCADING FOUR MCM69C433s FOR A 64K WORD TABLE
CONTROL PORT
MATCH PORT
CAM 0
A2 – A0
A0 – A2
DQ31 – DQ0
DQ0 – DQ31
SEL0
WE
MQ31 – MQ0
MQ0 – MQ31
WE
K
K
G
LM/SM
G
LH/SM
MC
IRQ
IRQ
MS
DTACK
DTACK
Freescale Semiconductor, Inc...
VPC
CAM 1
A0 – A2
LE
A
SC
DQ0 – DQ31
SEL1
CH
R
A
ED
V
I
BY
EWEE
R
F
CO
I
MQ0 –M
MQ31
SE K
,I
R
TO
C
U
ND
N
C.
MC
MS
VPC
G
LM/SM
MC
IRQ
MS
DTACK
VPC
CAM 2
A0 – A2
MQ0 – MQ31
K
DQ0 – DQ31
SEL2
G
LM/SM
WE
MC
IRQ
MS
DTACK
VPC
CAM 3
A0 – A2
DQ0 – DQ31
SEL3
WE
MQ0 – MQ31
K
G
LM/SM
MC
IRQ
MS
DTACK
VPC
MCM69C433•SCM69C433
12
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MOTOROLA FAST SRAM
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tKHVPH
5
6
7
8
9
10
11
12
14
tKHMQV
13
15
DOUT
16
300 ns
tGHMQZ
18
tKHMCL
17
tKHVPL
tKHMSL
R,
O
CT
U
ND
C
IN
NOTE: See description of Match Port Timing.
VPC
MS
tKHMSH
tKHMCH
tGLMQX
4
S
O
IC
EM
MC
DIN
tKHMQX
3
LE
A
SC
MQ31 – MQ0
tMQVKH
2
225 ns
EE
R
F
G
tKHLH
1
150 ns
BY
LHBSM
t LLKH
0
75 ns
CH
R
A
ED
V
I
LL
K
0 ns
MATCH PORT TIMING (SINGLE CLOCK MODE 32–BIT MATCH)
ALTERNATE A
Freescale Semiconductor, Inc...
20
21
tKHLH
tKHVPH
tKHMSH
tKHMCH
tMQVKH
tLLKH
19
22
DIN
375 ns
23
Freescale Semiconductor, Inc.
.
MCM69C433•SCM69C433
13
MCM69C433•SCM69C433
14
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7
tGLMQX
6
8
9
10
11
12
14
tKHMQV
13
15
17
tKHVPL
18
tKHMCL
tGHMQZ
tKHMSL
DOUT
16
C
IN
NOTE: See description of Match Port Timing.
tKHVPH
5
300 ns
R,
O
CT
U
ND
VPC
MS
tKHMSH
tKHMCH
4
S
O
IC
EM
MC
DIN
tKHMQX
3
LE
A
SC
MQ31 – MQ0
tMQVKH
2
225 ns
EE
R
F
G
tKHLH
1
150 ns
BY
LHBSM
t LLKH
0
75 ns
CH
R
A
ED
V
I
LL
K
0 ns
MATCH PORT TIMING (SINGLE CLOCK MODE 32–BIT MATCH)
ALTERNATE B
Freescale Semiconductor, Inc...
19
21
tKHVPH
tKHMSH
tKHMCH
tMQVKH
tKHLH
tLLKH
20
DIN
375 ns
22
23
Freescale Semiconductor, Inc.
.
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
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IRQ
t ILIH
t SHDTH
DATA – OUT
t QVDTL
t SLDTL
O
IC
EM
DTACK
t DTLIL
t AVQV
S
t SLDTL
t DTLWH
B
t AVSL
LE
A
SC
WE
t WVSL
DATA – IN
EE
R
F
DQ15 – DQ0
t DTLDX
t DTLSH
BY
t DVSL
t AVSL
A
CH
R
A
ED
V
I
SEL
A2 – A0
t DTLAX
CONTROL PORT TIMING
Freescale Semiconductor, Inc...
t SHDTH
t SHQZ
Freescale Semiconductor, Inc.
R,
O
CT
U
ND
C
IN
.
MCM69C433•SCM69C433
15
Freescale Semiconductor, Inc.
JTAG
AC OPERATING CONDITIONS AND CHARACTERISTICS
FOR THE TEST ACCESS PORT (IEEE 1149.1)
(TJ < 120°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . 50 Ω Termination to 1.5 V
TAP CONTROLLER TIMING
Parameter
Symbol
Cycle Time
R,
tCKH
12O
T
C12
tCKL
U
D 5
tA N
O
C
0
ItCKZ
M
t
0
E
tCK
Clock High Time
Clock Low Time
Freescale Semiconductor, Inc...
Min
Clock Low to Output Valid
Clock Low to Output High–Z
Clock Low to Output Active
Setup Times:
EE
R
F
Hold Times:
LE
A
SC
S
30
CKX
C
IN—
.
Max
Unit
Notes
ns
—
ns
—
ns
9
ns
9
ns
1
9
ns
2, 3
TMS
TDI
TRST
tS
tSD
tSR
2
2
2
—
ns
TMS
TDI
TRST
tH
tHD
tHR
2
2
10
—
ns
BY
D
NOTES:
E depending on the current state of the TAP state machine.
1. TDO will High–Z from a clock low
Vedge
I
2. TDO is active only in the SHIFT–IR
SHIFT–DR state of the TAP state machine.
CHmV fromandsteady–state
3. Transition is measuredR
±500
voltage. This parameter is sampled and not 100% tested.
A
tCKH
tCK
tCKL
TCK TEST
CLOCK
tS
tH
TMS TEST
MODE SELECT
tSD
tHD
TDI TEST
DATA IN
tA
tCKZ
tCKX
TDO TEST
DATA OUT
tHR
tSR
TRST
Figure 4. TAP Controller Timing
MCM69C433•SCM69C433
16
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
TEST ACCESS PORT DESCRIPTION
INSTRUCTION SET
A 5–pin IEEE Standard 1149.1 Test Port (JTAG) is included on this device. When the TAP (Test Access Port) controller is in the SHIFT–IR state, the instruction register is
placed between TDI and TDO. In this state, the desired
instruction would be serially loaded through the TDI input.
TRST resets the TAP controller to the test–logic reset state.
The TAP instruction set for this device are as follows.
Freescale Semiconductor, Inc...
STANDARD INSTRUCTIONS
Instruction
Code
(Binary)
BYPASS
1111*
Bypass instruction
SAMPLE/PRELOAD
0010
Sample and/or preload
instruction
EXTEST
0000
Extest instruction
Description
After one clock cycle of TCK, the TAP controller would then
be moved to the SHIFT–DR state where the sampled values
would be shifted out of TDO (and new values would be
shifted in TDI). These values would normally be compared to
expected values to test for board connectivity.
CLAMP TAP INSTRUCTION
The CLAMP instruction is provided to allow the state of the
signals driven from the output pins to be determined from the
boundary scan register while the bypass register is selected
as the serial path between TDI and TDO. The signals driven
. while the CLAMP
from the output pins will not change
C
N
instruction is selected. EXTESTI could also be used for this
purpose, but CLAMP shortens
R,the board scan path by insertO
ing only the bypass register
TDI and TDO. To use
T between
C
CLAMP, the SAMPLE/PRELOAD
instruction would be used
U that will be driven on the output pins
first to scan in the
Dvalues
N
when the CLAMP
O instruction is active.
IC
HIGH–Z
M TAP INSTRUCTION
E
SThe
HIGH–Z instruction is provided to allow all the outputs
E
L
to be placed in an inactive drive state (high–Z). During the
CLAMP
1100
Clamp output pins while
CA HIGH–Z instruction the bypass register is connected bebypass register is between
S
tween TDI and TDO.
TDI and TDO
EE
R
BYPASS TAP INSTRUCTION
F
* Default state at power–up.
Y
B
The BYPASS instruction is the default instruction loaded at
SAMPLE/PRELOAD TAP INSTRUCTION
D
power
up. This instruction will place a single shift register
VE
between TDI and TDO during the SHIFT–DR state of the
The SAMPLE/PRELOAD TAPIinstruction
is used to allow
TAP controller. This allows the board level scan path to be
scanning of the boundary scan
CHregister without causing interR
shortened to facilitate testing of other devices in the scan
ference to the normal operation
of the chip logic. The 62–bit
A
path.
HIGHZ
1001
High–Z all output pins while
bypass register is between
TDI and TDO
boundary scan register contains bits for all device signal and
clock pins and associated control signals. This register is accessible when the SAMPLE/PRELOAD TAP instruction is
loaded into the TAP instruction register in the SHIFT–IR
state. When the TAP controller is then moved to the SHIFT–
DR state, the boundary scan register is placed between TDI
and TDO. This scan register can then be used prior to the
EXTEST instruction to preload the output pins with desired
values so that these pins will drive the desired state when the
EXTEST instruction is loaded. As data is written into TDI,
data also streams out TDO which can be used to pre–sample
the inputs and outputs.
SAMPLE/PRELOAD would also be used prior to the
CLAMP instruction to preload the values on the output pins
that will be driven out when the CLAMP instruction is loaded.
EXTEST TAP INSTRUCTION
The EXTEST instruction is intended to be used in conjunction with the SAMPLE/PRELOAD instruction to assist in
testing board level connectivity. Normally, the SAMPLE/
PRELOAD instruction would be used to preload all output
pins. The EXTEST instruction would then be loaded. During
EXTEST, the boundary scan register is placed between TDI
and TDO in the SHIFT–DR state of the TAP controller. Once
the EXTEST instruction is loaded, the TAP controller would
then be moved to the run–test/idle state. In this state, one
cycle of TCK would cause the preloaded data on the output
pins to be driven while the values on the input pins would be
sampled. Note the TCK, not the clock pin (CLK), is used as
the clock input while CLK is only sampled during EXTEST.
MOTOROLA FAST SRAM
BOUNDARY SCAN REGISTER
The boundary scan register is identical in length to the
number of active input, output, and I/O connections on the
device (not counting the TAP pins). The boundary scan register, under the control of the TAP controller, is loaded with
the contents of the RAM I/O ring when the controller is in
capture–DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift–DR state.
Several TAP instructions can be used to activate the boundary scan register.
The Bit Scan Order table (Table 2) describes which device
pin connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit at G (i.e., first to be shifted out)
is defined as bit 1. The second column is the name of the pin,
third column is the pin number and the fourth column is the
pin type (input, output, or I/O).
DISABLING THE TEST ACCESS PORT AND
BOUNDARY SCAN
It is possible to use this device without utilizing the four
pins used for the test access port. To circuit disable the
device, TCK must be tied to V SS to preclude mid–level
inputs. Although TDI and TMS are designed in such a way
that an undriven input will produce a response equivalent to
the application of a logic 1, it is still advisable to tie these
inputs to VDD through a 1K resistor. TDO should remain
unconnected.
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MCM69C433•SCM69C433
17
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 2. Sample/Preload Boundary Scan Register Bit Definitions
Bit No.
Bit Pin Name
Bit Pin No.
Bit No.
Bit Pin Name
Bit Pin No.
1
G
61
33
MQ5
7
2
MS
62
34
MQ4
8
3
VPC
63
35
MQ3
11
4
MC
64
36
MQ2
12
5
MQ31
67
37
MQ1
13
6
MQ30
68
38
MQ0
14
7
MQ29
69
8
MQ28
70
9
MQ27
73
10
MQ26
74
11
MQ25
75
12
MQ24
76
13
MQ23
79
14
MQ22
80
15
MQ21
16
MQ20
17
MQ19
18
MQ18
EE
R
82 F
Y
B 85
81
ED
V
I
NC
40
DQ14 I
R,
O
41
DQ13
CT
U
42
DQ12
D
N
DQ11
O43
IC
DQ10
EM 44
39
LE
A
SC
S
DQ15
.
17
18
19
20
23
24
45
DQ9
25
46
DQ8
26
47
DQ7
29
48
DQ6
30
49
DQ5
31
50
DQ4
32
51
DQ3
35
52
DQ2
36
53
DQ1
37
54
DQ0
38
55
K
39
86
20
CH
R
A MQ16
21
LH/SM
89
22
LL
92
23
MQ15
93
24
MQ14
94
25
MQ13
95
56
A2
42
26
MQ12
96
57
A1
43
27
MQ11
99
58
A0
44
28
MQ10
100
59
WE
45
29
MQ9
1
60
SEL
46
30
MQ8
2
61
RESET
56
31
MQ7
5
62
IRQ
57
32
MQ6
6
63
DTACK
58
19
MQ17
MCM69C433•SCM69C433
18
87
88
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
the instruction that is currently loaded in the TAP instruction
register (see Figure 5). An undriven TDI pin will produce the
same result as a logic 1 input level.
TEST ACCESS PORT PINS
TCK — TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TDO — TEST DATA OUT (OUTPUT)
Output that is active depending on the state of the TAP
state machine (see Figure 5). Output changes in response to
the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
TMS — TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a
logic 1 input level.
TRST — TAP RESET
This device has a TRST pin. TRST is optional in IEEE
1149.1. Asserting the asynchronous
C.TRST places the TAP
N
controller in test–logic reset state.
Test–logic reset state can
, I high
also be entered by holding R
TMS
for five rising edges of
O not affect the operation of the
TCK. This type of resetTdoes
system logic.
UC
TDI — TEST DATA IN (INPUT)
Freescale Semiconductor, Inc...
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and
1
TEST–LOGIC
RESET
LE
A
SC
0
0
RUN–TEST/
IDLE
1
CH
R
A
ED
V
I
BY
EE
R
F SELECT DR–SCAN
S
N
O
IC
M
E
D
SELECT IR–SCAN
0
1
0
1
CAPTURE–DR
CAPTURE–IR
0
0
SHIFT–DR
SHIFT–IR
0
1
1
1
EXIT1–IR
0
0
PAUSE 1–DR
PAUSE–IR
0
1
0
1
0
EXIT2–DR
EXIT2–IR
1
1
UPDATE–IR
PAUSE 2–DR
1
0
1
EXIT1–DR
0
1
1
0
1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 5. TAP Controller State Diagram
MOTOROLA FAST SRAM
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MCM69C433•SCM69C433
19
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ORDERING INFORMATION
(Order by Full Part Number)
Freescale Semiconductor, Inc...
MCM
SCM
69C433
XX
XX X
Motorola Memory Prefix
MCM = Commercial Temp.
SCM = Industrial Temp.
Blank = Trays, R = Tape and Reel
Speed (15 = 15 ns)
Part Number
Package (TQ = TQFP)
Full Commercial Part Numbers — MCM69C433TQ15
MCM69C433TQ15R
Full Industrial Part Numbers —
SCM69C433TQ15R
CH
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MCM69C433•SCM69C433
20
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F
SCM69C433TQ15
LE
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S
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R,
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For More Information On This Product,
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IN
.
MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
TQ PACKAGE
TQFP
CASE 983A–01
4X
e
0.20 (0.008) H A–B D
2X 30 TIPS
e/2
0.20 (0.008) C A–B D
–D–
80
51
B
50
81
E/2
–A–
–B–
E1/2
31
100
1
30
D1/2
D/2
D1
D
2X 20 TIPS
0.20 (0.008) C A–B D
A
–H–
CH
R
A
–C–
SEATING
PLANE
0.05 (0.002)
ED
V
I
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EE
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SC
q2
S
O
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EM
R,
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U
ND
VIEW AB
q1
c
R2
A1
R1
L2
L
L1
ÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
c1
M
C A–B
S
D
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
2. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE BOTTOM OF THE
PARTING LINE.
3. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.
4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING
PLANE –C–.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010)
PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM PLANE
–H–.
6. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT
CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018).
GAGE PLANE
q
VIEW AB
DIM
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
L2
S
R1
R2
q
q1
q2
q3
MOTOROLA FAST SRAM
b1
b
0.25 (0.010)
A2
PLATING
SECTION B–B
q3
S
.
X=A, B, OR D
BASE
METAL
0.13 (0.005)
0.10 (0.004) C
S
C
IN
VIEW Y
E1 E
Freescale Semiconductor, Inc...
–X–
B
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MILLIMETERS
MIN
MAX
–––
1.60
0.05
0.15
1.35
1.45
0.22
0.38
0.22
0.33
0.09
0.20
0.09
0.16
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.65 BSC
0.45
0.75
1.00 REF
0.50 REF
0.20
–––
0.08
–––
0.08
0.20
0_
7_
0_
–––
11 _
13 _
11 _
13 _
MCM69C433•SCM69C433
21
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
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MCM69C433•SCM69C433
22
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For More Information On This Product,
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C
IN
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
CH
R
A
MOTOROLA FAST SRAM
ED
V
I
BY
EE
R
F
LE
A
SC
S
O
IC
EM
R,
O
CT
U
ND
For More Information On This Product,
Go to: www.freescale.com
C
IN
.
MCM69C433•SCM69C433
23
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
CH
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C
IN
.
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MCM69C433•SCM69C433
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MCM69C433/D
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SRAM