TI1 MSP430G2001IRSARQ1 Automotive mixed-signal microcontroller Datasheet

Product
Folder
Sample &
Buy
Technical
Documents
Support &
Community
Tools &
Software
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
MSP430G2x11 and MSP430G2x01 Automotive Mixed-Signal Microcontrollers
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Low Supply-Voltage Range: 1.8 V to 3.6 V
Ultra-Low-Power Consumption
– Active Mode: 220 µA at 1 MHz, 2.2 V
– Standby Mode: 0.5 µA
– Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Ultra-Fast Wakeup From Standby Mode in Less
Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With One
Calibrated Frequency
– Internal Very-Low-Power Low-Frequency (LF)
Oscillator
– 32-kHz Crystal
– External Digital Clock Source
16-Bit Timer_A With Two Capture/Compare
Registers
Brownout Detector
On-Chip Comparator for Analog Signal Compare
Function or Slope Analog-to-Digital Conversion
(See Table 1)
Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security Fuse
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
For Family Members Details, See Table 1
Available Packages
– 14-Pin Plastic Small-Outline Thin Package
(TSSOP) (PW)
– 16-Pin QFN (RSA)
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide (SLAU144)
Low-Cost Sensor Systems
3 Description
The Texas Instruments MSP430™ family of ultra-lowpower microcontrollers consists of several devices
featuring different sets of peripherals targeted for
various applications. The architecture, combined with
five low-power modes, is optimized to achieve
extended battery life in portable measurement
applications. The device features a powerful 16-bit
RISC CPU, 16-bit registers, and constant generators
that contribute to maximum code efficiency. The
digitally controlled oscillator (DCO) allows the device
to wake up from low-power modes to active mode in
less than 1 µs.
The MSP430G2x01 and MSP430G2x11 devices
include ultra-low-power mixed-signal microcontrollers
with a built-in 16-bit timer and 10 I/O pins. The
MSP430G2x11 family members have a versatile
analog comparator.
Typical applications include low-cost sensor systems
that capture analog signals, convert them to digital
values, and then process the data for display or for
transmission to a host system.
Device Information (1)
PACKAGE
BODY SIZE
MSP430G2211IRSARQ1
ORDER NUMBER
RSA (16)
4 mm x 4 mm
MSP430G2211IPW4RQ1
PW (14)
5 mm x 4.4 mm
(1)
For the most current part, package, and ordering information,
see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
4 Functional Block Diagrams
XOUT
XIN
DVCC
DVSS
P1.x
P2.x
8
2
Port P1
Port P2
8 I/O
Interrupt
capability
pullup/down
resistors
2 I/O
Interrupt
capability
pullup/down
resistors
ACLK
Clock
System
SMCLK
Flash
RAM
2KB
128B
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
Comp_A+
Brownout
Protection
JTAG
Interface
8
Channels
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
Spy-Bi
Wire
RST/NMI
Figure 1. Functional Block Diagram, MSP430G2x11
XIN
XOUT
DVCC
DVSS
P2.x
P1.x
8
2
Port P1
Port P2
8 I/O
Interrupt
capability
pull-up/down
resistors
2 I/O
Interrupt
capability
pull-up/down
resistors
ACLK
Clock
System
SMCLK
MCLK
Flash
RAM
2KB
0.5KB
128B
16MHz
CPU
MAB
incl. 16
Registers
MDB
Emulation
2BP
Brownout
Protection
JTAG
Interface
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
Spy-Bi
Wire
RST/NMI
Figure 2. Functional Block Diagram, MSP430G2x01
2
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
Table of Contents
1
2
3
4
5
6
7
Features .................................................................
Applications ..........................................................
Description ............................................................
Functional Block Diagrams .................................
Revision History ...................................................
Device Characteristics .........................................
Terminal Configuration and Functions ...............
7.1
7.2
7.3
7.4
7.5
8
14-Pin PW Package (Top View), MSP430G2x11 .... 6
16-Pin RSA Package (Top View), MSP430G2x11 .. 6
14-Pin PW Package (Top View), MSP430G2x01 .... 6
16-Pin RSA Package (Top View), MSP430G2x01 .. 7
Terminal Functions .................................................. 8
Detailed Description ............................................. 9
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9
1
1
1
2
4
5
6
CPU .......................................................................... 9
Instruction Set .......................................................... 9
Operating Modes ................................................... 10
Interrupt Vector Addresses .................................... 11
Special Function Registers (SFRs) ........................ 12
Memory Organization ............................................. 13
Flash Memory ........................................................ 13
Peripherals ............................................................. 14
Specifications ...................................................... 17
9.1
9.2
9.3
9.4
Absolute Maximum Ratings ................................... 17
Handling Ratings .................................................... 17
Recommended Operating Conditions .................... 17
Active Mode Supply Current Into VCC Excluding
External Current ...................................................... 18
9.5 Typical Characteristics - Active Mode Supply Current
(Into VCC) ................................................................ 18
9.6 Low-Power Mode Supply Currents (Into VCC)
Excluding External Current ..................................... 19
9.7 Typical Characteristics, Low-Power Mode Supply
Currents .................................................................. 19
9.8 Schmitt-Trigger Inputs - Ports Px ........................... 20
9.9 Leakage Current - Ports Px ................................... 20
9.10 Outputs - Ports Px ................................................ 20
9.11 Output Frequency - Ports Px ............................... 20
9.12 Typical Characteristics - Outputs ......................... 21
9.13 POR, BOR ........................................................... 22
9.14 Main DCO Characteristics ................................... 24
Copyright © 2011–2014, Texas Instruments Incorporated
9.15 DCO Frequency ................................................... 24
9.16 Calibrated DCO Frequencies - Tolerance ........... 25
9.17 Wakeup From Lower-Power Modes (LPM3 or
LPM4) Electrical Characteristics ............................. 25
9.18 Typical Characteristics - DCO Clock Wakeup Time
From LPM3 or LPM4 .............................................. 25
9.19 Crystal Oscillator, XT1, Low-Frequency Mode .... 26
9.20 Internal Very-Low-Power Low-Frequency Oscillator
(VLO) ...................................................................... 26
9.21 Timer_A ................................................................ 26
9.22 Comparator_A+ (MSP430G2x11 only) ................ 27
9.23 Typical Characteristics - Comparator_A+ ............ 28
9.24 Flash Memory ...................................................... 29
9.25 RAM ..................................................................... 29
9.26 JTAG and Spy-Bi-Wire Interface .......................... 30
9.27 JTAG Fuse ........................................................... 30
10 I/O Port Schematics ........................................... 31
10.1 Port P1 Pin Schematic: P1.0 to P1.3, Input/Output
With Schmitt Trigger - MSP430G2x01 .................... 31
10.2 Port P1 Pin Schematic: P1.4 to P1.7, Input/Output
With Schmitt Trigger - MSP430G2x01 .................... 32
10.3 Port P1 Pin Schematic: P1.0 to P1.3, Input/Output
With Schmitt Trigger - MSP430G2x11 .................... 33
10.4 Port P1 Pin Schematic: P1.4 to P1.7, Input/Output
With Schmitt Trigger - MSP430G2x11 .................... 35
10.5 Port P2 Pin Schematic: P2.6, Input/Output With
Schmitt Trigger - MSP430G2x01 and MSP430G2x11
................................................................................. 37
10.6 Port P2 Pin Schematic: P2.7, Input/Output With
Schmitt Trigger - MSP430G2x01 and MSP430G2x11
................................................................................. 38
11 Device and Documentation Support ................ 39
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support .......................................
Related Links .......................................................
Community Resources .........................................
Trademarks ..........................................................
Electrostatic Discharge Caution ...........................
Glossary ...............................................................
39
41
42
42
42
42
42
12 Mechanical, Packaging, and Orderable
Information .......................................................... 42
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
3
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
REVISION
DESCRIPTION
SLAS775
Product Preview release
SLAS775A
Production Data release
SLAS775B
Changed port schematics (added buffer after PxOUT.y mux) in I/O Port Schematics
Removed all information related to operation at T temperature (-40°C to 105°C).
SLAS775C
Table 2, Added pin 13 to NC list for RSA-16 package
Recommended Operating Conditions, Added test conditions for typical values.
POR, BOR, Added note (2).
SLAS775D
Added Development Tools Support and Device and Development Tool Nomenclature.
Formatting and document organization changes throughout, including addition of section numbering.
SLAS775E
Added Device Characteristics, Device and Documentation Support, and Mechanical, Packaging, and Orderable
Information.
Removed MSP430G2111 and MSP430G2101 and all related information.
4
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
6 Device Characteristics
Table 1 shows the features of the MSP430G2x01 and MSP430G2x11 devices.
Table 1. Family Members (1)
BSL
EEM
Flash
(KB)
RAM
(B)
Timer_A
Comp_A+
Channel
Clock
I/O
Package
Type
MSP430G2211
-
1
2
128
1x TA2
8
LF, DCO, VLO
10
16-QFN
14-TSSOP
MSP430G2201
-
1
2
128
1x TA2
-
LF, DCO, VLO
10
16-QFN
14-TSSOP
MSP430G2001
-
1
0.5
128
1x TA2
-
LF, DCO, VLO
10
16-QFN
14-TSSOP
Device
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
5
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
7 Terminal Configuration and Functions
7.1 14-Pin PW Package (Top View), MSP430G2x11
DVCC
P1.0/TA0CLK/ACLK/CA0
1
14
2
13
P1.1/TA0.0/CA1
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
P1.4/SMCLK/CA4/TCK
3
12
4
11
5
10
6
9
P1.5/TA0.0/CA5/TMS
7
8
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/CAOUT/CA7/TDO/TDI
P1.6/TA0.1/CA6/TDI/TCLK
NOTE: See port schematics in I/O Port Schematics for detailed I/O information.
NC
DVSS
NC
DVCC
7.2 16-Pin RSA Package (Top View), MSP430G2x11
16 15 14 13
11
XOUT/P2.7
P1.2/TA0.1/CA2
3
10
TEST/SBWTCK
P1.3/CAOUT/CA3
4
9
RST/NMI/SBWTDIO
5
6
7
8
P1.6/TA0.1/CA6/TDI/TCLK
XIN/P2.6/TA0.1
2
P1.7/CAOUT/CA7/TDO/TDI
12
P1.1/TA0.0/CA1
P1.5/TA0.0/CA5/TMS
1
P1.4/SMCLK/CA4/TCK
P1.0/TA0CLK/ACLK/CA0
NOTE: See port schematics in I/O Port Schematics for detailed I/O information.
7.3 14-Pin PW Package (Top View), MSP430G2x01
DVCC
P1.0/TA0CLK/ACLK
1
14
2
13
P1.1/TA0.0
P1.2/TA0.1
P1.3
P1.4/SMCLK/TCK
3
12
P1.5/TA0.0/TMS
4
11
5
10
6
9
7
8
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/TDO/TDI
P1.6/TA0.1/TDI/TCLK
NOTE: See port schematics in I/O Port Schematics for detailed I/O information.
6
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
NC
DVSS
NC
DVCC
7.4 16-Pin RSA Package (Top View), MSP430G2x01
2
11
XOUT/P2.7
P1.2/TA0.1
3
10
TEST/SBWTCK
P1.3
4
9
RST/NMI/SBWTDIO
5
6
7
8
P1.7/TDO/TDI
P1.1/TA0.0
P1.5/TA0.0/TMS
16 15 14 13
12
P1.6/TA0.1/TDI/TCLK
1
P1.4/SMCLK/TCK
P1.0/TA0CLK/ACLK
XIN/P2.6/TA0.1
NOTE: See port schematics in I/O Port Schematics for detailed I/O information.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
7
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
7.5 Terminal Functions
Table 2. Terminal Functions
TERMINAL
NO.
NAME
14
PW
I/O
DESCRIPTION
16
RSA
P1.0/
General-purpose digital I/O pin
TA0CLK/
ACLK/
2
1
I/O
Timer0_A, clock signal TACLK input
ACLK signal output
Comparator_A+, CA0 input (1)
CA0
P1.1/
General-purpose digital I/O pin
TA0.0/
3
2
I/O
Timer0_A, capture: CCI0A input, compare: Out0 output
Comparator_A+, CA1 input (1)
CA1
P1.2/
General-purpose digital I/O pin
TA0.1/
4
3
I/O
Timer0_A, capture: CCI1A input, compare: Out1 output
Comparator_A+, CA2 input (1)
CA2
P1.3/
General-purpose digital I/O pin
CA3/
5
4
I/O
Comparator_A+, CA3 input (1)
CAOUT
Comparator_A+, output (1)
P1.4/
General-purpose digital I/O pin
SMCLK/
6
CA4/
5
I/O
SMCLK signal output
Comparator_A+, CA4 input (1)
TCK
JTAG test clock, input terminal for device programming and test
P1.5/
General-purpose digital I/O pin
TA0.0/
7
CA5/
6
I/O
Timer0_A, compare: Out0 output
Comparator_A+, CA5 input (1)
TMS
JTAG test mode select, input terminal for device programming and test
P1.6/
General-purpose digital I/O pin
TA0.1/
8
CA6/
7
I/O
Timer0_A, compare: Out1 output
Comparator_A+, CA6 input (1)
TDI/TCLK
JTAG test data input or test clock input during programming and test
P1.7/
General-purpose digital I/O pin
CA7/
9
CAOUT/
8
I/O
TDO/TDI (2)
CA7 input (1)
Comparator_A+, output (1)
JTAG test data output terminal or test data input during programming and test
XIN/
Input terminal of crystal oscillator
P2.6/
13
12
I/O
TA0.1
General-purpose digital I/O pin
Timer0_A, compare: Out1 output
XOUT/
P2.7
12
11
I/O
10
9
I
RST/
Output terminal of crystal oscillator (3)
General-purpose digital I/O pin
Reset
NMI/
SBWTDIO
TEST/
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.
11
10
I
DVCC
1
16
NA
Supply voltage
DVSS
14
14
NA
Ground reference
NC
-
13, 15
NA
Not connected
QFN Pad
-
Pad
NA
QFN package pad connection to VSS is recommended.
SBWTCK
(1)
(2)
(3)
8
Spy-Bi-Wire test clock input during programming and test
MSP430G2x11 only
TDO or TDI is selected via JTAG instruction.
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
8 Detailed Description
8.1 CPU
Instruction Set (continued)
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
SR/CG1/R2
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
8.2 Instruction Set
General-Purpose Register
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
General-Purpose Register
R14
General-Purpose Register
R15
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator, respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Table 3. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 --> R5
Single operands, destination only
CALL R8
PC ->(TOS), R8-> PC
JNE
Jump-on-equal bit = 0
Relative jump, un/conditional
Table 4. Address Mode Descriptions (1)
(1)
ADDRESS MODE
S
D
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
OPERATION
R10 - -> R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) - -> M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
Absolute
✓
✓
MOV &MEM,&TCDAT
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) - -> M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) - -> R11
R10 + 2- -> R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 - -> M(TONI)
M(EDE) - -> M(TONI)
M(MEM) - -> M(TCDAT)
S = source, D = destination
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
9
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
8.3 Operating Modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 1 (LPM1)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– DCO's dc generator is disabled if DCO not used in active mode
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK and SMCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
10
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
8.4 Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed) the
CPU goes into LPM4 immediately after power-up.
Table 5. Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE
INTERRUPT FLAG
Power-Up
External Reset
Watchdog Timer+
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
PRIORITY
Reset
0FFFEh
31, highest
(non)-maskable
(non)-maskable
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
0FFF6h
27
CAIFG (4) (5)
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer_A2
TACCR0 CCIFG (4)
maskable
0FFF2h
25
TACCR1 CCIFG, TAIFG
I/O Port P2 (two flags)
I/O Port P1 (eight flags)
See
(2)
(3)
(4)
(5)
(6)
WORD
ADDRESS
Comparator_A+
Timer_A2
(1)
SYSTEM
INTERRUPT
(2) (4)
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
0FFEAh
21
0FFE8h
20
P2IFG.6 to P2IFG.7 (2) (4)
maskable
0FFE6h
19
(2) (4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
0FFDEh to
0FFC0h
15 to 0, lowest
P1IFG.0 to P1IFG.7
(6)
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address ranges.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Interrupt flags are located in the module.
Devices with Comparator_A+ only
The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
11
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
8.5 Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
Address
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in
interval timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
2
1
0
01h
Table 7. Interrupt Flag Register 1 and 2
Address
7
6
5
02h
WDTIFG
OFIFG
PORIFG
RSTIFG
NMIIFG
Address
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault.
Power-on reset interrupt flag. Set on VCC power-up.
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.
Set via RST/NMI pin
7
6
5
4
3
2
1
0
03h
12
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
8.6 Memory Organization
Table 8. Memory Organization
MSP430G2001
MSP430G2011
Memory
MSP430G2201
MSP430G2211
Size
512B
2kB
Main: interrupt vector
Flash
0xFFFF to 0xFFC0
0xFFFF to 0xFFC0
Main: code memory
Flash
0xFFFF to 0xFE00
0xFFFF to 0xF800
Information memory
Size
256 Byte
256 Byte
Flash
010FFh to 01000h
010FFh to 01000h
RAM
Size
Peripherals
128B
128B
027Fh to 0200h
027Fh to 0200h
16-bit
01FFh to 0100h
01FFh to 0100h
8-bit
0FFh to 010h
0FFh to 010h
0Fh to 00h
0Fh to 00h
8-bit SFR
8.7 Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire or JTAG port or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also
called information memory.
• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It
can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is
required.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
13
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
8.8 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
8.8.1 Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).
The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic
clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 9. DCO Calibration Data
(Provided From Factory In Flash Information Memory Segment A)
DCO FREQUENCY
1 MHz
CALIBRATION
REGISTER
SIZE
ADDRESS
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
8.8.2 Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
8.8.3 Digital I/O
There is one 8-bit I/O port implemented—port P1—and two bits of I/O port P2:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
• Read/write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup/pulldown resistor.
8.8.4 Watchdog Timer (WDT+)
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
14
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
8.8.5 Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 10. Timer_A2 Signal Connections - Devices With No Analog
INPUT PIN NUMBER
PW
RSA
DEVICE INPUT
SIGNAL
2 - P1.0
1 - P1.0
TACLK
MODULE
INPUT NAME
TACLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PW
RSA
2 - P1.0
1 - P1.0
TACLK
INCLK
3 - P1.1
2 - P1.1
TA0
CCI0A
3 - P1.1
2 - P1.1
ACLK (internal)
CCI0B
7 - P1.5
6 - P1.5
VSS
GND
4 - P1.2
3 - P1.2
CCR0
TA0
VCC
VCC
TA1
CCI1A
4 - P1.2
3 - P1.2
TA1
CCI1B
8 - P1.6
7 - P1.6
VSS
GND
13 - P2.6
12 - P2.6
VCC
VCC
CCR1
TA1
Table 11. Timer_A2 Signal Connections - Devices With Comparator_A+
INPUT PIN NUMBER
PW
RSA
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
2 - P1.0
1 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
2 - P1.0
1 - P1.0
TACLK
INCLK
3 - P1.1
2 - P1.1
TA0
CCI0A
ACLK (internal)
CCI0B
VSS
GND
4 - P1.2
3 - P1.2
VCC
VCC
TA1
CCI1A
CAOUT
(internal)
CCI1B
VSS
GND
VCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
CCR1
TA0
TA1
OUTPUT PIN NUMBER
PW
RSA
3 - P1.1
2 - P1.1
7 - P1.5
6 - P1.5
4 - P1.2
3 - P1.2
8 - P1.6
7 - P1.6
13 - P2.6
12 - P2.6
8.8.6 Comparator_A+ (MSP430G2x11 Only)
The primary function of the comparator_A+module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
15
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
8.8.7 Peripheral File Map
Table 12. Peripherals With Word Access
MODULE
REGISTER
NAME
REGISTER DESCRIPTION
Timer_A
Flash Memory
Watchdog Timer+
OFFSET
Capture/compare register
TACCR1
0174h
Capture/compare register
TACCR0
0172h
Timer_A register
TAR
0170h
Capture/compare control
TACCTL1
0164h
Capture/compare control
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
Watchdog/timer control
WDTCTL
0120h
Table 13. Peripherals With Byte Access
MODULE
REGISTER DESCRIPTION
Comparator_A+
(MSP430G2x11 only)
Basic Clock System+
Port P2
Port P1
Special Function
16
Submit Documentation Feedback
REGISTER
NAME
OFFSET
Comparator_A+ port disable
CAPD
05Bh
Comparator_A+ control 2
CACTL2
05Ah
Comparator_A+ control 1
CACTL1
059h
Basic clock system control 3
BCSCTL3
053h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P2 resistor enable
P2REN
02Fh
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 resistor enable
P1REN
027h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
9 Specifications
9.1 Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
-0.3 V to 4.1 V
Voltage applied to any pin (2)
-0.3 V to VCC + 0.3 V
Diode current at any device pin
(1)
±2 mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(2)
9.2 Handling Ratings
Tstg
Storage temperature
MIN
MAX
UNIT
Unprogrammed device
-55
150
°C
Programmed device
-55
150
9.3 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
VCC
Supply voltage
VSS
Supply voltage
TA
Operating free-air temperature
fSYSTEM
(1)
(2)
NOM
MAX
During program execution
1.8
3.6
During flash program or erase
2.2
3.6
0
Processor frequency (maximum MCLK frequency) (1) (2)
UNIT
V
V
-40
85
VCC = 1.8 V,
Duty cycle = 50% ± 10%
dc
6
VCC = 2.7 V,
Duty cycle = 50% ± 10%
dc
12
VCC ≥ 3.3 V,
Duty cycle = 50% ± 10%
dc
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency - MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
Note:
2.7 V
2.2 V
Supply Voltage - V
3.3 V 3.6 V
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 3. Safe Operating Area
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
17
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
9.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
PARAMETER
Active mode (AM)
current (1 MHz)
IAM,1MHz
(1)
(2)
TEST CONDITIONS
VCC
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
MIN
TYP
2.2 V
220
3V
300
MAX
UNIT
µA
370
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
9.5 Typical Characteristics - Active Mode Supply Current (Into VCC)
5.0
4.0
Active Mode Current − mA
Active Mode Current − mA
f DCO = 16 MHz
4.0
3.0
f DCO = 12 MHz
2.0
f DCO = 8 MHz
1.0
TA = 85 °C
3.0
TA = 25 °C
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
f DCO = 1 MHz
0.0
1.5
2.0
2.5
3.0
3.5
VCC = 2.2 V
4.0
VCC − Supply Voltage − V
Figure 4. Active Mode Current vs VCC, TA = 25°C
18
Submit Documentation Feedback
0.0
0.0
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 5. Active Mode Current vs DCO Frequency
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
9.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TA
VCC
Low-power mode 0
(LPM0) current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25°C
2.2 V
65
µA
ILPM2
Low-power mode 2
(LPM2) current (4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
22
µA
ILPM3,LFXT1
Low-power mode 3
(LPM3) current (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.7
1.5
µA
ILPM3,VLO
Low-power mode 3
current, (LPM3) (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25°C
2.2 V
0.5
0.7
µA
0.5
ILPM4
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
0.1
Low-power mode 4
(LPM4) current (5)
0.8
1.5
ILPM0,1MHz
(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
MIN
(2)
TYP
25°C
2.2 V
85°C
MAX
UNIT
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
9.7 Typical Characteristics, Low-Power Mode Supply Currents
3.00
2.50
2.75
2.25
ILPM4 – Low-Power Mode Current – µA
ILPM3 – Low-Power Mode Current – µA
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
2.50
2.25
2.00
1.75
1.50
Vcc = 3.6 V
1.25
Vcc = 3 V
1.00
Vcc = 2.2 V
0.75
0.50
Vcc = 1.8 V
0.25
0.00
-40
-20
0
20
40
60
TA – Temperature – °C
Figure 6. LPM3 Current vs Temperature
Copyright © 2011–2014, Texas Instruments Incorporated
80
2.00
1.75
1.50
1.25
Vcc = 3.6 V
1.00
Vcc = 3 V
0.75
Vcc = 2.2 V
0.50
0.25
0.00
-40
Vcc = 1.8 V
-20
0
20
40
60
80
TA – Temperature – °C
Figure 7. LPM4 Current vs Temperature
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
19
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
9.8 Schmitt-Trigger Inputs - Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ - VIT-)
VCC
MIN
RPull
Pullup/pulldown resistor
CI
Input capacitance
VIN = VSS or VCC
MAX
0.45 VCC
0.75 VCC
1.35
2.25
3V
For pullup: VIN = VSS
For pulldown: VIN = VCC
TYP
UNIT
V
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1
V
3V
20
50
kΩ
35
5
V
pF
9.9 Leakage Current - Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
VCC
(1) (2)
High-impedance leakage current
MIN
3V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
9.10 Outputs - Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
I(OHmax) = -6 mA (1)
3V
VCC - 0.3
V
VOL
Low-level output voltage
I(OLmax) = 6 mA (1)
3V
VSS + 0.3
V
(1)
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
9.11 Output Frequency - Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Port output frequency
(with load)
fPx.y
fPort_CLK
(1)
(2)
20
TEST CONDITIONS
Clock output frequency
Px.y, CL = 20 pF, RL = 1 kΩ (1)
Px.y, CL = 20 pF
(2)
(2)
VCC
MIN
TYP
MAX
UNIT
3V
12
MHz
3V
16
MHz
A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
9.12 Typical Characteristics - Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
50
VCC = 2.2 V
P1.7
TA = 25°C
25
TA = 85°C
20
15
10
5
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
30
0
TA = 25°C
40
TA = 85°C
30
20
10
0
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
3
3.5
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
Figure 8. Typical Low-Level Output Current vs Low-Level
Output Voltage
Figure 9. Typical Low-Level Output Current vs Low-Level
Output Voltage
0
0
VCC = 2.2 V
P1.7
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
VCC = 3 V
P1.7
−5
−10
−15
TA = 85°C
−20
TA = 25°C
−25
0
0.5
VCC = 3 V
P1.7
−10
−20
−30
TA = 85°C
−40
TA = 25°C
−50
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
3
3.5
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
Figure 10. Typical High-Level Output Current vs High-Level
Output Voltage
Figure 11. Typical High-Level Output Current vs High-Level
Output Voltage
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
21
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
9.13 POR, BOR (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
See Figure 12
dVCC/dt ≤ 3 V/s
0.7 ×
V(B_IT-)
V(B_IT-)
See Figure 12 through Figure 14
dVCC/dt ≤ 3 V/s
1.35
V
Vhys(B_IT-)
See Figure 12
dVCC/dt ≤ 3 V/s
130
mV
td(BOR)
See Figure 12
t(reset)
Pulse duration needed at RST/NMI pin to
accepted reset internally
(1)
(2)
V
2000
2.2 V, 3 V
2
µs
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-)is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 12. POR and BOR vs Supply Voltage
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
t pw − Pulse Width − µs
1000
1 ns
1 ns
t pw − Pulse Width − µs
Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal
22
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
t pw − Pulse Width − µs
1000
tf
tr
t pw − Pulse Width − µs
Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
23
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
9.14 Main DCO Characteristics
•
•
•
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
DCO control bits DCOx have a step size as defined by parameter SDCO.
Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage =
32 × fDCO(RSEL,DCO) × fDCO(RSEL,DCO+1)
MOD × fDCO(RSEL,DCO) + (32 – MOD) × fDCO(RSEL,DCO+1)
9.15 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
V
RSELx = 14
2.2
3.6
V
RSELx = 15
3
3.6
V
0.06
0.14
MHz
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3V
0.12
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3V
0.15
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3V
0.21
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3V
0.3
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3V
0.41
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3V
0.58
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3V
0.8
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3V
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3V
1.6
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3V
2.3
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3V
3.4
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3V
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3V
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3V
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3V
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
15.25
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
21
MHz
SRSEL
Frequency step between
range RSEL and
RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
ratio
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
ratio
Duty cycle
Measured at SMCLK output
3V
50
24
Submit Documentation Feedback
0.8
1.5
4.25
4.3
MHz
7.3
7.8
8.6
MHz
MHz
MHz
13.9
MHz
%
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
9.16 Calibrated DCO Frequencies - Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over temperature (1)
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
1-MHz tolerance over VCC
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
30°C
1.8 V to 3.6 V
-3
±2
+3
%
1-MHz tolerance overall
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz,
calibrated at 30°C and 3 V
-40°C to 85°C
1.8 V to 3.6 V
-6
±3
+6
%
(1)
This is the frequency change from the measured frequency at 30°C over temperature.
9.17 Wakeup From Lower-Power Modes (LPM3 or LPM4) Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDCO,LPM3/4
DCO clock wake-up time from LPM3
or LPM4 (1)
tCPU,LPM3/4
CPU wake-up time from LPM3 or
LPM4 (2)
(1)
(2)
VCC
BCSCTL1= CALBC1_1MHz,
DCOCTL = CALDCO_1MHz
MIN
TYP
3V
MAX
1.5
UNIT
µs
1/fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
9.18 Typical Characteristics - DCO Clock Wakeup Time From LPM3 or LPM4
DCO Wake Time − µs
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 15. DCO Wakeup Time From LPM3 vs DCO Frequency
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
25
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
9.19 Crystal Oscillator, XT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
Integrated effective load
capacitance, LF mode (2)
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
TYP
1.8 V to 3.6 V
1.8 V to 3.6 V
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at ACLK,
fLFXT1,LF = 32768 Hz
2.2 V
30
Oscillator fault frequency,
LF mode (3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
2.2 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
9.20 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TA
VCC
MIN
TYP
MAX
fVLO
VLO frequency
PARAMETER
-40°C to 85°C
3V
4
12
20
dfVLO/dT
VLO frequency temperature drift
-40°C to 85°C
3V
25°C
1.8 V to 3.6 V
dfVLO/dVCC VLO frequency supply voltage drift
UNIT
kHz
0.5
%/°C
4
%/V
9.21 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK or ACLK,
External: TACLK or INCLK,
Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TA0, TA1
26
Submit Documentation Feedback
VCC
MIN
TYP
fSYSTEM
3V
20
MAX
UNIT
MHz
ns
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
9.22 Comparator_A+ (MSP430G2x11 only)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
I(DD)
CAON = 1, CARSEL = 0, CAREF = 0
3V
45
µA
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0, CAREF = 1, 2,
or 3,
No load at CA0 and CA1
3V
45
µA
V(IC)
Common-mode input voltage
CAON = 1
3V
V(Ref025)
Voltage @ 0.25 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at CA0 and CA1
3V
0.24
V(Ref050)
Voltage @ 0.5 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at CA0 and CA1
3V
0.48
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at CA0 and CA1, TA = 85°C
3V
490
mV
3V
±10
mV
3V
0.7
mV
120
ns
1.5
µs
V(RefVT)
See Figure 16 and Figure 17
V(offset)
Offset voltage (1)
Vhys
Input hysteresis
t(response)
(1)
CAON = 1
Response time
(low-high and high-low)
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
TA = 25°C, Overdrive 10 mV,
With filter: CAF = 1
0
VCC-1
V
3V
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The
two successive measurements are then summed together.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
27
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
9.23 Typical Characteristics - Comparator_A+
650
650
VCC = 2.2 V
V(RefVT) – Reference Voltage – mV
V(RefVT) – Reference Voltage – mV
VCC = 3 V
600
Typical
550
500
450
400
-45
600
Typical
550
500
450
400
-25
-5
15
35
55
75
TA – Free-Air Temperature – °C
95
-45
115
Figure 16. Reference Voltage vs Temperature, VCC = 3 V
-25
-5
15
35
55
75
TA – Free-Air Temperature – °C
95
115
Figure 17. Reference Voltage vs Temperature, VCC = 2.2 V
Short Resistance – kW
100
VCC = 1.8 V
VCC = 2.2 V
VCC = 3 V
10
VCC = 3.6 V
1
0
0.2
0.4
0.6
0.8
1
VIN/VCC – Normalized Input Voltage – V/V
Figure 18. Short Resistance vs Normalized Input Voltage
28
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
9.24 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V, 3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V, 3.6 V
1
7
mA
10
ms
(1)
tCPT
Cumulative program time
tCMErase
Cumulative mass erase time
2.2 V, 3.6 V
2.2 V, 3.6 V
20
104
Program and erase endurance
cycles
tRetention
Data retention duration
tWord
Word or byte program time (2)
30
tFTG
tBlock,
Block program time for first byte or word (2)
25
tFTG
Block program time for each additional
byte or word (2)
18
tFTG
0
tBlock, 1-63
tBlock,
End
tMass Erase
tSeg
(1)
(2)
Erase
Block program end-sequence wait time
TJ = 25°C
ms
105
15
(2)
Mass erase time (2)
Segment erase time
years
(2)
6
tFTG
10593
tFTG
4819
tFTG
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word write, byte write, and block write modes.
These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
9.25 RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage (1)
TEST CONDITIONS
CPU halted
MIN
MAX
1.6
UNIT
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
29
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
9.26 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V, 3 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V, 3 V
15
100
2.2 V
0
5
MHz
3V
0
10
MHz
2.2 V, 3 V
25
90
kΩ
fTCK
TCK input frequency (2)
RInternal
Internal pulldown resistance on TEST
(1)
(2)
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
9.27 JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
30
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
After the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, or emulation feature is possible, and JTAG is switched to
bypass mode.
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
10 I/O Port Schematics
10.1 Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger - MSP430G2x01
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
DVSS
0
DVCC
1
1
0
1
From Timer
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 14. Port P1 (P1.0 to P1.3) Pin Functions - MSP430G2x01
PIN NAME (P1.x)
x
P1.0/
TA0CLK/
0
P1DIR.x
P1SEL.x
P1.x (I/O)
I: 0; O: 1
0
TA0CLK
0
1
ACLK
ACLK
P1.1/
P1.x (I/O)
TA0.0
1
P1.2/
TA0.1
P1.3
CONTROL BITS/SIGNALS
FUNCTION
1
1
I: 0; O: 1
0
TA0.CCI0A
0
1
TA0.0
1
1
P1.x (I/O)
2
3
I: 0; O: 1
0
TA0.CCI1A
0
1
TA0.1
1
1
I: 0; O: 1
0
P1.x (I/O)
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
31
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
10.2 Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger - MSP430G2x01
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
0
From Module
1
DVSS
0
DVCC
1
1
P1.4/SMCLK/TCK
P1.5/TA0.0/TMS
P1.6/TA0.1/TDI/TCLK
P1.7/TDO/TDI
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
Table 15. Port P1 (P1.4 to P1.7) Pin Functions - MSP430G2x01
PIN NAME (P1.x)
x
P1.4/
FUNCTION
P1.x (I/O)
SMCLK/
4
SMCLK
TCK
TCK
P1.5/
P1.x (I/O)
TA0.0/
5
TMS
P1.6/
6
TDI/TCLK
P1.7/
TDO/TDI
(1)
32
7
P1DIR.x
P1SEL.x
JTAG Mode
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
TA0.0
1
1
0
TMS
X
X
1
P1.x (I/O)
TA0.1/
CONTROL BITS / SIGNALS (1)
I: 0; O: 1
0
0
TA0.1
1
1
0
TDI/TCLK
X
X
1
P1.x (I/O)
I: 0; O: 1
0
0
TDO/TDI
X
X
1
X = Don't care
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
10.3 Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger - MSP430G2x11
To Comparator
From Comparator
CAPD.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
0
ACLK
1
DVSS
0
DVCC
1
Bus
Keeper
EN
1
P1.0/TA0CLK/ACLK/CA0
P1.1/TA0.0/CA1
P1.2/TA0.1/CA2
P1.3/CAOUT/CA3
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
33
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger MSP430G2x11 (continued)
Table 16. Port P1 (P1.0 to P1.3) Pin Functions - MSP430G2x11
PIN NAME (P1.x)
x
FUNCTION
P1.0/
P1.x (I/O)
TA0CLK/
TA0.TACLK
ACLK/
0
CONTROL BITS / SIGNALS (1)
P1DIR.x
P1SEL.x
CAPD.y
I: 0; O: 1
0
0
0
1
0
ACLK
1
1
0
CA0
CA0
X
X
1 (y = 0)
P1.1/
P1.x (I/O)
I: 0; O: 1
0
0
TA0.0/
TA0.0
1
1
0
1
TA0.CCI0A
0
1
0
CA1
CA1
X
X
1 (y = 1)
P1.2/
P1.x (I/O)
I: 0; O: 1
0
0
TA0.1
1
1
0
TA0.CCI1A
0
1
0
CA2
X
X
1 (y = 2)
0
TA0.1/
2
CA2
P1.3/
P1.x (I/O)
CAOUT/
CA3
(1)
34
3
I: 0; O: 1
0
CAOUT
1
1
0
CA3
X
X
1 (y = 3)
X = Don't care
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
10.4 Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger - MSP430G2x11
To Comparator
From Comparator
CAPD.y
PxSEL.y
PxDIR.y
1
Direction
0: Input
1: Output
0
PxREN.y
PxSEL.y
PxOUT.y
From Module
DVSS
0
DV CC
1
1
0
1
P1.4/SMCLK/CA4/TCK
P1.5/TA0.0/CA5/TMS
P1.6/TA0.1/CA6/TDI/TCLK
P1.7/CAOUT/CA7/TDO/TDI
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
From JTAG
To JTAG
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
35
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
Port P1 Pin Schematic: P1.4 to P1.7, Input/Output With Schmitt Trigger MSP430G2x11 (continued)
Table 17. Port P1 (P1.4 to P1.7) Pin Functions - MSP430G2x11
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
JTAG Mode
CAPD.y
I: 0; O: 1
0
0
0
SMCLK
1
1
0
0
P1.4/
P1.x (I/O)
SMCLK/
CA4/
4
CONTROL BITS / SIGNALS (1)
CA4
X
X
0
1 (y = 4)
TCK
TCK
X
X
1
0
P1.5/
P1.x (I/O)
I: 0; O: 1
0
0
0
TA0.0/
TA0.0
1
1
0
0
5
CA5/
CA5
X
X
0
1 (y = 5)
TMS
TMS
X
X
1
0
P1.6/
P1.x (I/O)
I: 0; O: 1
0
0
0
TA0.1/
TA0.1
1
1
0
0
CA6
X
X
0
1 (y = 6)
TDI/TCLK
TDI/TCLK
X
X
1
0
P1.7/
P1.x (I/O)
I: 0; O: 1
0
0
0
CAOUT/
CAOUT
1
1
0
0
CA7
X
X
0
1 (y = 7)
TDO/TDI
X
X
1
0
6
CA6/
CA7/
TDO/TDI
(1)
36
7
X = Don't care
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
10.5 Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger - MSP430G2x01 and
MSP430G2x11
XOUT/P2.7
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
PxSEL.6
PxDIR.y
1
0
Direction
0: Input
1: Output
PxREN.y
PxSEL.6
PxOUT.y
0
From Module
1
DV SS
0
DV CC
1
1
Bus
Keeper
EN
XIN/P2.6/TA0.1
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
Set
PxIFG.y
PxSEL.y
PxIES.y
Interrupt
Edge
Select
Table 18. Port P2 (P2.6) Pin Functions - MSP430G2x01 and MSP430G2x11
PIN NAME (P2.x)
x
XIN
XIN
P2.6
TA0.1
(1)
FUNCTION
6
P2.x (I/O)
Timer0_A2.TA1
CONTROL BITS / SIGNALS (1)
P2DIR.x
P2SEL.6
P2SEL.7
0
1
1
I: 0; O: 1
0
X
1
1
X
X = Don't care
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
37
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
10.6 Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger - MSP430G2x01 and
MSP430G2x11
XIN/P2.6/TA0.1
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
PxDIR.y
1
0
from P2.6/XIN
1
PxSEL.7
Direction
0: Input
1: Output
PxREN.y
PxSEL.7
PxOUT.y
0
From Module
1
DVSS
0
DV CC
1
1
Bus
Keeper
EN
XOUT/P2.7
PxIN.y
To Module
PxIE.y
EN
PxIRQ.y
Q
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Table 19. Port P2 (P2.7) Pin Functions - MSP430G2x01 and MSP430G2x11
PIN NAME (P2.x)
XOUT
P2.7
38
x
7
FUNCTION
XOUT
P2.x (I/O)
Submit Documentation Feedback
CONTROL BITS / SIGNALS
P2DIR.x
P2SEL.6
P2SEL.7
1
1
1
I: 0; O: 1
0
0
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
11.1.1.1 Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
Architecture
4-Wire
JTAG
2-Wire
JTAG
Breakpoints
(N)
Range
Breakpoints
Clock
Control
State
Sequencer
Trace
Buffer
LPMx.5
Debugging
Support
MSP430
Yes
Yes
2
No
Yes
No
No
No
11.1.1.2 Recommended Hardware Options
11.1.1.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also feature
header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG
programmer and debugger included. The following table shows the compatible target boards and the supported
packages.
Package
Target Board and Programmer Bundle
14-pin TSSOP (PW)
Target Board Only
MSP-FET430U14
MSP-TS430PW14
MSP-FET430U28A
MSP-TS430PW28A
11.1.1.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional
hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools
for details.
11.1.1.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full
list of available tools at www.ti.com/msp430tools.
11.1.1.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
Part Number
PC Port
MSP-GANG
Serial and USB
Features
Provider
Program up to eight devices at a time. Works with PC or standalone.
Texas Instruments
11.1.1.3 Recommended Software Options
11.1.1.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also available.
This device is supported by Code Composer Studio™ IDE (CCS).
11.1.1.3.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices
delivered in a convenient package. MSP430Ware is available as a component of CCS or as a standalone
package.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
39
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
11.1.1.3.3 Command-Line Programmer
MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a
FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to
download binary files (.txt or .hex) files directly to the MSP430 Flash without the need for an IDE.
11.1.2 Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430™ MCU devices and support tools. Each MSP430™ MCU commercial family member has one of three
prefixes: MSP, PMS, or XMS (for example, MSP430F5259). Texas Instruments recommends two of three
possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZP) and temperature range (for example, T). Figure 19 provides a legend for reading the
complete device name for any family member.
40
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
www.ti.com
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
MSP 430 F 5 438 A I ZQW T XX
Processor Family
Optional: Additional Features
430 MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
TI’s Low Power Microcontroller Platform
430 MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz w/ LCD
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz w/ LCD
0 = Low Voltage Series
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = -40°C to 85°C
T = -40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel (7 inch)
R = Large Reel (11 inch)
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (-40°C to 105°C)
-HT = Extreme Temperature Parts (-55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 19. Device Nomenclature
11.2 Documentation Support
11.2.1 Related Documents
The following documents describe the MSP430G2x11 and MSP430G2x01 devices. Copies of these documents
are available on the Internet at www.ti.com.
SLAU144 MSP430x2xx Family User's Guide. Detailed information on the modules and peripherals available in
this device family.
SLAZ413 MSP430G2211 Device Erratasheet. Describes the known exceptions to the functional specifications
for the MSP430G2211 device.
SLAZ410 MSP430G2201 Device Erratasheet. Describes the known exceptions to the functional specifications
for the MSP430G2201 device.
SLAZ399 MSP430G2001 Device Erratasheet. Describes the known exceptions to the functional specifications
for the MSP430G2001 device.
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
41
MSP430G2211-Q1, MSP430G2201-Q1, MSP430G2001-Q1
SLAS775E – AUGUST 2011 – REVISED MARCH 2014
www.ti.com
11.3 Related Links
Table 20 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 20. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430G2211-Q1
Click here
Click here
Click here
Click here
Click here
MSP430G2201-Q1
Click here
Click here
Click here
Click here
Click here
MSP430G2001-Q1
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you
can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
11.5 Trademarks
MSP430, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
42
Submit Documentation Feedback
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: MSP430G2211-Q1 MSP430G2201-Q1 MSP430G2001-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430G2001IPW4RQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
G2001Q1
MSP430G2001IRSARQ1
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430G
2001Q1
MSP430G2201IRSARQ1
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430G
2201Q1
MSP430G2211IPW4RQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
G2211Q1
MSP430G2211IRSARQ1
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430G
2211Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430G2001-Q1, MSP430G2201-Q1, MSP430G2211-Q1 :
• Catalog: MSP430G2001, MSP430G2201, MSP430G2211
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Mar-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430G2001IPW4RQ1 TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430G2001IRSARQ1
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430G2201IRSARQ1
QFN
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
MSP430G2211IPW4RQ1 TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MSP430G2211IRSARQ1
RSA
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
QFN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Mar-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430G2001IPW4RQ1
MSP430G2001IRSARQ1
TSSOP
PW
14
2000
367.0
367.0
35.0
QFN
RSA
16
3000
367.0
367.0
35.0
MSP430G2201IRSARQ1
QFN
RSA
16
3000
367.0
367.0
35.0
MSP430G2211IPW4RQ1
TSSOP
PW
14
2000
367.0
367.0
35.0
MSP430G2211IRSARQ1
QFN
RSA
16
3000
367.0
367.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated