TI1 DCP021212DP Dcp02x 2-w, isolated, unregulated dc/dc converter module Datasheet

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DCP020503, DCP020505, DCP020507, DCP020509, DCP020515D, DCP021205
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DCP02x 2-W, Isolated, Unregulated DC/DC Converter Modules
1 Features
3 Description
•
•
•
•
•
The DCP02 series is a family of 2-W, isolated,
unregulated DC/DC converter modules. Requiring a
minimum of external components and including onchip device protection, the DCP02 series of devices
provide extra features such as output disable and
synchronization of switching frequencies.
1
1-kV Isolation (Operational)
Device-to-Device Synchronization
EN55022 Class B EMC Performance
UL1950 Recognized Component
7-Pin PDIP and 12-Pin SOP Packages
This combination of features and small size makes
the DCP02 series of devices suitable for a wide range
of applications, and is an easy-to-use solution in
applications requiring signal path isolation.
2 Applications
•
•
•
•
•
Signal Path Isolation
Ground Loop Elimination
Data Acquisition
Industrial Control and Instrumentation
Test Equipment
WARNING: This product has operational isolation
and is intended for signal isolation only. It should not
be used as a part of a safety isolation circuit requiring
reinforced isolation. See definitions in the Feature
Description section.
Device Information(1)
PART NUMBER
DCP02xxxx
PACKAGE
BODY SIZE (NOM)
PDIP (7)
19.18 mm × 10.60 mm
SOP (12)
17.90 mm × 10.33 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
.
.
Single Output Block Diagram
OSC
800
kHz
SYNC
Divideby-2
Reset
Watchdog
Startup
Dual Output Block Diagram
+VOUT
Power
Stage
OSC
800
kHz
SYNC
Divideby-2
Reset
±VOUT
Watchdog
Startup
+VOUT
Power
Stage
COM
±VOUT
PSU
Thermal
Shutdown
+VS
PSU
Thermal
Shutdown
+VS
Power Controller
Power Controller
±VS
±VS
.
.
.
.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagrams ....................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 11
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support .......................................
Community Resources..........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision K (February 2008) to Revision L
Page
•
Updated Features .................................................................................................................................................................. 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Added Dual Output Block Diagram......................................................................................................................................... 1
•
Renamed pin "0V" to "COM" (output side common pin) in table............................................................................................ 4
•
Renamed pin "VS" to "+VS" (input voltage pin) in table .......................................................................................................... 4
•
Renamed pin "0V" to "–VS" (input side common pin) in table ................................................................................................ 4
•
Added Recommended Operating Conditions table ................................................................................................................ 5
•
Added Thermal Information table ........................................................................................................................................... 5
•
Added information to the ISOLATION section of the Electrical Characteristics table ........................................................... 6
•
Added Isolation section to the Feature Description section ................................................................................................... 9
•
Added a typical application design to the Application Information section........................................................................... 13
2
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5 Device Comparison Table
OUTPUT
VOLTAGE
VNOM @ VS (TYP)(V)
75% LOAD
INPUT
VOLTAGE
VS (V)
DEVICE
NUMBER
MIN
NO LOAD
CURRENT
IQ (mA)
0% LOAD
EFFICIENCY
(%)
100% LOAD
BARRIER
CAPACITANCE
CISO (pF)
VISO = 750Vrms
TYP
MAX
MAX
TYP
MAX
TYP
TYP
TYP
DCP020503P
DCP020503U
3.13
3.3
3.46
600
19
30
18
74
26
DCP020505P
DCP020505U
4.75
5
5.25
400
14
20
18
80
22
6.65
7
7.35
285
14
25
20
81
30
8.55
9
9.45
222
12
20
23
82
31
±14.25
±15
±15.75
133 (3)
11
20
27
85
24
4.75
5
5.25
400
7
15
14
83
33
11.4
12
12.6
166
7
20
15
87
47
±11.4
±12
±12.6
166 (3)
6
20
16
88
35
14.25
15
15.75
133
6
20
15
88
42
4.75
5
5.25
400
6
15
13
81
33
±4.75
±5
±5.25
400 (3)
6
15
12
80
22
±14.25
±15
±15.75
133 (3)
6
25
16
79
44
4.5
5
MAX
LOAD
REGULATION
10% TO 100%
LOAD (2)
MIN
DCP020507P
DCP020507U
TYP
DEVICE
OUTPUT
CURRENT
(mA) (1)
5.5
DCP020509P
DCP020509U
DCP020515DP
DCP020515DU
DCP021205P
DCP021205U
DCP021212P
DCP021212U
10.8
12
13.2
DCP021212DP
DCP021212DU
DCP021515P
DCP021515U
13.5
15
16.5
DCP022405P
DCP022405U
DCP022405DP
DCP022405DU
DCP022415DP
DCP022415DU
(1)
(2)
(3)
21.6
24
26.4
POUT(max) = 2 W
Load regulation = (VOUT at 10% load – VOUT at 100%)/VOUT at 75% load
IOUT1 + IOUT2
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6 Pin Configuration and Functions
NVA Package
7-Pin PDIP (Single Output)
(Top View)
+VS 1
–VS
NVA Package
7-Pin PDIP (Dual Output)
(Top View)
14 SYNC
+VS 1
2
–VS
2
DCP02
–VOUT
DCP02
5
COM
+VOUT 6
NC
–VS
–VS
5
+VOUT 6
7
8
-VOUT 7
NC
DVB PACKAGE
12-Pin SOP (Single Output)
(Top View)
+VS
14 SYNC
1
2
3
8
NC
DVB Package
12-Pin SOP (Dual Output)
(Top View)
28 SYNC
+VS 1
28 SYNC
27 NC
–VS 2
27 NC
26 NC
–VS 3
26 NC
DCP02
DCP02
–VOUT 12
+VOUT 13
NC 14
17 NC
COM 12
17 NC
16 NC
+VOUT 13
16 NC
15 NC
-VOUT 14
15 NC
Pin Functions
PIN
NAME
COM
NUMBER
DVB
(DUAL)
DVB
(SINGLE)
NVA
(DUAL)
NVA
(SINGLE)
I/O (1)
—
5
—
O
Output side common
—
No connection
12
15
DESCRIPTION
14
15
7
16
16
17
17
26
26
27
27
SYNC
28
28
14
14
I
Synchronization Pin - Synchronize multiple devices by connecting
their SYNC pins together. Pulling this pin low disables the internal
oscillator.
+VOUT
13
13
6
6
O
Positive output voltage
–VOUT
14
12
7
5
O
Negative output voltage
+VS
1
1
1
1
I
Input voltage
2
2
3
3
2
2
I
Input side common
NC
–VS
(1)
4
8
8
I = Input, O = Output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Input voltage
7
12-V input devices
15
15-V input devices
18
24-V input devices
29
Storage temperature, Tstg
(1)
MAX
5-V input devices
–60
UNIT
V
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input Voltage
NOM
MAX
5-V input devices
4.5
5
5.5
12-V input devices
10.8
12
13.2
15-V input devices
13.5
15
16.5
24-V input devices
21.6
24
26.4
Operating temperature
–40
UNIT
V
85
°C
7.4 Thermal Information
THERMAL METRIC (1)
DCP020x
DCP020x
NVA (PDIP)
DVB (SOP)
7 PINS
12 PINS
RθJA
Junction-to-ambient thermal resistance
61
61
RθJC(top)
Junction-to-case (top) thermal resistance
19
19
RθJB
Junction-to-board thermal resistance
24
24
ψJT
Junction-to-top characterization parameter
7
7
ψJB
Junction-to-board characterization parameter
24
24
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
POUT
Output power
ILOAD = 100% (full load)
VRIPPLE
Output voltage ripple
COUT = 1 μF, ILOAD = 50%
Voltage vs. Temperature
2
W
20
mVPP
–40°C ≤ TA ≤ 25°C
0.046
%/°C
25°C ≤ TA ≤ 85°C
0.016
%/°C
INPUT
VS
Input voltage range
–10%
10%
ISOLATION
Voltage
1-second flash test
VISO
Isolation
1
kVrms
dV/dt
500
Leakage Current
30
nA
DC
60
VDC
AC
42.5
VAC
Continuous working
voltage across isolation
barrier
V/s
LINE REGULATION
Output voltage
IOUT ≥ 10% load current and constant,
VS (min) to VS (typ)
1%
15%
IOUT ≥ 10% load current and constant,
VS (typ) to VS (max)
1%
15%
RELIABILITY
Demonstrated
TA = 55°C
75
FITS
THERMAL SHUTDOWN
TSD
Die temperature at
shutdown
ISD
Shutdown current
150
°C
3
mA
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
fOSC
Oscillator frequency
VIL
Low-level input voltage, SYNC
ISYNC
Input current, SYNC
tDISABLE
Disable time
CSYNC
(1)
6
Capacitance loading on SYNC pin
TEST CONDITIONS
MIN
fSW = fOSC/2
TYP
0
VSYNC = 2 V
(1)
External
MAX
800
UNIT
kHz
0.4
V
75
µA
2
µs
3
pF
The application report External Synchronization of the DCP01/02 Series of DC/DC Converters(SBAA035) describes this configuration.
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7.7 Typical Characteristics
TA = 25°C, unless otherwise noted.
5.04
Series 1
Series 2
Series 3
50
40
5.02
Output Voltage (V)
Peak Emission Level (dB/µA)
60
30
20
10
0
5.00
4.98
4.96
4.94
4.92
±10
±20
0.15
1
Frequency (MHz)
DCP020505P
10
4.90
±40
30
ILOAD = 400 mA
2.5
5.3
2.0
5.2
5.1
5.0
1.5
1.0
0.5
4.9
0
20
40
60
Load (%)
DCP021205P
80
0
±50
100
Figure 3. Output Voltage vs. Output Current
0
25
50
Temperature (°C)
DCP021205P
75
±25
100
ILOAD = 400 mA
Figure 4. Output Power vs. Temperature
100
450
COUT = 1 µF
COUT = 0.1 µF
Output AC Ripple (mVP-P)
400
80
Efficiency (%)
20
40
60
80
100
Temperature (°C)
DCP020505P
75% Load Current
Figure 2. Output Voltage vs. Temperature
5.4
Output Power (W)
Output Voltage (V)
Figure 1. Conducted Emmisions vs. Frequency
0
±20
60
40
20
DCP021212DP
DCP021205P
0
350
300
250
200
150
100
50
0
0
25
50
Load (%)
75
100
0
100
200
300
Load Current (mA)
DCP020505P
400
(20 MHz
bandwidth)
Figure 5. Efficiency vs. Percent Load Current
Figure 6. Output AC Ripple vs. Load Current
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8 Detailed Description
8.1 Overview
The DCP02 offers up to 2 W of isolated, unregulated output power from a 5-V, 12-V, 15-V, or 24-V input source
with a typical efficiency of up to 89%. This efficiency is achieved through highly integrated packaging technology
and the implementation of a custom power stage and control device. The DCP02 devices are specified for
operational isolation only. The circuit design uses an advanced BiCMOS/DMOS process.
8.2 Functional Block Diagrams
SYNC
Oscillator
800 kHz
+VOUT
Divide-by-2
Reset
Watchdog
Startup
Power
Stage
–VOUT
PSU Thermal
Shutdown
+VS
Power Controller
–VS
Figure 7. Single Output Device
SYNC
Oscillator
800 kHz
+VOUT
Divide-by-2
Reset
Watchdog
Startup
Power
Stage
COM
–VOUT
PSU Thermal
Shutdown
+VS
Power Controller
–VS
Figure 8. Dual Output Device
8
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8.3 Feature Description
8.3.1 Isolation
Underwriters Laboratories, UL™ defines several classes of isolation that are used in modern power supplies.
Safety extra low voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit which is so
designated and protected that under normal and single fault conditions the voltage between any two accessible
parts, or between an accessible part and the equipment earthing terminal for operational isolation does not
exceed steady state 42 V peak or 60 VDC for more than 1 second.
8.3.1.1 Operation or Functional Isolation
Operational or functional isolation is defined by the use of a high-potential (hipot) test only. Typically, this
isolation is defined as the use of insulated wire in the construction of the transformer as the primary isolation
barrier. The hipot one-second duration test (dielectric voltage, withstand test) is a production test used to verify
that the isolation barrier is functioning. Products with operational isolation should never be used as an element in
a safety-isolation system.
8.3.1.2 Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and
secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the insulated
wire in the construction of the transformer. Input and output circuits must also be physically separated by
specified distances.
8.3.1.3 Continuous Voltage
For a device that has no specific safety agency approvals (operational isolation), the continuous voltage that can
be applied across the part in normal operation is less than 42.4 VRMS, or 60 VDC. Ensure that both input and
output voltages maintain normal SELV limits. The isolation test voltage represents a measure of immunity to
transient voltages.
WARNING
Do not use the device as an element of a safety isolation system when SELV is
exceeded
If the device is expected to function correctly with more than 42.4 VRMS or 60 VDC applied continuously across the
isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe
voltage, and further isolation or insulation systems must form a barrier between these circuits and any useraccessible circuitry according to safety standard requirements.
8.3.1.4 Isolation Voltage
Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation test voltage
are all terms that relate to the same thing: a test voltage applied for a specified time across a component
designed to provide electrical isolation to verify the integrity of that isolation. TI’s DCP02 series of dc-dc
converters are all 100% production tested at 1.0 kVAC for one second.
8.3.1.5 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending on
materials, construction, and environment. The DCP02 series of dc-dc converters have toroidal, enameled, wire
isolation transformers with no additional insulation between the primary and secondary windings. While a device
can be expected to withstand several times the stated test voltage, the isolation capability depends on the wire
insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual chemical
degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-voltage tests
and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage by 20% from
specified test voltage with a duration limit of one second per test.
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Feature Description (continued)
8.3.2 Power Stage
The DCP02 series of devices use a push-pull, center-tapped topology. The DCP02 devices switch at 400 kHz
(divide-by-2 from an 800-kHz oscillator).
8.3.3 Oscillator And Watchdog Circuit
The onboard, 800-kHz oscillator generates the switching frequency via a divide-by-2 circuit. The oscillator can be
synchronized to other DCP02-series device circuits or an external source, and is used to minimize system noise.
A watchdog circuit checks the operation of the oscillator circuit. The oscillator can be disabled by pulling the
SYNC pin low. When the SYNC pin goes low, the output pins transition into tri-state mode, which occurs within
2 μs.
8.3.4 Thermal Shutdown
The DCP02 series of devices are protected by a thermal-shutdown circuit.
If the on-chip temperature rises above 150°C, the device shuts down. Normal operation resumes as soon as the
temperature falls below 150°C.
8.3.5 Synchronization
In the event that more than one DC/DC converter is needed onboard, beat frequencies and other electrical
interference can be generated. This interference occurs because of the small variations in switching frequencies
between the DC/DC converters.
The DCP02 series of devices overcome this interference by allowing devices to be synchronized to one another.
Up to eight devices can be synchronized by connecting the SYNC pins together, taking care to minimize the
capacitance of tracking. Stray capacitance (greater than 3 pF) has the effect of reducing the switching frequency,
or even stopping the oscillator circuit. The maximum recommended voltage applied to the SYNC pin is 3.0 V.
For an application that uses more than eight synchronized devices use an external device to drive the SYNC
pins. The application report External Synchronization of the DCP01/02 Series of DC/DC Converters (SBAA035)
describes this configuration.
NOTE
During the start-up period, all synchronized devices draw maximum current from
the input simultaneously. If the input voltage falls below approximately 4 V, the
devices may not start up. A 2.2-μF capacitor should be connected close to each
device's input pin.
8.3.6 Construction
The basic construction of the DCP02 series of devices is the same as standard integrated circuits. The molded
package contains no substrate. The DCP02 series of devices are constructed using an IC, rectifier diodes, and a
wound magnetic toroid on a leadframe. Because the package contains no solder, the devices do not require any
special printed circuit board (PCB) assembly processing. This architecture results in an isolated DC/DC converter
with inherently high reliability.
8.3.7 Thermal Management
Due to the high power density of this device, it is advisable to provide ground planes on the input and output.
10
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DCP020503, DCP020505, DCP020507, DCP020509, DCP020515D, DCP021205
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8.4 Device Functional Modes
8.4.1 Disable/Enable (SYNC pin)
Any of the DCP02 series devices can be disabled or enabled by driving the SYNC pin using an open drain
CMOS gate. If the SYNC pin is pulled low, the DCP02 becomes disabled. The disable time depends upon the
external loading. The internal disable function is implemented in 2 μs. Removal of the pull down causes the
DCP02 to be enabled.
Capacitive loading on the SYNC pin should be minimized (≤ 3 pF) in order to prevent a reduction in the oscillator
frequency. The application report External Synchronization of the DCP01/02 Series of DC/DC Converters
(SBAA035) describes disable/enable control circuitry.
8.4.2 Decoupling
8.4.2.1 Ripple Reduction
The high switching frequency of 400 kHz allows simple filtering. To reduce ripple, it is recommended that a
minimum of 1-μF capacitor be used on the VOUT pin. For dual output devices, decouple both of the outputs to the
COM pin. A 2.2-μF capacitor on the input is also recommended.
8.4.2.2 Connecting the DCP02 in Series
Multiple DCP02 isolated 2W DC/DC converters can be connected in series to provide non-standard voltage rails.
This configuration is possible by using the floating outputs provided by the galvanic isolation of the DCP02.
Connect the +VOUT from one DCP02 to the –VOUT of another (see Figure 9). If the SYNC pins are tied together,
the self-synchronization feature of the DCP02 prevents beat frequencies on the voltage rails. The SYNC feature
of the DCP02 allows easy series connection without external filtering, thus minimizing cost.
The outputs of a dual-output DCP02 can also be connected in series to provide two times the magnitude of VOUT,
as shown in Figure 10. For example, connect a dual-output, 15-V, DCP022415D device to provide a 30-V rail.
All 5-V, 12-V, and 15-V input voltage designs require a2.2-μF, low-ESR ceramic input capacitor, while 24-V input
applications require only 0.47 μF of input capacitance.
VIN
+VS
CIN
SYNC
CIN
+VOUT1
DCP
COUT
1.0 µF
02
–VS
–VOUT1
VS
+VOUT2
SYNC
DCP
–VS
VOUT1
+
VOUT2
COUT
1.0 µF
02
–VOUT2
Figure 9. Multiple DCP02 Devices Connected in Series
VIN
+VS
CIN
+VOUT
DCP
–VS
02
+VOUT
COUT
1.0 µF
–VOUT
–VOUT
COUT
1.0 µF
COM
Figure 10. Dual Output Devices Connected in Series
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11
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8.4.2.3 Connecting the DCP02 in Parallel
If the output power from one DCP02 is not sufficient, it is possible to parallel the outputs of multiple DCP02s, as
shown in Figure 11, ( applies to single output devices only). The SYNC feature allows easy synchronization to
prevent power-rail beat frequencies at no additional filtering cost.
All 5-V, 12-V, and 15-V input voltage designs require a 2.2-μF, low-ESR, ceramic input capacitor, while 24-V
input applications require only 0.47 μF of input capacitance.
VIN
+VS
SYNC
CIN
+VOUT1
DCP
02
–VS
COUT
1.0 µF
–VOUT1
2 × Power Out
+VS
CIN
SYNC
–VS
+VOUT2
DCP
COUT
1.0 µF
02
–VOUT2
GND
Figure 11. Multiple DCP02 Devices Connected in Parallel
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DCP020503, DCP020505, DCP020507, DCP020509, DCP020515D, DCP021205
DCP021212, DCP021212D, DCP021515, DCP022405, DCP022405D, DCP022415D
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SBVS011L – MARCH 2000 – REVISED MAY 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
VIN
+VOUT
+VS
CIN
2.2 µF
SYNC
+VOUT
DCP02
COUT
1.0 µF
–VS
–VOUT
–VOUT
Figure 12. Typical DCP020505 Application
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 and follow the design procedures shown in
Detailed Design Procedure section.
Table 1. Design Example Parameters
PARAMETER
VALUE
UNIT
5
V
V(+VS)
Input voltage
V(+VOUT)
Output voltage
5
V
IOUT
Output current rating
400
mA
fSW
Operating frequency
400
kHz
9.2.2 DCP020505 Application Curves
100
5.9
90
5.7
Output Voltage (V)
Efficiency (%)
80
70
60
50
40
5.5
5.3
5.1
4.9
4.7
30
4.5
20
0
20
40
60
80
Load Current (%)
DCP020505 Efficiency
Figure 13. DCP020505 Efficiency
Copyright © 2000–2015, Texas Instruments Incorporated
100
C001
0
20
40
60
80
Load Current (%)
100
C004
DCP020505 Load Regulation
Figure 14. DCP020505 Load Regulation
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13
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9.2.3 Detailed Design Procedure
9.2.3.1 Input Capacitor
For all 5-V, 12-V, and 15-V input voltage designs, select a 2.2-μF low-ESR ceramic input capacitor to ensure a
good startup performance. 24-V input applications require only 0.47-μF of input capacitance.
9.2.3.2 Output Capacitor
For any DCP02 design, select a 1.0-μF low-ESR ceramic output capacitor to reduce output ripple.
9.2.3.3 SYNC Pin
In a stand-alone application, leave the SYNC pin floating.
9.2.4 PCB Design
The copper losses (resistance and inductance) can be minimized by the use of mutual ground and power planes
(tracks) where possible. If that is not possible, use wide tracks to reduce the losses. If several devices are being
powered from a common power source, a star-connected system for the track must be deployed; devices must
not be connected in series, as this will cascade the resistive losses. The position of the decoupling capacitors is
important. They must be as close to the devices as possible in order to reduce losses. See the PCB Layout
section for more details.
9.2.5 Decoupling Ceramic Capacitors
Capacitor Impedance (Ÿ )
All capacitors have losses because of internal equivalent series resistance (ESR), and to a lesser degree,
equivalent series inductance (ESL). Values for ESL are not always easy to obtain. However, some
manufacturers provide graphs of frequency versus capacitor impedance. These graphs typically show the
capacitor impedance falling as frequency is increased (as shown in Figure 15). In Figure 15, XC is the reactance
due to the capacitance, XL is the reactance due to the ESL, and f0 is the resonant frequency. As the frequency
increases, the impedance stops decreasing and begins to rise. The point of minimum impedance indicates the
resonant frequency of the capacitor. This frequency is where the components of capacitance and inductance
reactance are of equal magnitude. Beyond this point, the capacitor is not effective as a capacitor.
Z
XC
XL
0
Frequency (Hz)
f0
Figure 15. Capacitor Impedance vs Frequency
At f0, XC = XL; however, there is a 180° phase difference resulting in cancellation of the imaginary component.
The resulting effect is that the impedance at the resonant point is the real part of the complex impedance;
namely, the value of the ESR. The resonant frequency must be well above the 800-kHz switching frequency of
the DCP and DCVs.
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DCP020503, DCP020505, DCP020507, DCP020509, DCP020515D, DCP021205
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The effect of the ESR is to cause a voltage drop within the capacitor. The value of this voltage drop is simply the
product of the ESR and the transient load current, as shown in Equation 1.
VIN = VPK – (ESR × ITR)
where
•
•
•
VIN is the voltage at the device input
VPK is the maximum value of the voltage on the capacitor during charge
ITR is the transient load current
(1)
The other factor that affects the performance is the value of the capacitance. However, for the input and the full
wave outputs (single-output voltage devices), ESR is the dominant factor.
9.2.6 Input Capacitor and the Effects of ESR
If the input decoupling capacitor is not ceramic (and has an ESR greater than 20 mΩ), then at the instant the
power transistors switch on, the voltage at the input pins falls momentarily. If the voltage falls below
approximately 4 V, the DCP detects an undervoltage condition and switches the DCP drive circuits to the off
state. This detection is carried out as a precaution against a genuine low input voltage condition that could slow
down or even stop the internal circuits from operating correctly. A slow-down or stoppage results in the drive
transistors being turned on too long, causing saturation of the transformer and destruction of the device.
Following detection of a low input voltage condition, the device switches off the internal drive circuits until the
input voltage returns to a safe value, at which time the device tries to restart. If the input capacitor is still unable
to maintain the input voltage, shutdown recurs. This process repeats until the input capacitor charges sufficiently
to start the device correctly.
Normal startup should occur in approximately 1 ms after power is applied to the device. If a considerably longer
startup duration time is encountered, it is likely that either (or both) the input supply or the capacitors are not
performing adequately.
For 5-V to 15-V input devices, a 2.2-μF, low-ESR ceramic capacitor ensures a good startup performance. For 24V input voltage devices, 0.47 μF ceramic capacitors are recommended. Tantalum capacitors are not
recommended, since most do not have low-ESR values and will degrade performance. If tantalum capacitors
must be used, close attention must be paid to both the ESR and voltage as derated by the vendor.
NOTE
During the start-up period, these devices may draw maximum current from the input
supply. If the input voltage falls below approximately 4 V, the devices may not start
up. Connect a 2.2-μF ceramic capacitor close to the input pins.
9.2.7 Ripple and Noise
A good quality, low-ESR ceramic capacitor placed as close as practical across the input reduces reflected ripple
and ensures a smooth startup.
A good quality, low-ESR ceramic capacitor placed as close as practical across the rectifier output terminal and
output ground gives the best ripple and noise performance. See DC-to-DC Converter Noise Reduction
(SBVA012), for more information on noise rejection.
9.2.7.1 Output Ripple Calculation Example
The following example shows that increasing the capacitance has a much smaller effect on the output ripple
voltage than does reducing the value of the ESR for the filter capacitor.
To
•
•
•
•
•
calculate the output ripple for a DCP020505 device:
VOUT = 5 V
IOUT = 0.4 A
At full output power, the load resistor is 12.5Ω
Output capacitor of 1μF, ESR of 0.1Ω
Capacitor discharge time 1% of 800 kHz (ripple frequency
tDIS = 0.0125 μs
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15
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τ = C × RLOAD
τ = 1 × 10-6 × 12.5 = 12.5 μs
VDIS = VO(1 – EXP(–tDIS/τ))
VDIS = 5 mV
By contrast, the voltage dropped because of ESR:
VESR = ILOAD × ESR
VESR = 40 mV
Ripple voltage = 45 mV
9.2.8 Dual DCP02 Output Voltage
The voltage output for dual DCP02 devices is half wave rectified; therefore, the discharge time is 1.25 μs.
Repeating the above calculations using the 100% load resistance of 25 Ω (0.2 A per output), the results are:
τ = 25 μs
tDIS = 1.25 μs
VDIS = 244 mV
VESR = 20 mV
Ripple Voltage = 266 mV
This time, it is the capacitor discharging that contributes to the largest component of ripple. Changing the output
filter to 10 μF, and repeating the calculations, the result is:
Ripple Voltage = 45 mV.
This value is composed of almost equal components.
The previous calculations are offered as a guideline only. Capacitor parameters usually have large tolerances
and can be susceptible to environmental conditions.
9.2.9 Optimizing Performance
Optimum performance can only be achieved if the device is correctly supported. The very nature of a switching
converter requires power to be instantly available when it switches on. If the converter has DMOS switching
transistors, the fast edges will create a high current demand on the input supply. This transient load placed on
the input is supplied by the external input decoupling capacitor, thus maintaining the input voltage. Therefore, the
input supply does not see this transient (this is an analogy to high-speed digital circuits). The positioning of the
capacitor is critical and must be placed as close as possible to the input pins and connected via a low-impedance
path.
The optimum performance primarily depends on two factors:
• Connection of the input and output circuits for minimal loss.
• The ability of the decoupling capacitors to maintain the input and output voltages at a constant level.
10 Power Supply Recommendations
The DCP02 is a switching power supply, and as such can place high peak current demands on the input supply.
In order to avoid the supply falling momentarily during the fast switching pulses, ground and power planes should
be used to connect the power to the input of DCP02. If this connection is not possible, then the supplies must be
connected in a star formation with the traces made as wide as possible.
16
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DCP020503, DCP020505, DCP020507, DCP020509, DCP020515D, DCP021205
DCP021212, DCP021212D, DCP021515, DCP022405, DCP022405D, DCP022415D
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11 Layout
11.1 Layout Guidelines
Due to the high power density of these devices, provide ground planes on the input and output.
Figure 19 and Figure 17 illustrate a printed circuit board (PCB) layout for the two conventional (DCP01/02,
DCV01), and two SOP surface-mount packages (DCP02U). Figure 16 shows the schematic.
Including input power and ground planes provides a low-impedance path for the input power. For the output, the
COM signal connects via a ground plane, while the connections for the positive and negative voltage outputs
conduct via wide traces in order to minimize losses.
The output should be taken from the device using ground and power planes, thereby ensuring minimum losses.
The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the
effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the
input decoupling capacitor, because this capacitor supplies the transient current associated with the fast
switching waveforms of the power drive circuits.
Allow the unused SYNC pin, to remain configured as a floating pad. It is advisable to place a guard ring
(connected to input ground) or annulus connected around this pin to avoid any noise pick up. When connecting a
SYNC pin to one or more SYNC design the linking trace to be short and narrow to avoid stray capacitance.
Ensure that no other trace is in close proximity to this trace SYNC trace to decrease the stray capacitance on
this pin. The stray capacitance affects the performance of the oscillator.
11.2 Layout Example
CON1
VS1
1
+VS SYNC 14
CON3
JP1
VS3
1
C1
+VS SYNC 28
JP1
C11
NC 27
0V1
2
0V3
–VS
DCP02xxxxP
+V1
6
C3
C2-1
+VOUT
+V3
C2
–VS
3
–VS
C12
R5
5
COM1
C5
C4-1
NC 26
13 +VOUT
C13
R1
2
DCP02xxxxU
COM
12 COM
C4
COM3
C14
R2
C15
R6
– V1
7
–VOUT
– V3
14 –VOUT
CON2
VS2
1
+VS SYNC 14
CON4
JP2
VS4
1
C6
+VS SYNC 28
JP2
C16
NC 27
0V2
2
–VS
0V4
DCP02xxxxP
+V2
6
C8
C7-1
+VOUT
C7
+V4
COM2
C10
C9-1
12 COM
COM4
R4
– V2
–VS
DCP02xxxxU
COM
C9
3
NC 26
C18
R7
5
–VS
13 +VOUT
C17
R3
2
C20
C19
R8
7
–VOUT
Figure 16. PCB Schematic, P Package
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– V4
14 –VOUT
Figure 17. PCB Schematic, U Package
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17
DCP020503, DCP020505, DCP020507, DCP020509, DCP020515D, DCP021205
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Layout Example (continued)
Figure 18. PCB Layout Example, Component-Side View
Figure 19. PCB Layout Example, Non-Component-Side View
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DCP020503, DCP020505, DCP020507, DCP020509, DCP020515D, DCP021205
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
DCP02
05
03
(D)
(P)
Basic model number: 2-W product
Voltage input:
5, 12,15, or 24
Voltage output:
3, 5, 7, 9 or 15
Output type:
S (single) or D (dual)
Package code:
P = 7-pin PDIP (NVA package)
U = 12-pin SOP (DVB package)
Figure 20. Supplemental Ordering Information
12.2 Documentation Support
12.2.1 Related Documentation
DC-to-DC Converter Noise Reduction (SBVA012)
External Synchronization of the DCP01/02 Series of DC/DC Converters (SBAA035)
Optimizing Performance of the DCP01/02 Series of DC/DC Converters (SBVA013)
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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19
DCP020503, DCP020505, DCP020507, DCP020509, DCP020515D, DCP021205
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12.4 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DCP020503
Click here
Click here
Click here
Click here
Click here
DCP020505
Click here
Click here
Click here
Click here
Click here
DCP020507
Click here
Click here
Click here
Click here
Click here
DCP020509
Click here
Click here
Click here
Click here
Click here
DCP020515D
Click here
Click here
Click here
Click here
Click here
DCP021205
Click here
Click here
Click here
Click here
Click here
DCP021212
Click here
Click here
Click here
Click here
Click here
DCP021212D
Click here
Click here
Click here
Click here
Click here
DCP021515
Click here
Click here
Click here
Click here
Click here
DCP022405
Click here
Click here
Click here
Click here
Click here
DCP022405D
Click here
Click here
Click here
Click here
Click here
DCP022415D
Click here
Click here
Click here
Click here
Click here
12.5 Trademarks
E2E is a trademark of Texas Instruments.
Underwriters Laboratories, UL are trademarks of UL LLC.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DCP020503P
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP020503P
DCP020503U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020503U
DCP020505P
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP020505P
DCP020505U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020505U
DCP020505U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020505U
DCP020505U/1KE4
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020505U
DCP020505UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020505U
DCP020507P
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP020507P
DCP020507U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020507U
DCP020507U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020507U
DCP020509P
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP020509P
DCP020509U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020509U
DCP020509U/1K
OBSOLETE
SOP
DVB
12
TBD
Call TI
Call TI
-40 to 85
DCP020515DP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP020515DP
DCP020515DU
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020515DU
DCP020515DU/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP020515DU
DCP021205P
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP021205P
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2016
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DCP021205PE4
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP021205P
DCP021205U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP021205U
DCP021205U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP021205U
DCP021212DP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP021212DP
DCP021212DU
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP021212DU
DCP021212DU/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP021212DU
DCP021212P
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP021212P
DCP021212U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP021212U
DCP021212U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP021212U
DCP021515P
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP021515P
DCP021515U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP021515U
DCP021515U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP021515U
DCP022405DP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP022405DP
DCP022405DU
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP022405DU
DCP022405P
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP022405P
DCP022405U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP022405U
DCP022415DP
ACTIVE
PDIP
NVA
7
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
DCP022415DP
DCP022415DU
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DCP022415DU
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
28-Jun-2016
Status
(1)
DCP022415DU/1K
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOP
DVB
12
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
DCP022415DU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
Samples
PACKAGE OUTLINE
DVB0012A
SOP - 2.65 mm max height
SCALE 0.900
PLASTIC SMALL OUTLINE
C
10.65
10.01
SEATING PLANE
PIN 1 ID
AREA
A
28
1
18.1
17.7
NOTE 3
0.1 C
8X 1.27
2X 16.51
14
15
B
7.6
7.4
12X
0.51
0.33
0.25
C A
B
0.32
TYP
0.23
SEE DETAIL A
2.65 MAX
8
0
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4222497/A 10/2015
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DVB0012A
SOP - 2.65 mm max height
PLASTIC SMALL OUTLINE
12X (2)
SYMM
1
28
12X (0.6)
(R0.05)
TYP
SYMM
(16.51)
8X (1.27)
14
15
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222497/A 10/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DVB0012A
SOP - 2.65 mm max height
PLASTIC SMALL OUTLINE
12X (2)
1
SYMM
28
12X (0.6)
(R0.05)
SYMM
(16.51)
8X (1.27)
14
15
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222497/A 10/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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