LM5050-1 High Side OR-ing FET Controller General Description Features The LM5050-1 High Side OR-ing FET Controller operates in conjunction with an external MOSFET as an ideal diode rectifier when connected in series with a power source. This ORing controller allows MOSFETs to replace diode rectifiers in power distribution networks thus reducing both power loss and voltage drops. The LM5050-1 controller provides charge pump gate drive for an external N-Channel MOSFET and a fast response comparator to turn off the FET when current flows in the reverse direction. The LM5050-1 can connect power supplies ranging from +5V to +75V and can withstand transients up to +100V. ■ ■ ■ ■ ■ ■ ■ Wide Operating Input Voltage range, VIN: 5V to 75V +100 Volt transient capability Charge pump gate driver for external N-Channel MOSFET Fast 50ns response to current reversal 2A peak gate turn-off current Minimum VDS clamp for faster turn-off Package: TSOT-6 (Thin SOT23-6) Applications ■ Active OR-ing of Redundant (N+1) Power Supplies Typical Application Circuits 30104804 FIGURE 1. Full Application 30104833 FIGURE 2. Typical Redundant Supply Configuration © 2012 Texas Instruments Incorporated 301048 SNVS629B www.ti.com LM5050-1 High Side OR-ing FET Controller January 12, 2012 LM5050-1 Connection Diagram Top View 30104806 LM5050MK-1 TSOT-6 Package NS Package Number MK06A Ordering Information Order Number Package Type Supplied As LM5050MK-1 TSOT-6 1000 units Tape and Reel LM5050MKX-1 TSOT-6 3000 units Tape and reel Pin Descriptions www.ti.com Pin # Name Function 1 VS The main supply pin for all internal biasing and an auxiliary supply for the internal gate drive charge pump. Typically connected to either VOUT or VIN, a separate supply can also be used. 2 GND Ground return for the controller 3 OFF A logic high state at the OFF pin will pull the GATE pin low and turn off the external MOSFET. 4 IN 5 GATE 6 OUT Voltage sense connection to the external MOSFET Source pin. Connection to the external MOSFET Gate. Voltage sense connection to the external MOSFET Drain pin. 2 IN, OUT Pins to Ground (Note 5) GATE Pin to Ground (Note 5) VS Pin to Ground OFF Pin to Ground Storage Temperature Range ESD HBM (Note 2) MM (Note 3) Peak Reflow Temperature (Note 4) -0.3V to 100V -0.3V to 100V -0.3V to 100V -0.3V to 7V −65°C to 150°C Operating Ratings 2 kV 150V 260°C, 30sec (Note 1) IN, OUT, VS Pins OFF Pin Junction Temperature Range (TJ) 5.0V to 75V 0.0V to 5.5V −40°C to +125°C Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12.0V, VVS = VIN, VOUT = VIN, VOFF = 0.0V, CGATE= 47 nF, and TJ = 25°C. Symbol Parameter Conditions Min Typ Max Unit V VS Pin VVS IVS Operating Supply Voltage Range Operating Supply Current - 5.0 - 75.0 VVS= 5.0V, VIN = 5.0V VOUT = VIN - 100 mV - 75 105 VVS= 12.0V, VIN = 12.0V VOUT = VIN - 100 mV - 100 147 VVS= 75.0V, VIN = 75.0V VOUT = VIN - 100 mV - 130 288 - 5.0 - 75.0 VIN = 5.0V VVS= VIN VOUT = VIN - 100 mV GATE = Open 32 190 305 VIN = 12.0V to 75.0V VVS= VIN VOUT = VIN - 100 mV GATE = Open 233 320 400 5.0 - 75.0 V µA μA IN Pin VIN IIN Operating Input Voltage Range IN Pin current V μA OUT Pin VOUT Operating Output Voltage Range - IOUT OUT Pin Current VIN = 5.0V to 75.0V VVS= VIN VOUT = VIN - 100 mV - 3.2 8 VIN = 5.0V VVS = VIN VGATE = VIN VOUT = VIN - 175 mV 12 30 41 VIN = 12.0V to 75.0V VVS = VIN VGATE = VIN VOUT = VIN - 175 mV 20 32 41 VIN = 5.0V VVS = VIN VOUT = VIN - 175 mV 4.0 7 9.0 VIN = 12.0V to 75.0V VVS = VIN VOUT = VIN - 175 mV 9.0 GATE Pin IGATE(ON) VGS Gate Pin Source Current VGATE - VIN in Forward Operation (Note 8) 3 µA V 12 14.0 www.ti.com LM5050-1 Absolute Maximum Ratings (Note 1) LM5050-1 Symbol Parameter Conditions Min Typ Max - 25 85 - 60 - - 180 350 - 486 - ns VGATE = VIN + 3V VOUT > VIN + 100 mV 1.8 2.8 - A VIN - VOUT -41 -28 -16 mV - 10 - mV VIN = 5.0V VVS = VIN VIN - VOUT 1 19 37 VIN = 12.0V VVS = VIN VIN - VOUT 4.4 22 37 1.56 1.75 CGATE = 0 (Note 6) tGATE(REV) Gate Capacitance Discharge Time at CGATE = 10 nF Forward to Reverse Transition (Note 6) See Figure 3 CGATE = 47 nF (Note 6) tGATE(OFF) Gate Capacitance DischargeTime at OFF pin Low to High Transition See Figure 4 IGATE(OFF) Gate Pin Sink Current VSD(REV) Reverse VSD Threshold VIN < VOUT ΔVSD(REV) Reverse VSD Hysteresis VSD(REG) CGATE = 47 nF (Note 7) Unit ns t ≤ 10ms Regulated Forward VSD Threshold VIN > VOUT mV OFF Pin OFF Input High Threshold Voltage VOUT = VIN-500 mV VOFF Rising - VOFF(IL) OFF Input Low Threshold Voltage VOUT = VIN - 500 mV VOFF Falling 1.10 1.40 ΔVOFF OFF Threshold Voltage Hysteresis VOFF(IH) IOFF OFF Pin Internal Pull-down VOFF(IH) - VOFF(IL) V - - 155 - VOFF = 4.5V 3.0 5 7.0 VOFF = 5.0V - 8 - mV µA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including in-operability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should not be operated beyond such conditions. For guaranteed specifications and conditions, see the Electrical Characteristics table. Note 2: The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Applicable test standard is JESD-22-A114-C. Note 3: The Machine Model (MM) is a 200 pF capacitor discharged through a 0Ω resistor (i.e. directly) into each pin. Applicable test standard is JESD-A115-A. Note 4: For soldering specifications see the LM5050-1 Product Folder at www.national.com, general information at www.national.com/analog/packaging/, and reflow information at www.national.com/ms/MS/MS-SOLDERING.pdf . Note 5: The GATE pin voltage is typically 12V above the IN pin voltage when the LM5050-1 is enabled (i.e. OFF Pin is Open or Low, and VIN > VOUT). Therefore, the Absolute Maximum Rating for the IN pin voltage applies only when the LM5050-1 is disabled (i.e. OFF Pin is logic high), or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is also 100V Note 6: Time from VIN-VOUT voltage transition from 200 mV to -500 mV until GATE pin voltage falls to VIN + 1V. See Figure 3 Note 7: Time from VOFF voltage transition from 0.0V to 5.0V until GATE pin voltage falls to VIN + 1V. See Figure 4 Note 8: Measurement of VGS voltage (i.e. VGATE - VIN) includes 1 MΩ in parallel with CGATE. www.ti.com 4 LM5050-1 30104825 FIGURE 3. Gate Off Timing for Forward to Reverse Transition 30104826 FIGURE 4. Gate Off Timing for OFF pin Low to High Transition 5 www.ti.com LM5050-1 Typical Performance Characteristics Unless otherwise stated: VVS = 12V, VIN = 12V, VOFF = 0.0V, and TJ = 25°C IIN vs VIN IIN vs VIN 30104834 30104819 IOUT vs VOUT IOUT vs VOUT 30104835 30104820 IVS vs VVS IVS vs VVS 30104836 www.ti.com 30104821 6 (VGATE - VIN) vs VIN, VVS = VOUT 30104811 30104812 Forward CGATE Charge Time, CGATE = 47 nF 26 26 Vin Vout Vgate 24 22 22 20 20 VOLTS (V) VOLTS (V) Reverse CGATE Discharge, CGATE = 47 nF Vin Vout Vgate 24 LM5050-1 (VGATE - VIN) vs VIN, VVS = VOUT 18 16 18 16 14 14 12 12 10 10 -5 0 5 10 15 20 TIME (5ms / DIV) 25 30 -50 0 50 100 150 TIME (50ns / DIV) 30104847 200 250 30104846 VGATE - VIN vs Temperature tGATE(REV) vs Temperature 30104829 30104830 7 www.ti.com LM5050-1 OFF Pin Thresholds vs Temperature OFF Pin Pull-Down vs Temperature 30104827 30104828 CGATE Charge and Discharge vs OFF Pin OFF Pin, On to Off Transition 30104815 30104816 OFF Pin, Off to On Transition GATE Pin vs (RDS(ON) x IDS) 30104817 30104818 www.ti.com 8 LM5050-1 Block Diagram 30104822 9 www.ti.com LM5050-1 IN, GATE AND OUT PINS When power is initially applied, the load current will flow from source to drain through the body diode of the MOSFET. The resulting voltage across the body diode will be detected at the LM5050-1 IN and OUT pins which then begins charging the MOSFET gate through a 32 µA (typical) charge pump current source . In normal operation, the gate of the MOSFET is charged until it reaches the clamping voltage of the 12V GATE to IN pin zener diode internal to the LM5050-1. The LM5050-1 is designed to regulate the MOSFET gate- to -source voltage if the voltage across the MOSFET source and drain pins falls below the VSD(REG) voltage of 22 mV (typical). If the MOSFET current decreases to the point that the voltage across the MOSFET falls below the VSD(REG) voltage regulation point of 27 mV (typical), the GATE pin voltage will be decreased until the voltage across the MOSFET is regulated at 22 mV. If the drain-to-source voltage is greater than VSD (REG) voltage the gate-to-source will increase, eventually reaching the 12V GATE to IN zener clamp level. If the MOSFET current reverses, possibly due to failure of the input supply, such that the voltage across the LM5050-1 IN and OUT pins is more negative than the VSD(REV) voltage of -28 mV (typical), the LM5050-1 will quickly discharge the MOSFET gate through a strong GATE to IN pin discharge transistor. If the input supply fails abruptly, as would occur if the supply was shorted directly to ground, a reverse current will temporarily flow through the MOSFET until the gate can be fully discharged. This reverse current is sourced from the load capacitance and from the parallel connected supplies. The LM5050-1 responds to a voltage reversal condition typically within 25 ns. The actual time required to turn off the MOSFET will depend on the charge held by gate capacitance of the MOSFET being used. A MOSFET with 47 nF of effective gate capacitance can be turned off in typically 180 ns. This fast turn off time minimizes voltage disturbances at the output, as well as the current transients from the redundant supplies. Applications Information FUNCTIONAL DESCRIPTION Systems that require high availability often use multiple, parallel-connected redundant power supplies to improve reliability. Schottky OR-ing diodes are typically used to connect these redundant power supplies to a common point at the load. The disadvantage of using OR-ing diodes is the forward voltage drop, which reduces the available voltage and the associated power losses as load currents increase. Using an Nchannel MOSFET to replace the OR-ing diode requires a small increase in the level of complexity, but reduces, or eliminates, the need for diode heat sinks or large thermal copper area in circuit board layouts for high power applications. 30104832 FIGURE 5. OR-ing with Diodes The LM5050-1 is a positive voltage (i.e. high-side) OR-ing controller that will drive an external N-channel MOSFET to replace an OR-ing diode. The voltage across the MOSFET source and drain pins is monitored by the LM5050-1 at the IN and OUT pins, while the GATE pin drives the MOSFET to control its operation based on the monitored source-drain voltage. The resulting behavior is that of an ideal rectifier with source and drain pins of the MOSFET acting as the anode and cathode pins of a diode respectively. VS PIN The LM5050-1 VS pin is the main supply pin for all internal biasing and an auxiliary supply for the internal gate drive charge pump. For typical LM5050-1 applications, where the input voltage is above 5.0V, the VS pin can be connected directly to the OUT pin. In situations where the input voltage is close to, but not less than, the 5.0V minimum, it may be helpful to connect the VS pin to the OUT pin through an RC Low-Pass filter to reduce the possibility of erratic behavior due to spurious voltage spikes that may appear on the OUT and IN pins. The series resistor value should be low enough to keep the VS voltage drop at a minimum. A typical series resistor value is 100Ω. The capacitor value should be the lowest value that produces acceptable filtering of the voltage noise. Alternately, it is possible to operate the LM5050-1 with VIN values less than 1V if the VS pin is powered from a separate supply. This separate VS supply must be between 5.0V and 75V. See Figure 9. 30104833 FIGURE 6. OR-ing with MOSFETs www.ti.com 10 LM5050-1 OFF PIN The OFF pin is a logic level input pin that is used to control the gate drive to the external MOSFET. The maximum operating voltage on this pin is 5.5V. When the OFF pin is high, the MOSFET is turned off (independent of the sensed IN and OUT voltages). In this mode, load current will flow through the body diode of the MOSFET. The voltage difference between the IN pin and OUT pins will be approximately 700 mV if the MOSFET is operating normally through the body diode. The OFF pin has an internal pull-down of 5 µA (typical). If the OFF function is not required the pin may be left open or connected to ground. 30104824 FIGURE 8. MOSFET Selection The important MOSFET electrical parameters are the maximum continuous Drain current ID, the maximum Source current (i.e. body diode) IS, the maximum drain-to-source voltage VDS(MAX), the gate-to-source threshold voltage VGS(TH), the drain-to-source reverse breakdown voltage V(BR)DSS, and the drain-to-source On resistance RDS(ON). The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The rating for the maximum current through the body diode, IS, is typically rated the same as, or slightly higher than the drain current, but body diode current only flows while the MOSFET gate is being charged to VGS(TH). Gate Charge Time = Qg / IGATE(ON) The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential voltage seen in the application. This would include any anticipated fault conditions. The drain-to-source reverse breakdown voltage, V(BR)DSS, may provide some transient protection to the OUT pin in low voltage applications by allowing conduction back to the IN pin during positive transients at the OUT pin. The gate-to-source threshold voltage, VGS(TH), should be compatible with the LM5050-1 gate drive capabilities. Logic level MOSFETs, with RDS(ON) rated at VGS(TH) at 5V, are recommended, but sub-Logic level MOSFETs having RDS(ON) rated at VGS(TH) at 2.5V, can also be used. Standard level MOSFETs, with RDS(ON) rated at VGS(TH) at 10V, are not recommended. The dominate MOSFET loss for the LM5050-1 active OR-ing controller is conduction loss due to source-to-drain current to the output load, and the RDS(ON) of the MOSFET. This conduction loss could be reduced by using a MOSFET with the lowest possible RDS(ON). However, contrary to popular belief, arbitrarily selecting a MOSFET based solely on having low RDS(ON) may not always give desirable results for several reasons: 1) Reverse transition detection. Higher RDS(ON) will provide increased voltage information to the LM5050-1 Reverse Comparator at a lower reverse current level. This will give an earlier MOSFET turn-off condition should the input voltage become shorted to ground. This will minimize any disturbance of the redundant bus. 2) Reverse current leakage. In cases where multiple input supplies are closely matched it may be possible for some small current to flow continuously through the MOSFET drain to source (i.e. reverse) without activating the LM5050-1 Reverse Comparator. Higher RDS(ON) will reduce this reverse current level. 3) Cost. Generally, as the RDS(ON) rating goes lower, the cost of the MOSFET goes higher. 30104823 FIGURE 7. SHORT CIRCUIT FAILURE OF AN INPUT SUPPLY An abrupt zero ohm short circuit across the input supply will cause the highest possible reverse current to flow while the internal LM5050-1 control circuitry discharges the gate of the MOSFET. During this time, the reverse current is limited only by the RDS(ON) of the MOSFET, along with parasitic wiring resistances and inductances. Worst case instantaneous reverse current would be limited to: ID(REV) = (VOUT - VIN) / RDS(ON) The internal Reverse Comparator will react, and will start the process of discharging the Gate, when the reverse current reaches: ID(REV) = VSD(REV) / RDS(ON) When the MOSFET is finally switched off, the energy stored in the parasitic wiring inductances will be transferred to the rest of the circuit. As a result, the LM5050-1 IN pin will see a negative voltage spike while the OUT pin will see a positive voltage spike. The IN pin can be protected by diode clamping the pin to GND in the negative direction. The OUT pin can be protected with a TVS protection diode, a local bypass capacitor, or both. In low voltage applications, the MOSFET draintosource breakdown voltage rating may be adequate to protect the OUT pin (i.e. VIN + V(BR)DSS(MAX) < 75V ), but most MOSFET datasheets do not guarantee the maximum breakdown rating, so this method should be used with caution. 11 www.ti.com LM5050-1 Selecting a MOSFET with an RDS(ON) that is too large will result in excessive power dissipation. Additionally, the MOSFET gate will be charged to the full value that the LM5050-1 can provide as it attempts to drive the Drain to Source voltage down to the VSD(REG) of 22 mV typical. This increased Gate charge will require some finite amount of additional discharge time when the MOSFET needs to be turned off. As a guideline, it is suggest that RDS(ON) be selected to provide at least 22 mV, and no more than 100 mV, at the nominal load current. reasonably well controlled, since the RDS(ON) of the MOSFET increases as the junction temperature increases. (22 mV / ID) ≤ RDS(ON) ≤ (100mV / ID) θJA ≤ (100°C - 35°C)/(10A x 10A x 0.01Ω) The thermal resistance of the MOSFET package should also be considered against the anticipated dissipation in the MOSFET in order to ensure that the junction temperature (TJ) is θJA ≤ 65°C/W PDISS = ID2 x (RDS(ON)) Operating with a maximum ambient temperature (TA(MAX)) of 35°C, a load current of 10A, and an RDS(ON) of 10 mΩ, and desiring to keep the junction temperature under 100°C, the maximum junction-to-ambient thermal resistance rating (θJA) would need to be: θJA ≤ (TJ(MAX) - TA(MAX))/(ID2 x RDS(ON)) Typical Applications 30104845 FIGURE 9. Using a Separate VS Supply For Low Vin Operation 30104842 FIGURE 10. Basic Application with Input Transient Protection www.ti.com 12 LM5050-1 30104843 FIGURE 11. Typical Application with Input and Output Transient Protection 30104844 FIGURE 12. +48V Application with Reverse Input Voltage (VIN = -48V) Protection 13 www.ti.com LM5050-1 Physical Dimensions inches (millimeters) unless otherwise noted 6-Lead TSOT Package NS Package Number MK06A www.ti.com 14 LM5050-1 Notes 15 www.ti.com LM5050-1 High Side OR-ing FET Controller Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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