MX29F400T/B
4M-BIT [512Kx8/256Kx16] CMOS FLASH MEMORY
FEATURES
• 524,288 x 8/262,144 x 16 switchable
• Single power supply operation
- 5.0V only operation for read, erase and program
operation
• Fast access time: 55/70/90/120ns
• Low power consumption
- 40mA maximum active current(5MHz)
- 1uA typical standby current
• Command register architecture
- Byte/word Programming (7us/12us typical)
- Sector Erase (Sector structure 16K-Bytex1, 8KBytex2, 32K-Bytex1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends an erase operation to read data from, or
program data to, another sector that is not being
erased, then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program and
erase cycle completion.
• Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase cycle completion.
- Sector protect/unprotect for 5V only system or 5V/
12V system.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 44-pin SOP
- 48-pin TSOP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
GENERAL DESCRIPTION
The MX29F400T/B is a 4-mega bit Flash memory organized as 512K bytes of 8 bits or 256K words of 16 bits.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memory. The MX29F400T/B is packaged in 44-pin SOP,
48-pin TSOP. It is designed to be reprogrammed and
erased in system or in standard EPROM programmers.
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maximum EPROM compatibility.
The standard MX29F400T/B offers access time as fast
as 55ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention,
the MX29F400T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cycling. The MX29F400T/B uses a 5.0V±10% VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F400T/B uses a command register to manage this
functionality. The command register allows for 100%
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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REV. 1.6 , NOV. 12, 2001
1
MX29F400T/B
PIN CONFIGURATIONS
PIN DESCRIPTION
NC
RY/BY
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
MX29F400T/B
44 SOP(500 mil)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
SYMBOL
PIN NAME
A0~A17
Address Input
Q0~Q14
Data Input/Output
Q15/A-1
Q15(Word mode)/LSB addr(Byte mode)
CE
Chip Enable Input
WE
Write Enable Input
BYTE
Word/Byte Selction input
RESET
Hardware Reset Pin/Sector Protect Unlock
OE
Output Enable Input
RY/BY
Ready/Busy Output
VCC
Power Supply Pin (+5V)
GND
Ground Pin
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MX29F400T/B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
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REV. 1.6, NOV. 12, 2001
2
MX29F400T/B
SECTOR STRUCTURE
MX29F400T TOP BOOT SECTOR ADDRESS TABLE
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
0
1
1
1
X
X
X
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
X
0
1
X
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
8/4
16/8
Address Range (in hexadecimal)
(x8)
(x16)
Address Range
Address Range
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-77FFFh
78000h-79FFFh
7A000h-7BFFFh
7C000h-7FFFFh
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3BFFFh
3C000h-3CFFFh
3D000h-3DFFFh
3E000h-3FFFFh
MX29F400B BOTTOM BOOT SECTOR ADDRESS TABLE
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
X
X
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
16/8
8/4
8/4
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Address Range (in hexadecimal)
(x8)
(x16)
Address Range
Address Range
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
00000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode.
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REV. 1.6, NOV. 12, 2001
3
MX29F400T/B
BLOCK DIAGRAM
CE
OE
WE
CONTROL
INPUT
HIGH VOLTAGE
LOGIC
LATCH
BUFFER
Y-DECODER
AND
X-DECODER
ADDRESS
A0-A17
PROGRAM/ERASE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
MX29F400T/B
FLASH
ARRAY
Y-PASS GATE
SENSE
AMPLIFIER
PGM
DATA
HV
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
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REV. 1.6, NOV. 12, 2001
4
MX29F400T/B
AUTOMATIC PROGRAMMING
AUTOMATIC ERASE ALGORITHM
The MX29F400T/B is byte programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29F400T/B is less than 4 seconds.
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the
status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 4 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
Register contents serve as inputs to an internal statemachine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever happens first .
AUTOMATIC SECTOR ERASE
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F400T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by using the EPROM programming mechanism of hot electron injection.
The MX29F400T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle.
The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are controlled internally within the device.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register to respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the program verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit toggling between consecutive read cycles, provide feedback to the user as to the status of the programming
operation.
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5
MX29F400T/B
TABLE1. SOFTWARE COMMAND DEFINITIONS
Command
Bus
First Bus
Cycle
Cycle Addr
Second Bus Third Bus
Cycle
Cycle
Data Addr Data Addr
Data
Fourth Bus
Cycle
Fifth Bus
Cycle
Addr Data
Addr
Reset
1
XXXH F0H
Read
1
RA
Read Silicon ID Word
4
555H AAH
2AAH 55H
555H 90H
ADI
DDI
Byte
4
AAAH AAH
555H 55H
AAAH 90H
ADI
DDI
Word
4
555H AAH
2AAH 55H
555H 90H
(SA)
XX00H
Sector Protect
Sixth Bus
Cycle
Data Addr
Data
RD
Verify
x02H XX01H
Byte
4
AAAH AAH
555H 55H
AAAH 90H
(SA)
00H
x04H 01H
Porgram
Word
4
555H AAH
2AAH 55H
555H A0H
PA
PD
Byte
4
AAAH AAH
555H 55H
AAAH A0H
PA
PD
Word
6
555H AAH
2AAH 55H
555H 80H
555H AAH
2AAH 55H
555H 10H
Byte
6
AAAH AAH
555H 55H
AAAH 80H
AAAH AAH
555H 55H
AAAH 10H
Word
6
555H AAH
2AAH 55H
555H 80H
555H AAH
2AAH 55H
SA
30H
Byte
6
AAAH AAH
555H 55H
AAAH 80H
AAAH AAH
555H 55H
SA
30H
Sector Erase Suspend
1
XXXH B0H
Sector Erase Resume
1
XXXH 30H
Unlock for sector
6
555H AAH
2AAH 55H
555H 80H
555H AAH
2AAH 55H
555H 20H
Chip Erase
Sector Erase
protect/unprotect
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code, A2~A17=do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, 23H/ABH (x8) and 2223H/22ABH (x16) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or
555H to Address A10~A-1 in byte mode.
Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A17 in either state.
4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it
means the sector is still not being protected.
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6
MX29F400T/B
COMMAND DEFINITIONS
Note that the Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Sector Erase
operation is in progress. Either of the two reset command sequences will reset the device(when applicable).
Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read mode.
Table 1 defines the valid register command sequences.
TABLE 2. MX29F400T/B BUS OPERATION
Pins
CE
OE
WE
A0
A1
A6
A9
L
L
H
L
L
X
VID(2)
Q0 ~ Q15
Mode
Read Silicon ID
Manfacturer Code(1)
Read Silicon ID
C2H (Byte mode)
00C2H (Word mode)
L
L
H
H
L
X
VID(2)
Device Code(1)
23H/ABH (Byte mode)
2223H/22ABH (Word mode)
Read
L
L
H
A0
A1
A6
A9
DOUT
Standby
H
X
X
X
X
X
X
HIGH Z
Output Disable
L
H
H
X
X
X
X
HIGH Z
Write
L
H
L
A0
A1
A6
A9
DIN(3)
Sector Protect with 12V
L
VID(2) L
X
X
L
VID(2)
X
L
VID(2) L
X
X
H
VID(2)
X
L
L
H
X
H
X
VID(2)
Code(5)
L
H
L
X
X
L
H
X
L
H
L
X
X
H
H
X
L
L
H
X
H
X
H
Code(5)
X
X
X
X
X
X
X
HIGH Z
system(6)
Chip Unprotect with 12V
system(6)
Verify Sector Protect
with 12V system
Sector Protect without 12V
system (6)
Chip Unprotect without 12V
system (6)
Verify Sector Protect/Unprotect
without 12V system (7)
Reset
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H/XX00H means unprotected.
Code=01H/XX01H means protected.
A17~A12=Sector address for sector protect.
6. Refer to sector protect/unprotect algorithm and waveform.
Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.
7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V system"
command.
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7
MX29F400T/B
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command register. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid command must then be written to place the device in the
desired state.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the
device resides in the target system. PROM programmers typically access signature codes by raising A9 to
a high voltage. However, multiplexing high voltage onto
address lines is not generally desired system design
practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).
The MX29F400T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read
silicon ID command sequence into the command register. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of 23H/2223H for MX29F400T, ABH/22ABH
for MX29F400B.
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE or CE, whichever happens later, pulse in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns
to the Read mode.
TABLE 3. EXPANDED SILICON ID CODE
Pins
Manufacture code
A0
A1
Q15~Q8 Q7
Q6
Q5
Q4
Q3
Q2 Q1
Q0
Code(Hex)
Word
VIL
VIL
00H
1
1
0
0
0
0
1
0
00C2H
Byte
VIL
VIL
X
1
1
0
0
0
0
1
0
C2H
Device code
Word
VIH
VIL
22H
0
0
1
0
0
0
1
1
2223H
for MX29F400T
Byte
VIH
VIL
X
0
0
1
0
0
0
1
1
23H
Device code
Word
VIH
VIL
22H
1
0
1
0
1
0
1
1
22ABH
for MX29F400B
Byte
VIH
VIL
X
1
0
1
0
1
0
1
1
ABH
Sector Protection
X
VIH
X
0
0
0
0
0
0
0
1
01H (Protected)
Verification
X
VIH
X
0
0
0
0
0
0
0
0
00H (Unprotected)
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8
MX29F400T/B
SECTOR ERASE COMMANDS
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the setup command 80H. Two more "unlock" write cycles are
then followed by the sector erase command 30H. The
sector address is latched on the falling edge of WEor
CE, whichever happens later, while the command(data)
is latched on the rising edge of WE or CE, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE or
CE, whichever happens later. Each successive sector
load cycle started by the falling edge of WE or CE, whichever happens later, must begin within 30us from the
rising edge of the preceding WE or CE, whichever happens First, otherwise, the loading period ends and internal auto sector erase cycle starts. (Monitor Q3 to determine if the sector erase timer window is still open, see
section Q3, Sector Erase Timer.) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.
The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing
the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
When using the Automatic Sector Erase algorithm, note
that the erase automatically terminates when adequate
Table 4. Write Operation Status
Status
Byte Program in Auto Program Algorithm
Auto Erase Algorithm
Erase Suspend Read
(Erase Suspended Sector)
Q7
Note1
Q6
Q5
Note2
Q3
Q2
RY/BY
Q7
Toggle
0
N/A
No
Toggle
0
0
Toggle
0
1
Toggle
0
1
No
Toggle
0
N/A Toggle
1
In Progress
Erase Suspended Mode
Erase Suspend Read
Data
(Non-Erase Suspended Sector)
Erase Suspend Program
Byte Program in Auto Program Algorithm
Exceeded
Time Limits
Auto Erase Algorithm
Erase Suspend Program
Data
Data Data Data
1
Q7
Toggle
0
N/A
N/A
0
Q7
Toggle
1
N/A
No
Toggle
0
0
Toggle
1
1
Toggle
0
Q7
Toggle
1
N/A
N/A
0
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
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9
MX29F400T/B
ERASE SUSPEND
tem is not required to provide further controls or timings.
The device will automatically provide an adequate internally generated program pulse and verify margin.
This command only has meaning while the state machine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 100us to suspend the erase
operations. However, When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been executed, the command register will initiate erase suspend
mode. The state machine will return to read mode automatically after suspend is ready. At this time, state machine only allows the command register to respond to
the Read Memory Array, Erase Resume and program
commands.
If the program opetation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data
on Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read mode(no
program verify command is required).
DATA POLLING-Q7
The MX29F400T/B also features Data Polling as a
method to indicate to the host system that the Automatic Program or Erase algorithms are either in progress
or completed.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend program operation is complete, the system can once again
read array data within non-suspended sectors.
While the Automatic Programming algorithm is in operation, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an attempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the fourth WEor CE, whichever happens
first, pulse of the four write pulse sequences for automatic program.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the sixth WE or CE, whichever happens first
pulse of six write pulse sequences for automatic chip/
sector erase.
SET-UP AUTOMATIC PROGRAM
COMMANDS
The Data Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer)
To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Program command A0H.
RY/BY:Ready/Busy
The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid
after the rising edge of the final WE or CE, whichever
happens first, pulse in the command sequence. Since
RY/BY is an open-drain output, several RY/BY pins can
be tied together in parallel with a pull-up resistor to Vcc.
Once the Automatic Program command is initiated, the
next WEor CE, pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the
rising edge of the WE or CE, whichever happens first,
pulse. The rising edge of WE or CE, whichever happens
first, also begins the programming operation. The sys-
P/N:PM0439
REV. 1.6, NOV. 12, 2001
10
MX29F400T/B
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.)If the output is high (Ready), the device
is ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid after the rising edge of the final WE or CE, whichever happens first, pulse in the command sequence.
Table 4 shows the outputs for RY/BY.
Q6:Toggle BIT I
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 4 to compare outputs for Q2 and Q6.
Toggle Bit I on Q6 indicates whether an Automatic Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE or CE, whichever
happens first, pulse in the command sequence(prior to
the program or erase operation), and during the sector
time-out.
During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause Q6
to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, Q6
stops toggling.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.
After an erase command sequence is written, if all sectors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfuly completed the program or erase operation. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7.
If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program command sequence is written, then returns to reading array
data.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algorithm is complete.
Table 4 shows the outputs for Toggle Bit I on Q6.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
11
MX29F400T/B
Q5
Exceeded Timing Limits
resulting from VCC power-up and power-down transition
or system noise.
Q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data Polling and Toggle Bit
are the only operating functions of the device under this
condition.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
protected sector to change data in-system. The Temporary Sector Unprotect mode is activated by setting the
RESET pin to VID(11.5V-12.5V). During this mode, formerly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin,all the previously protected sectors are protected again.
If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase command sequence.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or combination of sectors are bad.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.
If this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused).
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Automatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the
Q5 bit will indicate a "1". Please note that this is not a
device failure condition since the device was incorrectly
used.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.
DATA PROTECTION
LOGICAL INHIBIT
The MX29F400T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected between its VCC and GND.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
12
MX29F400T/B
Temporary Sector Unprotect Operation
Start
RESET = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET = VIH
Temporary Sector Unprotect Completed(Note 2)
Note : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
2. All previously protected sectors are protected again.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
13
MX29F400T/B
TEMPORARY SECTOR UNPROTECT
Parameter Std.
Description
Test Setup
AllSpeed Options Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET Setup Time for Temporary Sector Unprotect
Min
4
us
Note:
Not 100% tested
Temporary Sector Unprotect Timing Diagram
12V
RESET
0 or 5V
0 or 5V
Program or Erase Command Sequence
tVIDR
tVIDR
CE
WE
tRSP
RY/BY
P/N:PM0439
REV. 1.6, NOV. 12, 2001
14
MX29F400T/B
AC CHARACTERISTICS
Parameter Std
Description
Test Setup
tREADY1
RESET PIN Low (During Automatic Algorithms)
All Speed Options Unit
MAX
20
us
MAX
500
ns
to Read or Write (See Note)
tREADY2
RESET PIN Low (NOT During Automatic
Algorithms) to Read or Write (See Note)
tRP1
RESET Pulse Width (During Automatic Algorithms)
MIN
10
us
tRP2
RESET Pulse Width (NOT During Automatic Algorithms)
MIN
500
ns
tRH
RESET High Time Before Read(See Note)
MIN
0
ns
tRB1
RY/BY Recovery Time(to CE, OE go low)
MIN
0
ns
tRB2
RY/BY Recovery Time(to WE go low)
MIN
50
ns
Note:Not 100% tested
RESET TIMING WAVEFORM
RY/BY
CE, OE
tRH
RESET
tRP2
tReady2
Reset Timing NOT during Automatic Algorithms
tReady1
RY/BY
tRB1
CE, OE
WE
tRB2
RESET
tRP1
Reset Timing during Automatic Algorithms
P/N:PM0439
REV. 1.6, NOV. 12, 2001
15
MX29F400T/B
SECTOR PROTECTION WITH 12V SYSTEM
POWER-UP SEQUENCE
The MX29F400T/B features hardware sector protection.
This feature will disable both program and erase operations for these sectors protected. To activate this mode,
the programming equipment must force VID on address
pin A9 and control pin OE, (suggest VID = 12V) A6 =
VIL and CE = VIL.(see Table 2) Programming of the
protection circuitry begins on the falling edge of the WE
pulse and is terminated on the rising edge. Please refer
to sector protect algorithm and waveform.
The MX29F400T/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
SECTOR PROTECTION WITHOUT 12V
SYSTEM
The MX29F400T/B also feature a hardware sector
protection method in a system without 12V power suppply.
The programming equipment do not need to supply 12
volts to protect sectors. The details are shown in sector
protect algorithm and waveform.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
( with CE and OE at VIL and WE at VIH). When A1=1, it
will produce a logical "1" code at device output Q0 for a
protected sector. Otherwise the device will produce 00H
for the unprotected sector. In this mode, the
addresses,except for A1, are don't care. Address locations with A1 = VIL are reserved to read manufacturer
and device codes.(Read Silicon ID)
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F400T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and waveform.
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
ABSOLUTE MAXIMUM RATINGS
RATING
Ambient Operating Temperature
Ambient Temperature with Power
Applied
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9 & OE
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F400T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in the
code. It is recommended to protect all sectors before
activating chip unprotect mode.
To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and waveform
for the chip unprotect algorithm. The unprotection
mechanism begins on the falling edge of the WE pulse
and is terminated on the rising edge.
VALUE
-40oC to 125oC
-55oC to 125oC
-65oC to 125oC
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 13.5V
NOTICE:
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may
affect reliability.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
NOTICE:
Specifications contained within the following tables are subject to change.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
16
MX29F400T/B
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL
PARAMETER
CIN1
MIN.
TYP
MAX.
UNIT
CONDITIONS
Input Capacitance
8
pF
VIN = 0V
CIN2
Control Pin Capacitance
12
pF
VIN = 0V
COUT
Output Capacitance
12
pF
VOUT = 0V
READ OPERATION
DC CHARACTERISTICS TA = 0oC to 70oC, -40oC to 125oC, VCC = 5V ±10%
SYMBOL PARAMETER
MIN.
TYP
MAX.
UNIT
CONDITIONS
ILI
Input Leakage Current
1
uA
VIN = GND to VCC
ILO
Output Leakage Current
10
uA
VOUT = GND to VCC
ISB1
Standby VCC current
1
mA
CE = VIH
uA
CE = VCC ± 0.3V
40
mA
IOUT = 0mA, f=5MHz
50
mA
IOUT= 0mA, f=10MHz
ISB2
ICC1
1(Note3) 5(Note3)
Operating VCC current
ICC2
VIL
Input Low Voltage
-0.3(NOTE 1)
0.8
V
VIH
Input High Voltage(NOTE 2)
2.0
VCC + 0.3
V
VOL
Output Low Voltage
VOH1
Output High Voltage(TTL)
0.45
VOH2
Output High Voltage(CMOS) VCC-0.4
2.4
V
IOL = 2.1mA
V
IOH = -2mA
V
IOH = -100uA,VCC=VCC MIN
NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
3. ISB2 20uA max. for Automotive grade.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
17
MX29F400T/B
AC CHARACTERISTICS TA = 0oC to 70oC, -40oC to 125oC, VCC = 5V ± 10%
SYMBOL
tACC
tCE
tOE
tDF
tOH
PARAMETER
Address to Output Delay
CE to Output Delay
OE to Output Delay
OE High to Output Float (Note1)
Address to Output hold
29F400T/B-55 (Note2)
MIN.
MAX.
55
55
15
0
20
0
29F400T/B-70
MIN.
MAX.
70
70
40
0
30
0
UNIT
ns
ns
ns
ns
ns
Conditions
CE=OE=VIL
OE=VIL
CE=VIL
CE=VIL
CE=OE=VIL
UNIT
ns
ns
ns
ns
ns
Conditions
CE=OE=VIL
OE=VIL
CE=VIL
CE=VIL
CE=OE=VIL
29F400T/B-90 (Note3) 29F400T/B-12(Note3)
SYMBOL
tACC
tCE
tOE
tDF
tOH
PARAMETER
MIN.
Address to Output Delay
CE to Output Delay
OE to Output Delay
OE High to Output Float (Note1) 0
Address to Output hold
MAX.
90
90
40
30
0
MIN.
0
0
MAX.
120
120
50
30
NOTE:
TEST CONDITIONS:
1. tDF is defined as the time at which the output achieves
the open circuit condition and data is no longer driven.
2.VCC=5V±10%,CL=50pF,VIH/VIL=3.0V/0V,
VOH/VOL=1.5V/1.5V, IOL=2mA,IOH=-2mA.
3. Automotive grade is only provided for MX29F400T/B90 & MX29F400T/B-12
• Input pulse levels: 0.45V/2.4V
• Input rise and fall times is equal to or less than 10ns
• Output load: 1 TTL gate + 100pF (Including scope and
jig)
• Reference levels for measuring timing: 0.8V, 2.0V
P/N:PM0439
REV. 1.6, NOV. 12, 2001
18
MX29F400T/B
READ TIMING WAVEFORMS
VIH
ADD Valid
Addresses
VIL
tCE
VIH
CE
VIL
WE
VIH
OE
VIH
tACC
VIL
Outputs
tDF
tOE
VIL
VOH
tOH
HIGH Z
HIGH Z
DATA Valid
VOL
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICS TA = 0oC to 70oC, -40oC to 125oC, VCC = 5V ± 10%
SYMBOL
PARAMETER
MIN.
ICC1 (Read)
Operating VCC Current
ICC2
ICC3 (Program)
ICC4 (Erase)
ICCES
VCC Erase Suspend Current
TYP
2
MAX.
40
50
50
50
UNIT
mA
mA
mA
mA
mA
CONDITIONS
IOUT=0mA, f=5MHz
IOUT=0mA, F=10MHz
In Programming
In Erase
CE=VIH, Erase Suspended
NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less
than 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guranteed.
3. ICCES is specified with the device de-selected. If
the device is read during erase suspend mode, current draw is the sum of ICCES and ICC1 or ICC2.
4. All current are in RMS unless otherwise noted.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
19
MX29F400T/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10%
29F400T/B-55(Note2)
MAX.
29F400T/B-70
Symbol
PARAMETER
MIN.
MIN.
tOES
OE setup time
50
50
ns
tCWC
Command programming cycle
70
70
ns
tCEP
WE programming pulse width
45
45
ns
tCEPH1
WE programming pluse width High
20
20
ns
tCEPH2
WE programming pluse width High
20
20
ns
tAS
Address setup time
0
0
ns
tAH
Address hold time
45
45
ns
tDS
Data setup time
30
30
ns
tDH
Data hold time
0
0
ns
tCESC
CE setup time before command write 0
0
ns
tDF
Output disable time (Note 1)
tAETC
Total erase time in auto chip erase
4(TYP.)
32
tAETB
Total erase time in auto sector erase
1.3(TYP.)
10.4
tAVT
Total programming time in auto verify 7/12(TYP.) 210/360
tBAL
Sector address load time
tCH
20
MAX.
Unit
30
ns
4(TYP.)
32
s
1.3(TYP.)
10.4
s
7/12(TYP.) 210/360
us
100
100
us
CE Hold Time
0
0
ns
tCS
CE setup to WE going low
0
0
ns
tVLHT
Voltge Transition Time
4
4
us
tOESP
OE Setup Time to WE Active
4
4
us
tWPP1
Write pulse width for sector protect
10
10
us
tWPP2
Write pulse width for sector unprotect 12
12
ms
(byte/ word program time)
NOTES:
1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
2. Under condition of VCC=5V± 10%, CL=50pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
20
MX29F400T/B
AC CHARACTERISTICS TA = 0oC to 70oC, -40oC to 125oC, VCC = 5V ± 10%
29F400T/B-90
MAX.
29F400T/B-120
Symbol
PARAMETER
MIN.
MIN.
tOES
OE setup time
50
50
ns
tCWC
Command programming cycle
90
120
ns
tCEP
WE programming pulse width
45
45
ns
tCEPH1
WE programming pluse width High
20
20
ns
tCEPH2
WE programming pluse width High
20
20
ns
tAS
Address setup time
0
0
ns
tAH
Address hold time
45
50
ns
tDS
Data setup time
45
50
ns
tDH
Data hold time
0
0
ns
tCESC
CE setup time before command write
0
0
ns
tDF
Output disable time (Note 1)
tAETC
Total erase time in auto chip erase
4(TYP.)
32
tAETB
Total erase time in auto sector erase
1.3(TYP.)
tAVT
Total programming time in auto verify
7/12(TYP.)
30
MAX.
Unit
30
ns
4(TYP.)
32
s
10.4
1.3(TYP.)
10.4
s
210/360
7/12(TYP.) 210/360
us
(byte/ word program time)
tBAL
Sector address load time
100
100
us
tCH
CE Hold Time
0
0
ns
tCS
CE setup to WE going low
0
0
ns
tVLHT
Voltge Transition Time
4
4
us
tOESP
OE Setup Time to WE Active
4
4
us
tWPP1
Write pulse width for sector protect
10
10
us
tWPP2
Write pulse width for sector unprotect
12
12
ms
NOTES:
1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
2. Under condition of VCC=5V± 10%, CL=50pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
21
MX29F400T/B
SWITCHING TEST CIRCUITS
DEVICE UNDER
TEST
1.6K ohm
+5V
CL
1.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance,
CL=50pF for MX29F400T/B-55
SWITCHING TEST WAVEFORMS
2.4V
2.0V
2.0V
TEST POINTS
0.8V
0.8V
0.45V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall time are < 20ns.(5ns for MX29F400T/B-55)
Note:VIH/VIL=3.0V/0V, VOH/VOL=1.5V/1.5V, for MX29F400T/B-55.
COMMAND WRITE TIMING WAVEFORM
VCC
Addresses
5V
VIH
ADD Valid
VIL
tAH
tAS
WE
VIH
VIL
tOES
tCEPH1
tCEP
tCWC
CE
VIH
VIL
tCS
OE
tCH
VIH
VIL
tDS
tDH
VIH
Data
DIN
VIL
P/N:PM0439
REV. 1.6, NOV. 12, 2001
22
MX29F400T/B
AUTOMATIC PROGRAMMING TIMING
WAVEFORM
One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are executed automatically by internal control circuit. Programming
completion can be verified by DATA polling and toggle
bit checking after automatic verification starts. Device
outputs DATA during programming and DATA after programming on Q7.(Q6 is for toggle bit; see toggle bit,
DATA polling, timing waveform)
AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)
Vcc 5V
A11~A17
A0~A10
ADD Valid
2AAH
555H
tAS
WE
ADD Valid
555H
tCWC
tAH
tCEPH1
tCESC
tAVT
CE
tCEP
OE
tDS
Q0,Q1,Q2
tDH
Command In
tDF
Command In
Command In
DATA
Data In
DATA polling
Q4(Note 1)
Q7
Command In
Command #AAH
Command In
Command In
Command #55H
Command #A0H
DATA
Data In
DATA
tOE
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit
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REV. 1.6, NOV. 12, 2001
23
MX29F400T/B
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Toggle Bit Checking
Q6 not Toggled
NO
YES
Invalid
Command
NO
Verify Word Ok
YES
NO
.
Q5 = 1
Auto Program Completed
YES
Reset
Auto Program Exceed
Timing Limit
P/N:PM0439
REV. 1.6, NOV. 12, 2001
24
MX29F400T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after auto-
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle
bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)
Vcc 5V
A11~A17
A0~A10
2AAH
555H
555H
555H
tAS
WE
2AAH
555H
tCWC
tAH
tCEPH1
tAETC
CE
tCEP
OE
tDS tDH
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
Q7
DATA polling
Command In
Command In
Command In
Command In
Command In
Command In
Command #AAH
Command #55H
Command #80H
Command #AAH
Command #55H
Command #10H
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0439
REV. 1.6, NOV. 12, 2001
25
MX29F400T/B
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
NO
Toggle Bit Checking
Q6 not Toggled
YES
Invalid
Command
NO
DATA Polling
Q7 = 1
YES
NO
Auto Chip Erase Completed
Q5 = 1
YES
Reset
Auto Chip Erase Exceed
Timing Limit
P/N:PM0439
REV. 1.6, NOV. 12, 2001
26
MX29F400T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector data indicated by A12 to A17 are erased. External erase verify is not required because data are erased
automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit check-
ing after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)
AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)
Vcc 5V
Sector
Address0
A12~A17
A0~A10
555H
2AAH
555H
555H
Sector
Address1
Sector
Addressn
2AAH
tAS
tCWC
tAH
WE
tCEPH1
tBAL
tAETB
CE
tCEP
OE
tDS tDH
Q0,Q1,
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Q4(Note 1)
Q7
DATA polling
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H
(Q0~Q7)
Command
In
Command #30H
Command
In
Command #30H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0439
REV. 1.6, NOV. 12, 2001
27
MX29F400T/B
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART (WORD MODE)
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Toggle Bit Checking
Q6 Toggled ?
NO
Invalid Command
YES
Load Other Sector Addrss If Necessary
(Load Other Sector Address)
NO
Last Sector
to Erase
YES
Time-out Bit
Checking Q3=1 ?
NO
YES
Toggle Bit Checking
Q6 not Toggled
NO
YES
NO
Q5 = 1
DATA Polling
Q7 = 1
YES
Reset
Auto Sector Erase Completed
Auto Sector Erase Exceed
Timing Limit
P/N:PM0439
REV. 1.6, NOV. 12, 2001
28
MX29F400T/B
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
Programming End
NO
YES
Write Data 30H
Continue Erase
Another
Erase Suspend ?
NO
YES
P/N:PM0439
REV. 1.6, NOV. 12, 2001
29
MX29F400T/B
TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V
5V
A9
tVLHT
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 1
WE
tOESP
CE
Data
01H
F0H
tOE
A17-A12
Sector Address
P/N:PM0439
REV. 1.6, NOV. 12, 2001
30
MX29F400T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V
5V
A9
tVLHT
A6
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 2
WE
tOESP
CE
Data
00H
F0H
tOE
P/N:PM0439
REV. 1.6, NOV. 12, 2001
31
MX29F400T/B
SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Set Up Sector Addr
(A17,A16,A15,A14,A13,A12)
PLSCNT=1
OE=VID,A9=VID,CE=VIL
A6=VIL
Activate WE Pulse
Time Out 10us
Set WE=VIH, CE=OE=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
No
PLSCNT=32?
No
Data=01H?
Yes
Yes
Device Failed
Protect Another
Sector?
Yes
No
Remove VID from A9
Write Reset Command
Sector Protection
Complete
P/N:PM0439
REV. 1.6, NOV. 12, 2001
32
MX29F400T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Protect All Sectors
PLSCNT=1
Set OE=A9=VID
CE=VIL,A6=1
Activate WE Pulse
Time Out 12ms
Increment
PLSCNT
Set OE=CE=VIL
A9=VID,A1=1
Set Up First Sector Addr
Read Data from Device
No
Data=00H?
Increment
Sector Addr
No
PLSCNT=1000?
Yes
Yes
No
Device Failed
All sectors have
been verified?
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
33
MX29F400T/B
TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Data
Don't care
(Note 2)
01H
F0H
tOE
A18-A16
Sector Address
Note1: Must issue "unlock for sector protect/unprotect" command before sector protection
for a system without 12V provided.
Note2: Except F0H
P/N:PM0439
REV. 1.6, NOV. 12, 2001
34
MX29F400T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Data
Don't care
(Note 2)
00H
F0H
tOE
Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection
for a system without 12V provided.
Note2: Except F0H
P/N:PM0439
REV. 1.6, NOV. 12, 2001
35
MX29F400T/B
SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for sector protect/unprotect"
Command(Table1)
Set Up Sector Addr
(A17,A16,A15,A14,A13,A12)
OE=VIH,A9=VIH
CE=VIL,A6=VIL
Activate WE Pulse to start
Data don't care
Toggle bit checking
Q6 not Toggled
No
Yes
Increment PLSCNT
Set CE=OE=VIL
A9=VIH
Read from Sector
Addr=SA, A1=1
No
PLSCNT=32?
No
Data=01H?
Yes
Yes
Device Failed
Protect Another
Sector?
Yes
No
Write Reset Command
Sector Protection
Complete
P/N:PM0439
REV. 1.6, NOV. 12, 2001
36
MX29F400T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
Protect All Sectors
PLSCNT=1
Write "unlock for sector protect/unprotect"
Command (Table 1)
Set OE=A9=VIH
CE=VIL,A6=1
Activate WE Pulse to start
Data don't care
No
Toggle bit checking
Q6 not Toggled
Increment
PLSCNT
Yes
Set OE=CE=VIL
A9=VIH,A1=1
Set Up First Sector Addr
Read Data from Device
No
Data=00H?
Increment
Sector Addr
No
PLSCNT=1000?
Yes
Yes
No
All sectors have
been verified?
Device Failed
Yes
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
P/N:PM0439
REV. 1.6, NOV. 12, 2001
37
MX29F400T/B
ID CODE READ TIMING WAVEFORM
VCC
5V
VID
ADD
VIH
VIL
A9
ADD
VIH
A0
VIL
tACC
tACC
ADD
A1-A8
A10-A17
CE
VIH
VIL
VIH
VIL
WE
VIH
tCE
VIL
OE
VIH
tOE
VIL
tDF
tOH
tOH
VIH
DATA
Q0-Q15
DATA OUT
DATA OUT
VIL
23H/ABH (Byte)
C2H/00C2H
2223H/22ABH (Word)
P/N:PM0439
REV. 1.6, NOV. 12, 2001
38
MX29F400T/B
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
TYP.(2)
MAX.(3)
UNITS
1.3
10.4
sec
Chip Erase Time
4
32
sec
Byte Programming Time
7
210
us
Word Programming Time
12
360
us
Chip Programming Time
4
12
sec
PARAMETER
MIN.
Sector Erase Time
Erase/Program Cycles
Note:
100,000
Cycles
1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C,5V.
3.Maximum values measured at 25°C,4.5V.
LATCHUP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all pins except I/O pins
-1.0V
13.5V
Input Voltage with respect to GND on all I/O pins
-1.0V
Vcc + 1.0V
-100mA
+100mA
MIN.
UNIT
20
Years
Current
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
DATA RETENTION
PARAMETER
Data Retention Time
P/N:PM0439
REV. 1.6, NOV. 12, 2001
39
MX29F400T/B
ORDERING INFORMATION
PLASTIC PACKAGE (Top Boot Sector as an sample. For Bottom Boot Sector ones,MX29F400Txx will
change to MX29F400Bxx)
PART NO.
MX29F400TMC-55
MX29F400TMC-70
MX29F400TMC-90
MX29F400TMC-12
MX29F400TTC-55
Access Time
(ns)
55
70
90
120
55
Operating Current
MAX.(mA)
40
40
40
40
40
Standby Current
MAX.(uA)
5
5
5
5
5
Temperature
Range
o
0 C~70oC
0oC~70oC
0oC~70oC
0oC~70oC
0oC~70oC
MX29F400TTC-70
70
40
5
0oC~70oC
MX29F400TTC-90
90
40
5
0oC~70oC
MX29F400TTC-12
120
40
5
0oC~70oC
MX29F400TTA-90
90
40
20
-40oC~125oC
MX29F400TTA-12
120
40
20
-40oC~125oC
PACKAGE
44 Pin SOP
44 Pin SOP
44 Pin SOP
44 Pin SOP
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
Note:MX29F400T/B-55 is supplied by request
P/N:PM0439
REV. 1.6, NOV. 12, 2001
40
MX29F400T/B
PACKAGE INFORMATION
48-PIN PLASTIC TSOP
P/N:PM0439
REV. 1.6, NOV. 12, 2001
41
MX29F400T/B
44-PIN PLASTIC SOP
P/N:PM0439
REV. 1.6, NOV. 12, 2001
42
MX29F400T/B
REVISION HISTORY
Revision
Description
1.0
To remove "Advanced Information" datasheet marking and
P1
contain information on products in full production.
To correct the typing error on package dimension.
P41
In fact,the physical packages are never changed,just correct the
previously typing error.
To add the description for 100K endurance cycles
P1,P40
To modify timing of sector address loading period while
P9
operating multi-sector erase from 80uS to 30uS
To modify tBAL from 80uS to 100uS
P20,P21
1.Program/erase cycle times:10K cycles-->100K cycles
P1,34
2.To add data retention minimum 20 years
P1,34
3.To remove A9 from "timing waveform for sector protection for P34
system without 12V"
To remove A9 from "timing waveform for chip unprotection for P35
system without 12V"
Add erase suspend ready max. 100us in ERASE SUSPEND's P10
section at page10
To modify "Package Information"
P41~42
Add automotive grade
P16-20,40
1.1
1.2
1.3
1.4
1.5
1.6
Page
P/N:PM0439
Date
JUL/01/1999
SEP/01/1999
SEP/17/1999
DEC/20/1999
MAY/29/2000
JUN/12/2001
NOV/12/2001
REV. 1.6, NOV. 12, 2001
43
MX29F400T/B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
44