CPC5712 Voltage Monitor with Detectors INTEGRATED CIRCUITS DIVISION Features Description • CPC5712 Outputs: • Two Independent Programmable Level Detectors with Programmable Hysteresis • Fixed-Level Polarity Detector with Hysteresis • Differential Linear Output • Minimum External Components • Excellent Common-Mode Rejection Ratio (CMRR) > 55dB • Application circuits meet isolation requirements of worldwide telephony standards • Worldwide telephone network compatibility • Single Supply Operation, 3.0V to 5.5V • High differential input impedance • Very low common-mode input impedance • Fixed Gain • TTL Compatible CMOS Logic Level outputs • Small SOP 16-Pin package The CPC5712 is a special purpose Voltage Monitor with Detectors integrated circuit that is used in various high-voltage telephony applications such as VoIP gateways and IP-PBXs. The device monitors the TIP/RING potential through a high-impedance divider (resistor isolation) to derive two programmable signal level detects, polarity information, and a scaled representation of the phone line voltages. In use, the resistor divider and the high input impedance of the CPC5712 make the circuit practically undetectable on the line. The two voltage-level detects are programmed with external resistors, which gives the designer complete freedom with respect to line voltage detection levels. The level settings also have programmable hysteresis to prevent false triggering conditions. Detection of these levels allows the user to determine the condition of the line. Applications • VoIP Gateways, IP-PBX, xDSL • TIP/RING Monitoring • Line-In-Use Detection • Polarity Detection for Caller ID, Enhanced 911 • Battery Detection, PSTN Check • Non-telephony voltage level detection applications • Instrumentation • Industrial Controls This device can also be used in non-telephony applications such as instrumentation and industrial controls, especially when a low-level differential level needs to be detected in the presence of a large common-mode voltage. Ordering Information e3 Pb Part Description CPC5712U CPC5712UTR 16-Pin SOP (100/Tube) 16-Pin SOP (2000/Reel) CPC5712 With Support Components V+ 1 VCC RIN1 TIP OUT+ 5 7 IN+ + 8 IN- - RDIFF RING RIN2 CPC5712 G=5 OUT - 6 POLARITY 4 OUT+ DET1 3 DET2 2 VREF GND 16 15 14 VL1 9 VH1 10 R1 DS-CPC5712-R02 + Analog Output R2 VL2 11 R3 - Analog Output Polarity Output Voltage Level Detect 1 Voltage Level Detect 2 VH2 12 R4 13 R5 www.ixysic.com 1 CPC5712 INTEGRATED CIRCUITS DIVISION 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 3 4 4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Line Side Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Monitor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Detector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Detector Threshold Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 5 6 6 3. Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Differential Input Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Voltage Detector Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Calculate Resistor Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Verify Resistor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 High Voltage Detection Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 8 8 8 9 9 4. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 CPC5712U 16-Pin SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 CPC5712UTR Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 www.ixysic.com 10 10 10 10 10 11 11 R02 CPC5712 INTEGRATED CIRCUITS DIVISION 1. Specifications 1.1 Package Pinout 1.2 Pin Description Pin DET2 DET1 POLARITY OUT+ OUTIN+ IN- 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC Supply Voltage 2 3 4 5 6 7 8 Output, Detector 2 Output, Detector 1 Output, represents polarity of input signal Output, amplifier non-inverting Output, amplifier inverting Input, amplifier non-inverting Input, amplifier inverting VH2 9 VL2 10 VL1 11 VH1 12 VL2 13 VH2 14 15 16 Not Used Not Used GND GND Not Used Not Used VH1 VL1 VREF Description 1 DET2 DET1 POLARITY OUT+ OUTIN+ INVREF CPC5712 Pinout VCC Name Output, Reference used to set threshold levels Input, sets DET1 low voltage detection threshold Input, sets DET1 high voltage detection threshold Input, sets DET2 low voltage detection threshold Input, sets DET2 high voltage detection threshold Do not use, connect to ground Do not use, connect to ground Ground 1.3 Absolute Maximum Ratings Parameter VCC Storage temperature Power dissipation Min Max Unit -0.3 -40 - 6.0 +125 50 V °C mW Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. 1.4 ESD Rating ESD Rating (Human Body Model) 4000 V R02 www.ixysic.com 3 CPC5712 INTEGRATED CIRCUITS DIVISION 1.5 Recommended Operating Conditions Parameter Symbol Min Max Units VCC 3.0 5.5 V | ICM | - 12 A VCC Input Common Mode Current 1 VREF Loading 2 Resistive Capacitive OUT+ and OUT- Loading Capacitive Current Operating Temperature 1 2 RREF 20 1000 k CREF - 220 pF COUT COUT 300 pF IOUT -500 +500 A TA -40 +85 °C Input common-mode current per pin must not exceed limit. Resistive and Capacitive loads on the VREF output must remain within these limits. 1.6 Electrical Characteristics Unless otherwise specified, minimum and maximum values are guaranteed by production testing. Typical values are characteristic of the device at 25°C and are the result of engineering evaluations. They are Parameter DC Characteristics provided for informational purposes only and are not part of the manufacturing testing requirements. Unless otherwise noted, all electrical specifications are listed for TA=25°C and VCC = 3V to 5.5V. Conditions Symbol Min Typ Max Units VCC 3 - 5.5 V 1.1 1.5 1.42 1.72 1.9 2.4 mA RIN VOUT+ VOUT- 10 -5 -5 - 5 5 M mV mV - -20 - 20 mV IIO -45 - 45 nA Supply Voltage Supply Current VREF and all outputs open, Pins 14 and 15 = Gnd. VCC=3V VCC=5.5V ICC AC Characteristics Differential Input Resistance Output Offset Voltage Comparator Input Offset Voltage Input Offset Current Reference Voltage Common-Mode Rejection Ratio Differential Gain RDIFF = 806k, VIN=0V RDIFF = 806k, From VIN through to the comparators, Measured at VOUT+ and VOUTICM=0A VCC=3V, VCC=5.5V IREF=0A, IREF=-80A ICM < 12A, 0-120 Hz 0 < f < 20kHz VREF 1.4 1.5 1.6 V CMRR - 55 4.85 5.00 5.15 dB - Differential signal applied to IN+ and IN- VIN ±22 ±37 ±54 mV IOH=-5mA IOL=5mA VOH VOL VCC-0.6 - 0.4 V V Polarity Detection Characteristics Polarity Detection Threshold Voltage Digital Output Characteristics Output Voltage, High Output Voltage, Low 4 www.ixysic.com - R02 CPC5712 INTEGRATED CIRCUITS DIVISION 2. Functional Description 2.1 Overview Clare’s CPC5712 is a generalized building block IC for telephone systems that is connected, through a resistor network, to the TIP and RING leads. From the TIP and RING line voltage, the CPC5712 provides a buffered and amplified differential linear representation output voltage, a polarity detect signal, and two programmable level detect signals. From these detected levels, certain line conditions can be inferred such as Line-In-Use and battery presence. The CPC5712 provides TTL/CMOS compatible outputs for the polarity and programmable level detectors. The polarity detect and the two programmable level detects all incorporate hysteresis to provide noise immunity and eliminate rapid output state changes in the presence of large voice signals. Hysteresis settings for the two programmable level detects are independently programmable; however, the polarity hysteresis is internally fixed. The high and low thresholds of the two programmable level detectors are set with external resistors, the selection of which is described below. Positive polarity, POLARITY = HIGH, is indicated for an OUT+ level greater than the OUT- level while negative polarity is indicated for an OUT+ level less than OUT-. For a logic-high polarity detect output with a normal battery feed of TIP more positive than RING, the amplifier IN+ will need to be connected to the TIP lead via the high impedance input resistors. Detection and hysteresis thresholds for polarity are internal to the device. The CPC5712 is connected to the TIP/RING interface through a high-impedance resistor divider to attenuate the signal. The resistors in the divider network become a distributed resistive isolation barrier between the high-voltage line side and the low voltage side. The attenuator and the CPC5712 present a high impedance to TIP and RING, making the circuit almost undetectable when used as a monitoring device. 2.2 Line Side Interface IN+, IN-: Analog inputs. The differential signal across these inputs is amplified and brought out to the pins OUT+ and OUT-. A nominal reference voltage bias of 1.5V is applied to IN+ and IN- by circuitry internal to R02 the chip. Because the voltage across TIP and RING can be very large, TIP and RING cannot be directly connected to IN+ and IN-. A resistor divider network defined by RIN1, RIN2 and RDIFF attenuates the high voltage signal across TIP and RING (see ). The resulting low voltage differential signal across RDIFF is applied to the inputs IN+ and IN-. Resistors RIN1, RIN2 and RDIFF are external resistors that must be supplied by the user. Any component sizing and value recommendations given in the circuits described in this document will need to be reviewed with regard to the regulatory and safety requirements for each particular application. For example, the resistors selected for RIN1 and RIN2, shown in , are recommended to be a pair of 1206 surface mount size resistors in series to provide for high-voltage isolation. 2.3 Monitor Output OUT+, OUT-: Analog outputs. The differential signal across these outputs is the same as the differential input signal, except there has been a differential gain of 5 applied to it. A nominal reference voltage bias of 1.5V is applied to OUT+ and OUT- by circuitry internal to the chip. 2.4 Detector Outputs DET2, DET1, POLARITY: Digital outputs. These signals show whether threshold 2 has been crossed, threshold 1 has been crossed, and the polarity of the TIP to RING potential. When configured as shown in , POLARITY will be high after the TIP to RING potential (TIP more positive than RING) has increased to a nominal 2V. POLARITY will switch low after the TIP to RING voltage decreases to approximately -2V. For example, if the TIP to RING voltage starts at -48V, POLARITY will be low. As the TIP to RING voltage increases to +1V, POLARITY will remain low. As the TIP to RING voltage increases beyond it’s internally set positive threshold, the POLARITY output will switch high. POLARITY will remain high until the TIP to RING voltage decreases below it’s internally set negative threshold. Because these polarity thresholds are set internally they are not user adjustable. www.ixysic.com 5 CPC5712 INTEGRATED CIRCUITS DIVISION In the case of the detector 2 switching points, DET2 will be low after the |TIP/RING| voltage has decreased below a threshold set at VL2. DET2 will not transition high until after the |TIP/RING| voltage has increased above a threshold set at VH2. This |TIP/RING| voltage will be larger than the threshold set at VL2. As an example, the voltage at VL2 represents a |TIP/RING| threshold of 20V and VH2 represents a TIP/RING threshold of 22V. DET2 will be low if the |TIP/RING| voltage decreases below 20V, and it will remain low until the |TIP/RING| voltage increases above 22V. DET2 will change states for both positive and negative values of TIP/RING voltage as represented by |TIP/RING|. This means that DET2 will also be low if the TIP/RING voltage decreases below -20V and will remain low until the TIP/RING voltage increases beyond -22V. The user must rely on POLARITY to determine whether the TIP/RING threshold changed due to a positive or negative differential signal since DET2 does not contain any polarity information. VREF: An analog output that is similar to the DC bias level that is applied to OUT+ and OUT-. This voltage is brought off chip so that it can be used to define threshold detection levels. Load capacitance on this pin must be kept less than the value recommended in the table Recommended Operating Conditions. The total load resistance on this pin must be within the range specified in the table Recommended Operating Conditions. DET1 behaves similarly to DET2, except that it is triggered based on the voltage set at VL1 and VH1. This means that DET1 will be low after the |TIP/RING| voltage has decreased below the value set by the voltage at VL1 and will not change high until after the |TIP/RING| voltage has increased above the value set by the voltage at VH1. DET1 does not give any polarity information for the same reasons as defined for DET2. In the application circuit provided, the TIP/RING threshold levels of DET2 will always be higher than the threshold levels of DET1. Then use the following algorithm to find the values of R2, R3, R4 and R5. 2.5 Detector Threshold Operation VL1, VH1, VL2, and VH2: Inputs used to set the |TIP/RING| threshold levels that are to be detected. VH1 and VL1 are used to set the high and low threshold levels. The difference between VH1 and VL1 sets the Resistors R1, R2, R3, R4 and R5 are external resistors, which must be provided by the user. The selection of the resistors determines the voltages at VL2, VH2, VL1 and VH1 and therefore the threshold and hysteresis values for the 2 detectors. The values for R1, R2, R3, R4, and R5 are easily determined. Select voltage levels for the 1st and 2nd threshold and hysteresis settings such that: VH2 > VL2 > VH1 > VL1 1. Select a value for R1. 2. R2 = (R1(VH1-VL1)) / VL1 3. R3 = (R1(VL2-VH1))/ VL1 4. R4 = (R1(VH2-VL2)) / VL1 5. R5 = (R1(VREF/A-VH2)) / VL1 • VREF = 1.5V • A = (2.5 (RDIFF)) / (RIN1 + RIN2 + RDIFF), which typically calculates to 0.05; in this case: 0.04938. See Figure 1. Also, as shown in the table of Recommended Operating Conditions, the resistive load on the VREF pin must fall within the range: 20k < (R1 + R2 + R3 + R4 + R5) < 1M hysteresis for the 1st threshold level. VH2 and VL2 are used to set the threshold and hysteresis for the 2nd threshold level. There is a digital output for both the 1st and 2nd threshold levels that shows when the |TIP/RING| voltage has crossed a threshold level and when it has exceeded the configured hysteresis level. This was explained in the DET1 and DET2 definitions. In general, the digital output will be low when the |TIP/RING| voltage has fallen below the VL# level and will change high again once the |TIP/RING| voltage has risen above the VH# level. 6 2.6 Power Connections VCC, Ground: Power supply pins. These are used to supply voltage and ground to the chip. www.ixysic.com R02 CPC5712 INTEGRATED CIRCUITS DIVISION 3. Design Example An application circuit that is based on information discussed in Section 2.5 “Detector Threshold Operation” on page 6 is shown in Figure 1. LIU detector will monitor the Public Switched Telephone Network (PSTN) twisted pair TIP and RING leads for a voltage level that indicates a device on the line is off-hook while the LOOP detector monitors for the presence of battery feed. In this example detector 2 (DET2) will be the LIU detector as it has the greater voltage detect thresholds. In the following telephony design example, it is desired to have a Line-In-Use (LIU) detector set at 12V with a hysteresis of 3V, and a loop or battery-presence (LOOP) detector set at 5V with a hysteresis of 2V. The Figure 1 CPC5712 Application Circuit V+ 0.1µF 1 VCC CPC5712 OUT+ 5 TIP 806K 1% RING 7 IN+ 8 IN- + - G=5 OUT - 6 (4) 10M 1% 1206 POLARITY 4 OUT+ DET1 3 DET2 2 VREF GND 16 15 14 VL1 9 VH1 10 R1 26.7K 1% R02 + Analog Output R2 VL2 11 R3 VH2 12 R4 − Analog Output Polarity Output Voltage Level Detect 1 Voltage Level Detect 2 13 R5 17.8K 61.9K 26.7K 137K 1% 1% 1% 1% www.ixysic.com 7 CPC5712 INTEGRATED CIRCUITS DIVISION 3.1 Line Interface 3.3 Voltage Detector Design Between the CPC5712 and the TIP/RING line is a high impedance resistive divider network that provides sufficient impedance to meet the barrier insulation specifications in safety regulations and comply with the on-hook DC leakage to ground requirements from the various network compatibility specifications. From the application requirements given above, the desired LIU detector threshold voltages are therefore: • VH2 = 15V • VL2 = 12V and the detector thresholds for the LOOP detector are: To ensure regulatory compliance, a 20M or greater resistance is required from the individual TIP and RING leads to the IN+ and IN- inputs. For most applications where the tip and ring interface does not have a ground referenced surge protector, Clare recommends using two 1206-size 10M resistors in series to provide the minimum impedance and to meet surge requirements. Resistors having a smaller physical footprint may be used when ground referenced surge protection is available. • VH1 = 5V • VL1 = 3V 3.3.1 Calculate Resistor Values From the design equations provided in Section 2.5 “Detector Threshold Operation” on page 6 this gives: In practice, each 1206-size resistor is capable of withstanding the 2000V peak waveforms typical of lightning surges on the phone line. Hence, two 1206 resistors can withstand 4000V lightning pulses. • R1=R1 • R2=0.666667 R1 • R3=2.333333 R1 • R4=R1 • R5=5.125558 R1 Summing these equations provides the following result: 3.2 Differential Input Resistor R1+R2+R3+R4+R5 = 10.12556 R1 and since this sum is bound by: 20k < (R1 + R2 + R3 + R4 + R5) < 1M The differential input resistor placed across the IN+ and IN- inputs provides two functions. this reduces to: 20k < (10.12556 R1) < 1M From the application perspective, this component provides a scaled down representation of the tip and ring line voltage to the CPC5712 inputs. The voltage applied to the inputs is easily calculated because it is derived from a simple resistive divider comprising the tip and ring input resistors and the differential input resistor. For improved performance, the CPC5712 signal path is trimmed at the factory to reduce comparator detection errors caused by offset currents and voltages. The CPC5712’s input offset effects are reduced by trimming the device with an 806kinput resistor. Using any other value resistor at the inputs negates the trim and introduces offset errors. Taking into account the additional constraint of resistor tolerance, 1% in this example, the range of allowable values for R1 is further reduced and becomes: 1.995k < R1 < 97.782k permitting a value for R1 to be chosen. Selecting a standard value from the E96, 1% table for R1 of 26.7k the calculated values for the remaining resistors becomes: • • • • R2=17.8k R3=62.3k R4=26.7k R5=136.85k Since the calculated values of R3 and R5 are not standard values, a reasonable compromise for these resistors is: R3=61.9k, R5=137k. See Figure 1. 8 www.ixysic.com R02 CPC5712 INTEGRATED CIRCUITS DIVISION 3.3.2 Verify Resistor Selection Once the resistor values are chosen it is necessary to back calculate the nominal detector thresholds. To do this the following equations are provided for two variables: R = R IN1 + R IN2 + R DIFF where R is the sum of the resistive interface network and RREF is the sum of the resistor divider network on the reference voltage output. The following values are also needed to perform the threshold calculations. They are: VREF = 1.5V RIN1 = RIN2 = 2 x 10M = 20M RDIFF = 806k G=2.5 (Single ended gain of input amplifier) which gives: • R = 40.806M and • RREF = 270.1k The threshold equations are: VL1 = 3.00280V VH1 = 5.00467V VL2 = 11.9662V VH2 = 14.9690V 3.4 High Voltage Detection Designs Designs that require higher detection levels greater than approximately 17V will necessitate a different voltage divider ratio to accommodate the operational range of the CPC5712’s internal circuitry. Changes to the input resistor divider network are restricted to the high impedance resistors from the tip and ring leads to the IN+ and IN- inputs. Changing the differential input resistor value from 806k is not recommended as this will introduce offset errors. The degree of offset error caused by changing this component’s value is not measured and therefore not calculable. The design procedure for higher voltage detect levels is the same as presented above. Remember to begin with the equations shown in Section 2.5 “Detector Threshold Operation” on page 6 and use the updated value for the “A” term based on the new input resistor values. 1. V REF R R1 V L1 = ---------------------------------------G R DIFF R REF 2. V REF R R1 + R2 V H1 = ----------------------------------------------------G R DIFF R REF 3. V REF R R1 + R2 + R3 V L2 = -----------------------------------------------------------------G R DIFF R REF 4. V REF R R1 + R2 + R3 + R4 V H2 = -------------------------------------------------------------------------------G R DIFF R REF R02 • • • • As can be seen, the error from using standard value resistors is less than 0.1% for VL1 and VH1 and is less than 0.3% for VL2 and VH2. R REF = R1 + R2 + R3 + R4 + R5 • • • • Using the selected standard 1% resistor values, and back calculating to the threshold voltages produces these results: www.ixysic.com 9 CPC5712 INTEGRATED CIRCUITS DIVISION 4. Manufacturing Information 4.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Rating CPC5712U MSL 1 4.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 4.3 Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed. Device Maximum Temperature x Time CPC5712U 260°C for 30 seconds 4.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used. Pb 10 e3 www.ixysic.com R02 CPC5712 INTEGRATED CIRCUITS DIVISION 4.5 CPC5712U 16-Pin SOP Package 0.254 MAX - 0.178 MIN (0.010 MAX - 0.007 MIN) 4.902 ± 0.102 (0.193 ± 0.004) PCB Land Pattern 0.712 ± 0.051 (0.028 ± 0.002) 3.812 ± 0.076 (0.150 ± 0.003) 5.40 (0.213) 6.045 ± 0.153 (0.238 ± 0.006) 1.55 (0.061) Pin 1 0.635 (0.025) 0.254 ± 0.051 (0.010 ± 0.002) 0.762 MAX - 0.508 MIN (0.030 MAX - 0.020 MIN) 0.635 (0.025) 0.051 MIN, 0.305 MAX (0.002 MIN, 0.012 MAX) 1.447 ± 0.076 (0.057 ± 0.003) 0.40 (0.0157) Dimensions mm (inches) 1.829 MAX (0.072 MAX) 4.6 CPC5712UTR Tape and Reel Packaging 330.2 DIA. (13.00 DIA.) Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) W=12.00 (0.472) B0=5.30 (0.209) K0= 2.10 (0.083) A0=6.50 (0.256) P=8.00 (0.315) User Direction of Feed Embossed Carrier Embossment Dimensions mm (inches) NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 For additional information please visit www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC5712-R02 © Copyright 2012, IXYS Integrated Circuits Division All rights reserved. Printed in USA. 12/22/2012 R02 www.ixysic.com 11