SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation (’HC190, 191) D 4.5-V to 5.5-V VCC Operation (’HCT191) D Wide Operating Temperature Range of D D D D D D CD54HC190, 191; CD54HCT191 . . . F PACKAGE CD74HC190 . . . E, NS, OR PW PACKAGE CD74HC191, CD74HCT191 . . . E OR M PACKAGE (TOP VIEW) −55°C to 125°C Synchronous Counting and Asynchronous Loading Two Outputs for n-Bit Cascading Look-Ahead Carry for High-Speed Counting Balanced Propagation Delays and Transition Times Standard Outputs Drive Up To 15 LS-TTL Loads Significant Power Reduction Compared to LS-TTL Logic ICs B QB QA CTEN D/U QC QD GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC A CLK RCO MAX/MIN LOAD C D description/ordering information The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A−D) is accomplished by a low asynchronous parallel load (LOAD) input. Counting occurs when LOAD is high, count enable (CTEN) is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. ORDERING INFORMATION PDIP − E SOIC − M −55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA SOP − NS TSSOP − PW CDIP − F Tube of 25 TOP-SIDE MARKING CD74HC190E CD74HC190E CD74HC191E CD74HC191E CD74HCT191E CD74HCT191E Tube of 40 CD74HC191M Reel of 2500 CD74HC191M96 Reel of 250 CD74HC191MT Tube of 40 CD74HCT191M HCT191M Reel of 2000 CD74HC190NSR HC190M Tube of 90 CD74HC190PW Reel of 2000 CD74HC190PWR Reel of 250 CD74HC190PWT Tube of 25 HC191M HJ190 CD54HC190F3A CD54HC190F3A CD54HC191F3A CD54HC191F3A CD54HCT191F3A CD54HCT191F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ '*%$"# $')!" " 121343 !)) '!!&"&# !& "&#"&* %)&## ",&.#& "&*+ !)) ",& '*%$"# '*%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 description/ordering information (continued) When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO) output, which normally is high, goes low, and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO (see Figure 2). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3). FUNCTION TABLE INPUTS CLK FUNCTION LOAD CTEN D/U H L L Count up H L H Count down L X X X Asynchronous preset H H X X No change D/U or CTEN should be changed only when clock is high. X = Don’t care Low-to-high clock transition 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 ’HC190 logic diagram B A 15 CLK 1 14 b 5 c D/U LOAD 11 d e f g h i LOAD DATA LOAD DATA T T Q j Q CLKQ CLKQ FF0 FF1 k l m n o 4 p CTEN 3 2 QA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QB 3 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 ’HC190 logic diagram (continued) D C 9 10 13 b RCO c d e f g h i j 12 LOAD DATA LOAD DATA T T Q Q CLK Q CLK Q FF2 FF3 k l m n o p 6 4 7 QC POST OFFICE BOX 655303 QD • DALLAS, TEXAS 75265 MAX/MIN SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 ’HC191, ’HCT191 logic diagram A C B 15 10 1 14 b CLK D/U 5 c d 11 e f g LOAD LOAD DATA LOAD LOAD DATA DATA T T T Q Q h Q i CLK Q CLKQ CLKQ FF0 FF1 FF2 j k l M N 4 CTEN 3 2 Q B QA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 Q C 5 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 ’HC191, ’HCT191 logic diagram (continued) D 9 13 b RCO c d 12 e f g h i LOAD DATA T Q CLK Q FF3 j k l m n 7 6 QD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX/MIN SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 ’HC190 and ’HC191/HCT191 flip-flop DATA LOAD n p LOAD LOAD LOAD CL CL p p p n n p LOAD p n n CK Q CLK CLK Q n CLK T CLK CLK CLK POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 typical load, count, and inhibit sequence for ’HC190 The following sequence is illustrated below: 1. Load (preset) to BCD 7 2. Count up to 8, 9 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 9, 8, and 7 Parallel Load L P0 H P1 H P2 H Preset Input Data P3 Clock Down/Up L Clock Enable L H Q0 H L Q1 L Q2 L L Q3 H H H L Terminal Count Ripple Clock 7 8 9 0 1 Count Up 2 2 Inhibit Load 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 1 0 9 Count Down 8 7 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 typical load, count, and inhibit sequence for ’HC191 and ’HCT191 The following sequence is illustrated below: 1. Load (preset) to binary 13 2. Count up to 14, 15 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 15, 14, and 13 LOAD A Data Inputs B C D CLK D/U Data Outputs CTEN H QA L QB H QC L QD MAX/MIN H L RCO 13 14 15 0 1 Count Up 2 2 Inhibit 2 1 0 15 14 13 Count Down Load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 Direction Control Enable D/U D/U CE D/U CE CP TC CE CP TC CP TC Clock Figure 1. ’HC190 Synchronous n-Stage Counter With Parallel Gated Terminal Count Direction Control RC D/U Enable D/U RC D/U RC CE CE CE CP CP CP Clock Figure 2. ’HC191, ’HCT191 Synchronous n-Stage Counter With Parallel Gated Terminal Count 0 4 0 15 5 15 5 14 6 14 6 13 7 13 7 8 12 12 1 11 2 10 3 9 11 2 10 3 9 4 8 Count Down Count Up NOTE: Illegal states in BCD counters corrected in one count NOTE: Illegal states in BCD counters corrected in one or two counts Figure 3. ’HC190 State Diagram 10 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output drain current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous output source or sink current per output, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions for ’HC190 and ’HC191 (see Note 3) VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tt Low-level input voltage TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MAX MIN MAX MIN MAX 2 6 2 6 2 6 1.5 1.5 1.5 3.15 3.15 3.15 4.2 4.2 4.2 VCC = 4.5 V VCC = 6 V Input voltage 0 Output voltage Input transition (rise and fall) time TA = 25°C 0.5 0.5 0.5 1.35 1.35 1.8 1.8 1.8 0 0 VCC VCC 0 0 V V 1.35 VCC VCC 0 VCC = 2 V VCC = 4.5 V UNIT VCC VCC 1000 1000 1000 500 500 500 V V V ns VCC = 6 V 400 400 400 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. recommended operating conditions for ’HCT191 (see Note 4) VCC VIH Supply voltage VIL VI Low-level input voltage VO tt Output voltage High-level input voltage TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 2 Input voltage Input transition (rise and fall) time 2 2 UNIT V V 0.8 0.8 0.8 V VCC VCC VCC VCC VCC VCC V 500 500 500 ns V NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 ’HC190, ’HC191 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VCC TA = −40°C TO 85°C MIN MIN MIN MAX MAX UNIT MAX 2V 1.9 1.9 1.9 IOH = −20 µA 4.4 4.4 4.4 6V 5.9 5.9 5.9 IOH = −4 mA IOH = −5.2 mA 4.5 V 3.98 3.7 3.84 6V 5.48 5.2 5.34 2V 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.1 0.1 0.1 6V 0.1 0.1 0.1 4.5 V 0.26 0.4 0.33 6V 0.26 0.4 0.33 6V ±0.1 ±1 ±1 µA 6V 8 160 80 µA 10 10 10 pF VI = VIH or VIL VI = VIH or VIL VI = VCC or 0 VI = VCC or 0, TA = −55°C TO 125°C 4.5 V IOL = 4 mA IOL = 5.2 mA II ICC TA = 25°C IO = 0 Ci V V ’HCT191 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25°C VCC MIN VOH VI = VIH or VIL IOH = −20 µA IOH = −4 mA 4.5 V VOL VI = VIH or VIL IOL = 20 µA IOL = 4 mA 4.5 V II ICC VI = VCC to GND VI = VCC or 0, ∆ICC† IO = 0 One input at VCC − 2.1 V, Other inputs at 0 or VCC TYP MAX TA = −40°C TO 85°C MIN MIN MAX 4.4 4.4 4.4 3.98 3.7 3.84 UNIT MAX V 0.1 0.1 0.1 0.26 0.4 0.33 V 5.5 V ±0.1 ±1 ±1 µA 5.5 V 8 160 80 µA 360 490 450 µA 10 10 10 pF 4.5 V to 5.5 V 100 Ci † Additional quiescent supply current per input pin, TTL inputs high, 1 unit load HCT INPUT LOADING TABLE INPUTS UNIT LOADS A-D 0.4 CLK 1.5 LOAD 1.5 D/U 1.2 CTEN 1.5 Unit load is nICC limit specified in electrical characteristics table, (e.g., 360 µA max at 25°C). 12 TA = −55°C TO 125°C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 ’HC190, ’HC191 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) VCC fclock Clock frequency† LOAD low tw Pulse duration CLK high or low Data before LOAD↑ tsu Setup time CTEN before CLK↑ D/U before CLK↑ LOAD↑ Data before LOAD th Hold time CTEN before CLK CLK↑ CLK↑ D/U before CLK trec Recovery time LOAD inactive before CLK↑ TA = 25°C TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN MAX MAX UNIT MAX 2V 6 4 5 4.5 V 30 20 25 6V 35 23 29 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 26 21 2V 60 90 75 4.5 V 12 18 15 6V 10 15 13 2V 60 90 75 4.5 V 12 18 15 6V 10 15 13 2V 90 135 115 4.5 V 18 27 23 6V 15 23 20 2V 2 2 2 4.5 V 2 2 2 6V 2 2 2 2V 2 2 2 4.5 V 2 2 2 6V 2 2 2 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 2V 60 90 75 4.5 V 12 18 15 6V 10 15 13 MHz ns ns ns ns † Applies to noncascaded operation only. With cascaded counters, clock-to-terminal count propagation delays, CTEN-to-clock setup times, and CTEN-to-clock hold times determine maximum clock frequency. For example, with these HC devices: f max(CLK) + 1 1 + [ 18 MHz 42 ) 12 ) 2 CLK-to-MAXńMIN propagation delay ) CTEN-to-CLK setup time ) CTEN-to-CLK hold time POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 ’HC190, ’HC191 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE fmax LOAD A, B, C, or D Q Q CL = 50 pF Q RCO CLK MAX/MIN D/U RCO MAX/MIN tt 14 RCO Any MIN MAX 2V 6 4 5 4.5 V 30 20 25 6V 35 23 29 MHz 2V 195 295 245 4.5 V 39 59 49 33 50 42 2V 175 265 220 35 53 44 6V 30 45 37 2V 170 255 215 4.5 V 34 51 43 29 43 37 2V 125 190 155 4.5 V 25 38 31 6V 21 32 26 2V 210 315 265 4.5 V 42 63 53 36 54 45 2V 150 225 190 4.5 V 30 45 38 6V 26 38 33 CL = 50 pF 16 5V 14 6V CL = 50 pF CL = 50 pF 5V 14 5V 10 6V CL = 50 pF 5V 5V 2V 165 250 205 CL = 50 pF 4.5 V 33 50 41 6V 28 43 35 12 2V 125 190 155 4.5 V 25 38 31 6V 21 32 26 5V 13 CL = 15 pF 5V 2V 75 110 95 CL = 50 pF 4.5 V 15 22 19 6V 13 19 16 POST OFFICE BOX 655303 ns 18 CL = 15 pF CL = 50 pF UNIT MAX 4.5 V CL = 15 pF CTEN MIN CL = 50 pF CL = 15 pF D/U MAX TA = −40°C TO 85°C 5V CL = 15 pF tpd TYP 6V CL = 15 pF CLK MIN TA = −55°C TO 125°C CL = 15 pF CL = 15 pF CLK TA = 25°C VCC 10 • DALLAS, TEXAS 75265 ns SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 ’HCT191 timing requirements over recommended operating free-air temperature range VCC = 4.5 V (unless otherwise noted) (see Figure 5) fclock tw Hold time trec TA = −40°C TO 85°C MIN MIN MIN MAX 30 Setup time th TA = −55°C TO 125°C Clock frequency Pulse duration tsu TA = 25°C Recovery time MAX 20 25 LOAD low 16 24 20 CLK high or low 20 30 25 Data before LOAD↑ 12 18 15 CTEN before CLK↑ 12 18 15 D/U before CLK↑ 18 27 23 Data before LOAD↑ 2 2 2 CTEN before CLK↑ 2 2 2 D/U before CLK↑ 0 0 0 12 18 15 LOAD inactive before CLK↑ UNIT MAX MHz ns ns ns ns ’HCT191 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE fmax Q A, B, C, or D Q CLK RCO CLK Q CLK MAX/MIN tpd tt MIN 4.5 V LOAD D/U RCO D/U MAX/MIN CTEN RCO Any TA = 25°C VCC CL = 50 pF 4.5 V CL = 15 pF CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V 5V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V CL = 15 pF 5V CL = 50 pF 4.5 V POST OFFICE BOX 655303 TYP MAX 30 TA = −55°C TO 125°C TA = −40°C TO 85°C MIN MIN MAX 20 UNIT MAX 25 MHz 40 60 50 38 57 48 35 53 44 27 41 34 42 63 53 30 45 38 38 57 48 27 41 34 15 22 19 17 16 14 11 ns 18 12 16 11 • DALLAS, TEXAS 75265 ns 15 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 16 TYP Power dissipation capacitance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ’HC190 59 ’HC191 55 ’HCT191 68 UNIT pF SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION − ’HC190, ’HC191 VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt tw LOAD CIRCUIT VCC Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION LOAD Input VCC Reference Input VCC 50% VCC 50% VCC 0V 0V tsu trec Data 50% Input 10% VCC 50% VCC CLK 90% VOLTAGE WAVEFORMS RECOVERY TIME 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-of-Phase Output 90% tf tf VCC VOH 50% VCC 10% VOL tf 50% 10% 90% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC Output Waveform 1 (see Note B) 50% VCC Output Waveform 2 (see Note B) 10% VOL tPHZ tPZH VOH VOL VCC Output Control tPLH 50% VCC 10% VCC 50% VCC 10% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 0V In-Phase Output 90% tr 0V Input th 50% VCC 90% VOH ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION − ’HCT191 VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt tw LOAD CIRCUIT VCC Input 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS PULSE DURATION LOAD Input VCC Reference Input VCC 50% VCC 50% VCC 0V 0V tsu trec Data 50% Input 10% VCC 50% VCC CLK 90% VOLTAGE WAVEFORMS RECOVERY TIME 50% VCC 50% VCC tPLH tPHL 50% 10% 90% 90% tr tPHL Out-of-Phase Output 90% tf tf VCC VOH 50% VCC 10% VOL tf 50% 10% 90% tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% VCC 50% VCC 0V tPLZ tPZL ≈VCC Output Waveform 1 (see Note B) 50% VCC Output Waveform 2 (see Note B) 10% VOL tPHZ tPZH VOH VOL VCC Output Control tPLH 50% VCC 10% VCC 50% VCC 10% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 0V In-Phase Output 90% tr 0V Input th 50% VCC 90% VOH ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8867101EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type 5962-8994601EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC190F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC191F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HCT191F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC190E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC190EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC190NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC190NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC190PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC190PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC190PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC190PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC190PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC190PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC191E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC191EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC191M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC191M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC191M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC191ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC191MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC191MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT191E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT191EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT191M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT191ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Mailing Address: Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated