ON MC100EPT622 3.3v lvttl/lvcmos to lvpecl translator Datasheet

MC100EPT622
3.3VLVTTL/LVCMOS to
LVPECL Translator
The MC100EPT622 is a 10−Bit LVTTL/LVCMOS to LVPECL
translator. Because LVPECL (Positive ECL) levels are used only +3.3 V
and ground are required. The device has an OR−ed enable input which
can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs
(ENTTL). If the inputs are left open, they will default to the enable state.
The device design has been optimized for low channel−to−channel skew
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MARKING
DIAGRAM*
Features
•
•
•
•
•
•
•
•
450 ps Typical Propagation Delay
Maximum Frequency > 1.5 GHz Typical
MC100
EPT622
AWLYYWW
LQFP−32
FA SUFFIX
CASE 873A
PECL Mode
Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
32
PNP LVTTL Inputs for Minimal Loading
1
Q Output Will Default HIGH with Inputs Open
A
WL
YY
WW
The 100 Series Contains Temperature Compensation.
Pb−Free Packages are Available*
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
Table 1. TRUTH TABLE
ENPECL
ENTTL
D
Q
H
X
H
H
H
X
L
L
X
H
H
H
X
H
L
L
L
L
X
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 4
1
Publication Order Number:
MC100EPT622/D
MC100EPT622
24
23
22
21
20
19
VCCO
Q4
Q3
VCCO
Q2
Q1
Q0
VCCO
ENPECL
18
ENTTL
D0
17
D1
VCCO
25
16
VCCO
D0
26
15
Q5
D1
27
14
Q6
VEE
28
13
VCC
D2
29
12
Q7
D3
30
11
Q8
D4
31
10
Q9
VCCO
32
9
MC100EPT622
1
2
3
4
5
6
7
VCCO
D2
D3
LVCMOS/TTL
D4
D5
8
Q1
Q2
Q3
Q4 LVPECL
Q5
Q6
VEE
ENPECL
ENTTL
D9
D8
D7
D6
D5
D6
Q0
D7
Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
D8
Q7
Q8
Figure 1. 32−Lead LQFP Pinout (Top View)
D9
Q9
Figure 2. Logic Symbol
Table 1. PIN DESCRIPTION
Pin
Function
D0:9
Data Input (TTL)
Q0:9
Data Outputs (PECL)
ENTTL
Enable Control (TTL)
ENPECL
Enable Control (PECL)
VCC, VCCO
Positive Supply
VEE
Ground
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2
MC100EPT622
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
N/A
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack
Flammability Rating
Level 2
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
596 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
5
V
5 to 0
V
50
100
mA
mA
−40 to +85
°C
VCC
Power Supply
VEE = 0 V
VI
Input Voltage
VEE = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
32 LQFP
32 LQFP
80
55
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
32 LQFP
12 to 17
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VI VCC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. TTL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = −40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
25
mA
IIH
Input HIGH Current
VIN= 2.7 V
IIHH
Input HIGH Current MAX
VIN= VCC
100
mA
IIL
Input LOW Current
VIN= 0.5 V
−0.6
mA
VIK
Input Clamp Voltage
IIN= −18 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
−1.2
−0.9
V
2.0
V
0.8
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC100EPT622
Table 5. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND= 0.0 V, TA = −40°C to 85°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
IIH
Input HIGH Current
VIN= 2420 mV
150
mA
IIL
Input LOW Current
VIN= 1490 mV
200
mA
VIH
Input HIGH Voltage
2075
2420
mV
VIL
Input LOW Voltage
1490
1675
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. PECL OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 1)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
85
115
145
90
120
155
95
130
155
mA
IEE
Power Supply Current
VOH
Input High Voltage
(Note 2)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Input Low Current
(Note 2)
1355
1520
1700
1355
1520
1700
1355
1520
1700
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC.
2. All loading with 50 W to VCC−2.0 V.
Table 7. AC CHARACTERISTICS VCC = 3.0 V to 3.8 V (Note 3)
−40°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 3)
tPLH,
tPHL
Propagation Delay to Output (Figure 4, Note 4)
D to Q
ENPECL to Q
ENTTL to Q
tJITTER
Random Clock Jitter (RMS)
(See Figure 3)
tr / tf
Output Rise/Fall Times
(20% − 80%)
TSKEW
Duty Cycle Skew (Note 5)
D to Q
ENPECL to Q
ENTTL to Q
25°C
Min
Typ
1.0
1.5
100
150
300
450
500
450
800
875
800
0.7
3.0
200
450
120
200
120
100
375
775
400
275
100
Channel 0−7
Channel 8−9
Max
85°C
Min
Typ
1.0
1.5
100
150
300
500
500
500
875
875
800
0.7
3.0
200
250
120
200
120
100
375
775
400
275
100
Max
Min
Typ
1.0
1.5
100
200
300
500
550
500
800
925
800
0.7
3.0
ps
200
300
ps
120
200
120
100
375
775
400
275
100
Max
Unit
GHz
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 W to VCC−2.0 V.
4. 1.5 V to 50% point of the output.
5. Duty cycle skew |tPLH − tPHL| on the specific path.
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4
MC100EPT622
2400
10.0
9.0
8.0
VCC = 3.3 V
TA = 25°C
2000
VOH (mV)
7.0
1800
6.0
VOL (mV)
5.0
1600
4.0
1400
3.0
RMS Jitter (ps)
1200
RMS JITTER (ps)
OUTPUT AMPLITUDE (mV)
2200
2.0
1.0
1000
0.5
1.0
1.5
2.0
0.0
FREQUENCY (GHz)
Figure 3. Average Output Amplitude/Jitter (3.3 V, 255C)
800
700
tPLH, tPHL (ps)
600
500
400
300
200
100
0
tPLH
ÉÉ
ÉÉ
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
É
É
ÉÉ
ÉÉ
ÉÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÉÉ
ÉÉÉ
ÉÉÉ
ÉÉ
ÉÉÉ
ÉÉ
tPHL
CHANNEL
Figure 4. Average Propagation Delay (3.3 V, 255C)
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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5
MC100EPT622
ORDERING INFORMATION
Package
Shipping †
MC100EPT622FA
LQFP−32
250 Units / Tray
MC100EPT622FAG
LQFP−32
(Pb−Free)
250 Units / Tray
MC100EPT622FAR2
LQFP−32
2000 / Tape & Reel
MC100EPT622FAR2G
LQFP−32
(Pb−Free)
2000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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6
MC100EPT622
PACKAGE DIMENSIONS
32
A1
A
−T−, −U−, −Z−
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
25
0.20 (0.008) AB T−U Z
1
AE
−U−
−T−
B
P
V
17
8
BASE
METAL
DETAIL Y
V1
AC T−U Z
AE
DETAIL Y
ÉÉ
ÉÉ
ÉÉ
9
−Z−
4X
S1
0.20 (0.008) AC T−U Z
F
S
8X M_
G
D
DETAIL AD
−AB−
SECTION AE−AE
C E
−AC−
H
W
K
X
DETAIL AD
Q_
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
J
R
M
N
9
0.20 (0.008)
B1
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC100EPT622/D
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