LP38855 www.ti.com SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 1.5A Fast-Response High-Accuracy LDO Linear Regulator with Enable Check for Samples: LP38855 FEATURES DESCRIPTION • • The LP38855 is a high-current, fast-response regulator which can maintain output voltage regulation with an extremely low input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides power for the internal bias and control circuits, as well as drive for the gate of the N-MOS power transistor, while VIN supplies power to the load. The use of an external bias rail allows the part to operate from ultra low VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 2 • • • • • • • Standard VOUT Values of 0.8V and 1.2V Wide VBIAS Supply Operating Range of 3.0V to 5.5V Stable with 10 µF Ceramic Capacitors Dropout Voltage of 130 mV (Typical) at 1.5A Load Current Precision Output Voltage Across All Line and Load Conditions: – ±1.0% for TJ = 25°C – ±2.0% for 0°C ≤ TJ ≤ +125°C – ±3.0% for -40°C ≤ TJ ≤ +125°C Over-Temperature and Over-Current Protection Available in 5 Lead TO-220 and DDPAK/TO-263 Packages Custom VOUT Values between 0.8V and 1.2V are Available -40°C to +125°C Operating Temperature Range The fast transient response of this device makes it suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The LP38855 is available in TO-220 and DDPAK/TO-263 5-Lead packages. Dropout Voltage: 130 mV (typical) at 1.5A load current. APPLICATIONS • • • • Low Ground Pin Current: 10 mA (typical) at 1.5A load current. ASIC Power Supplies In: – Desktops, Notebooks, and Graphics Cards, Servers – Gaming Set Top Boxes, Printers and Copiers Server Core and I/O Supplies DSP and FPGA Power Supplies SMPS Post-Regulator Shutdown Current: 1 µA (typical) IIN(GND) when EN pin is low. Precision Output Voltage: ±1.0% for TJ = 25°C and ±2.0% for 0°C ≤ TJ ≤ +125°C, across all line and load conditions Typical Application Circuit LP38855-x.x VIN VBIAS IN VOUT OUT CIN 10 PF Ceramic VEN BIAS CBIAS 1 PF COUT 10 PF Ceramic EN GND GND GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LP38855 SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com Connection Diagrams Top View TAB IS GND EN 1 OUT 4 EN 1 LP38855T-x.x GND 3 LP38855S-x.x IN 2 Top View IN 2 GND 3 OUT 4 BIAS 5 TAB IS GND BIAS 5 Figure 1. DDPAK/TO-263 Package See Package Number KTT0005B Figure 2. TO-220 Package See Package Number NDH0005D PIN DESCRIPTIONS TO-220–5 and DDPAK/TO-263–5 Packages Pin # Pin Symbol Pin Description 1 EN The device Enable pin. 2 IN The unregulated input voltage pin 3 GND Ground 4 OUT The regulated output voltage pin 5 BIAS The supply for the internal control and reference circuitry TAB TAB The TAB is a thermal connection that is physically attached to the backside of the die, and is used as a thermal heat-sink connection. See the Application Information section for details These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −65°C to +150°C Storage Temperature Range Lead Temperature Soldering, 5 seconds ESD Rating Human Body Model (3) Power Dissipation (4) 260°C ±2 kV Internally Limited VIN Supply Voltage (Survival) −0.3V to +6.0V VBIAS Supply Voltage (Survival) −0.3V to +6.0V VEN Voltage (Survival) −0.3V to +6.0V VOUT Voltage (Survival) −0.3V to +6.0V IOUT Current (Survival) Internally Limited Junction Temperature −40°C to +150°C (1) (2) (3) (4) 2 Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22A114. The HBM rating for device pin 1 (EN) is ±1.5 kV. Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 LP38855 www.ti.com SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 Operating Ratings (1) VIN Supply Voltage (VOUT + VDO) to VBIAS VBIAS Supply Voltage 3.0V to 5.5V VEN Enable Input Voltage 0.0V to VBIAS IOUT 0 mA to 1.5A Junction Temperature Range (1) (2) −40°C to +125°C Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. (2) Electrical Characteristics Unless otherwise specified: VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1µF, VEN = VBIAS. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions VOUT(NOM) + 1V ≤ VIN ≤ VBIAS, 3.0V ≤ VBIAS ≤ 5.5V, 10 mA ≤ IOUT ≤ 1.5A VOUT ΔVOUT/ΔVIN Output Voltage Tolerance Line Regulation, VIN (1) (1) ΔVOUT/ΔVBIAS Line Regulation, VBIAS ΔVOUT/ΔIOUT Output Voltage Load Regulation (2) IGND(IN) IGND(BIAS) -1.0 -3.0 0 +1.0 +3.0 Units % -2.0 0 +2.0 VOUT(NOM) + 1V ≤ VIN ≤ VBIAS - 0.04 - %/V 3.0V ≤ VBIAS ≤ 5.5V - 0.10 - %/V 10 mA ≤ IOUT ≤ 1.5A - 0.2 - %/A mV IOUT = 1.5A - 130 LP38855-0.8 10 mA ≤ IOUT ≤ 1.5A - 7.0 8.5 9.0 Ground Pin Current Drawn from VIN LP38855-1.2 Supply 10 mA ≤ IOUT ≤ 1.5A - 11 12 15 VEN ≤ 0.5V - 1.0 10 300 µA 10 mA ≤ IOUT ≤ 1.5A - 3.0 3.8 4.5 mA VEN ≤ 0.5V - 100 170 200 µA 2.20 2.00 2.45 2.70 2.90 V 60 50 150 300 350 mV - 4.5 - A (3) Ground Pin Current Drawn from VBIAS Supply Under-Voltage Lock-Out Threshold VBIAS rising until device is functional UVLO(HYS) Under-Voltage Lock-Out Hysteresis VBIAS falling from UVLO threshold until device is non-functional ISC Output Short-Circuit Current VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VOUT = 0.0V (3) Max VOUT(NOM) + 1V ≤ VIN ≤ VBIAS, 3.0V ≤ VBIAS ≤ 5.5V, 10 mA ≤ IOUT ≤ 1.5A, 0°C ≤ TJ ≤ 125°C UVLO (1) (2) Typ 165 180 Dropout Voltage, VIN − VOUT VDO Min mA Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Dropout voltage is defined the as input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop 2% from the nominal value. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 3 LP38855 SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise specified: VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1µF, VEN = VBIAS. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions Min Typ - Max Units ENABLE Pin VEN = VBIAS 0.01 - VEN = 0.0V, VBIAS = 5.5V -19 -13 -30 -40 -51 Enable Voltage Threshold VEN rising until Output = ON 1.00 0.90 1.25 1.50 1.55 V VEN(HYS) Enable Voltage Hysteresis VEN falling from VEN(ON) until Output = OFF 50 30 100 150 200 mV tOFF Turn-OFF Delay Time RLOAD × COUT << tOFF - 20 - tON Turn-ON Delay Time RLOAD × COUT << tON - 15 - PSRR (VIN) Ripple Rejection for VIN Input Voltage VIN = VOUT +1V, f = 120 Hz - 80 - VIN = VOUT + 1V, f = 1 kHz - 65 - PSRR (VBIAS) Ripple Rejection for VBIAS Voltage VBIAS = VOUT + 3V, f = 120 Hz - 58 - VBIAS = VOUT + 3V, f = 1 kHz - 58 - f = 120 Hz - 1 - BW = 10 Hz − 100 kHz - 150 - BW = 300 Hz − 300 kHz - 90 - IEN ENABLE pin Current VEN(ON) µA µs AC Parameters Output Noise Density en Output Noise Voltage dB dB µV/√Hz µVRMS Thermal Parameters TSD Thermal Shutdown Junction Temperature - 160 - TSD(HYS) Thermal Shutdown Hysteresis - 10 - θJA Thermal Resistance, Junction to Ambient (4) TO-220-5 - 60 - DDPAK/TO-263-5 - 60 - θJC Thermal Resistance, Junction to Case (4) TO-220-5 - 3 - DDPAK/TO-263-5 - 3 - (4) 4 °C °C/W Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 LP38855 www.ti.com SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, VEN = VBIAS. VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature Figure 3. Figure 4. VIN Ground Pin Current (IGND(IN)) vs Temperature Load Regulation vs Temperature Figure 5. Figure 6. Dropout Voltage (VDO) vs Temperature Output Current Limit (ISC) vs Temperature Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 5 LP38855 SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, VEN = VBIAS. 6 VOUT vs Temperature UVLO Thresholds vs Temperature Figure 9. Figure 10. Enable Thresholds (VEN) vs Temperature Enable Pull-Down Current (IEN) vs Temperature Figure 11. Figure 12. Enable Pull-Up Resistor (rEN) vs Temperature VIN Line Transient Response Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 LP38855 www.ti.com SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, VEN = VBIAS. VIN Line Transient Response VBIAS Line Transient Response Figure 15. Figure 16. VBIAS Line Transient Response Load Transient Response, COUT = 10 μF Ceramic Figure 17. Figure 18. Load Transient Respose, COUT = 10 μF Ceramic Load Transient Response, COUT = 100 μF Ceramic Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 7 LP38855 SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, VEN = VBIAS. 8 Load Transient Response, COUT = 100 μF Ceramic Load Transient Response, COUT = 100 μF Tantalum Figure 21. Figure 22. Load Transient Response, COUT = 100 μF Tantalum VBIAS PSRR Figure 23. Figure 24. VIN PSRR Output Noise Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 LP38855 www.ti.com SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 Block Diagram OUT IN LP38855-x.x BIAS Under-Voltage Lock-Out Thermal Shut Down rEN EN Enable 1.2V VREF ILIMIT GND 0.6V APPLICATION INFORMATION EXTERNAL CAPACITORS To assure regulator stability, capacitors are required on the input, output and bias pins as shown in the Typical Application Circuit. Output Capacitor A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the IC and returned to the device ground pin with a clean analog ground. Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide sufficient capacitance over temperature. Tantalum capacitors will also provide stable operation across the entire operating temperature range. However, the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, Tantalum and/or Aluminum, to be added in parallel. Input Capacitor The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended. Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at cold temperatures. They are not recommended for any application where the ambient temperature falls below 0°C. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 9 LP38855 SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com Bias Capacitor The capacitor on the bias pin must be at least 1 µF. It can be any good quality capacitor (ceramic is recommended). INPUT VOLTAGE The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage, which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is used for VBIAS. BIAS VOLTAGE The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide gate drive for the N-FET pass transistor. The bias voltage must be in the range of 3.0V to 5.5V to ensure proper operation of the device. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V. As the bias voltage rises above the UVLO threshold the device control circuitry become active. There is approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity. When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the device will be functional, but the operating parameters will not be within the specified limits. SUPPLY SEQUENCING There is no requirement for the order that VIN or VBIAS are applied or removed. However, the output voltage cannot be ensured until both VIN and VBIAS are within the range of specified operating values. If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommend for this diode clamp. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there will not be any reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold, or the EN pin is held low. When VBIAS is above the UVLO threshold, and the EN pin is above the VEN(ON) threshold, the control circuitry is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin, limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 μF in this manner will not damage the device as the current will decay rapidly. However, continuous reverse current should be avoided. 10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 LP38855 www.ti.com SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 ENABLE OPERATION The Enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The Enable pin has an internal pull-up, through a typical 180 kΩ resistor, to VBIAS. If the Enable pin is actively driven, pulling the Enable pin above the VEN threshold of 1.25V (typical) will turn the regulator output on, while pulling the Enable pin below the VEN threshold will turn the regulator output off. There is approximately 100 mV of hysteresis built into the Enable threshold provide noise immunity. If the Enable function is not needed this pin should be left open, or connected directly to VBIAS. If the Enable pin is left open, stray capacitance on this pin must be minimized, otherwise the output turn-on will be delayed while the stray capacitance is charged through the internal resistance (rEN). POWER DISSIPATION AND HEAT-SINKING A heat-sink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is the sum of three different points of dissipation in the device. The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula: PD(PASS) = (VIN - VOUT) × IOUT (1) The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the formula: PD(BIAS) = VBIAS × IGND(BIAS) where • IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS (2) The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with the formula: PD(IN) = VIN × IGND(IN) where • IGND(IN) is the portion of the operating ground current of the device that is related to VIN (3) The total power dissipation is then: PD = PD(PASS) + PD(BIAS) + PD(IN) (4) The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient temperature (TA(MAX)) for the application, and the maximum allowable operating junction temperature (TJ(MAX)): 'TJ = TJ(MAX) - TA(MAX) (5) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: 'TJ TJA d PD (6) Heat-Sinking the TO-220 Package The TO-220 package has a θJA rating of 60°C/W, and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. The thermal resistance of a TO-220 package can be reduced by attaching it to a heat-sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for DDPAK/TO-263 package. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 11 LP38855 SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 www.ti.com The heat-sink to be used in the application should have a heat-sink to ambient thermal resistance, θHA: THA d TJA - (TCH + TJC) where • • • θJA is the required total thermal resistance from the junction to the ambient air θCH is the thermal resistance from the case to the surface of the heat sink θJC is the thermal resistance from the junction to the surface of the case (7) For this equation, θJC is about 3°C/W for a TO-220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. Consult the heat-sink manufacturer datasheet for details and recommendations. Heat-Sinking the DDPAK/TO-263 Package The DDPAK/TO-263 package has a θJA rating of 60°C/W, and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. The DDPAK/TO-263 package uses the copper plane on the PCB as a heat-sink. The tab of this package is soldered to the copper plane for heat-sinking. The graph below shows a curve for the θJA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat-sinking. Figure 27. θJA vs Copper (1 Ounce) Area for the DDPAK/TO-263 package As shown in Figure 27, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W. Figure 28 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Figure 28. Maximum Power Dissipation vs Ambient Temperature for DDPAK/TO-263 Package 12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 LP38855 www.ti.com SNVS461D – OCTOBER 2006 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LP38855 13 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP38855S-0.8/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38855S -0.8 LP38855S-1.2 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP38855S -1.2 LP38855S-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38855S -1.2 LP38855SX-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP38855S -1.2 LP38855T-0.8/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38855T -0.8 LP38855T-1.2/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 125 LP38855T -1.2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device LP38855SX-1.2/NOPB Package Package Pins Type Drawing SPQ DDPAK/ TO-263 500 KTT 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.85 5.0 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38855SX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA NDH0005D www.ti.com MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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