Cypress CYK256K16MCCBU-55BVI 4-mbit (256k x 16) pseudo static ram Datasheet

CYK256K16MCCB
MoBL3™
4-Mbit (256K x 16) Pseudo Static RAM
Features
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
• Wide voltage range: 2.70V–3.30V
• Access time: 55 ns, 60 ns and 70 ns
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = fmax (70-ns speed)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA package
Functional Description[1]
The CYK256K16MCCB is a high-performance CMOS Pseudo
static RAM organized as 256K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
Writing to the device is accomplished by taking Chip Enable
(CE LOW) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7) is written into the location specified on the address pins
(A0 through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE LOW) and Output Enable (OE) LOW while forcing
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. Refer to the truth table for a complete description of read
and write modes.
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
256K × 16
RAM Array
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
A11
A12
A13
A14
A15
A16
A17
BHE
WE
CE
OE
BLE
Power- Down
Circuit
BHE
BLE
CE
Note:
1. For best practice recommendations, please refer to the CY application note System Design Guidelines on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05585 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 18, 2006
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CYK256K16MCCB
MoBL3™
Pin Configuration[2, 3, 4]
VFBGA
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
Vcc
D
VCC
I/O12 DNU
A16
I/O4
Vss
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Product Portfolio
Power Dissipation
Operating ICC(mA)
VCC Range (V)
Product
CYK256K16MCCB
Min.
Typ.[5]
2.70
3.0
f = 1MHz
Max.
Speed
(ns)
Typ.[5]
3.30
55
1
f = fmax
Standby ISB2(µA)
Max.
Typ.[5]
Max.
Typ.[5]
Max.
5
14
22
17
40
8
15
60
70
Notes:
2. Ball H1, G2 and ball H6 for the VFBGA package can be used to upgrade to an 8-Mbit, 16-Mbit and 32-Mbit density, respectively.
3. NC “no connect” – not connected internally to the die.
4. DNU (Do Not Use) pins have to be left floating or tied to Vss to ensure proper application.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05585 Rev. *F
Page 2 of 10
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CYK256K16MCCB
MoBL3™
DC Input Voltage[6, 7, 8] ....................................–0.4V to 3.7V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied ........................................... –55°C to + 125°C
Supply Voltage to Ground Potential ................ –0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[6, 7, 8] ....................................... –0.4V to 3.7V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
Industrial
–25°C to +85°C
2.70V to 3.30V
Electrical Characteristics Over the Operating Range
CYK256K16MCCB -55, 60, 70
Parameter
Description
Test Conditions
VCC
Supply Voltage
VOH
VOL
Output HIGH Voltage IOH = –0.1 mA
Output LOW
IOL = 0.1 mA
Voltage
VCC = 2.70V
Min.
Typ.[5]
Max.
Unit
2.7
3.0
3.3
V
VCC – 0.4
V
VCC = 2.70V
0.4
V
VIH
Input HIGH Voltage
0.8 * Vcc
VCC + 0.4V
V
VIL
Input LOW Voltage
–0.4
0.6
V
IIX
Input Leakage
Current
GND < VIN < VCC
–1
+1
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC, Output Disabled
–1
+1
µA
ICC
VCC Operating
Supply Current
f = fMAX = 1/tRC
22 for –55
22 for –60
15 for –70
mA
VCC =
VCCmax
IOUT = 0 mA
CMOS levels
f = 1 MHz
14 for –55
14 for –60
8 for –70
1 for all speeds 5 for all speeds
mA
ISB1
Automatic CE
Power-Down
Current—CMOS
Inputs
CE > VCC−0.2V
VCC = 3.3V
VIN > VCC–0.2V, VIN <
0.2V) f = fMAX (Address
and Data Only), f = 0
(OE, WE, BHE and
BLE), VCC = 3.30V
150
250
µA
ISB2
Automatic CE
Power-Down
Current—CMOS
Inputs
CE > VCC – 0.2V
VIN > VCC – 0.2V or
VIN < 0.2V,
f = 0, VCC = 3.30V
17
40
µA
VCC = 3.3V
Thermal Resistance[9]
Parameter
Description
Test Conditions
ΘJA
Thermal Resistance (Junction to Ambient)
ΘJC
Thermal Resistance (Junction to Case)
Test conditions follow standard test methods
and procedures for measuring thermal
impedence, per EIA/JESD51.
BGA
Unit
55
°C/W
17
°C/W
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
Unit
8
pF
8
pF
Notes:
6. VIL(MIN) = –0.5V for pulse durations less than 20 ns.
7. VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
8. Overshoot and undershoot specifications are characterized and are not 100% tested.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05585 Rev. *F
Page 3 of 10
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CYK256K16MCCB
MoBL3™
AC Test Loads and Waveforms
R1
VCC
VCC
OUTPUT
GND
R2
30 pF
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalentto:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
3.0V VCC
Unit
R1
22000
Ω
R2
22000
Ω
RTH
11000
Ω
VTH
1.50
V
Switching Characteristics Over the Operating Range[10]
55 ns[14]
Parameter
Description
Min.
60 ns
Max.
Min.
70 ns
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
60
70
ns
tDOE
OE LOW to Data Valid
25
25
35
ns
tLZOE
tHZOE
55
60
55
OE LOW to LOW
Z[11, 13]
OE HIGH to High
Z[11, 13]
Z[11, 13]
5
70
60
8
5
10
5
25
ns
5
25
2
ns
ns
25
ns
tLZCE
CE LOW to Low
tHZCE
CE HIGH to High Z[11, 13]
25
25
25
ns
tDBE
BLE/BHE LOW to Data Valid
55
60
70
ns
Z[11, 13]
2
ns
70
tLZBE
BLE/BHE LOW to Low
BLE/BHE HIGH to HIGH Z[11, 13]
10
10
25
ns
Address Skew
0
5
10
ns
Write Cycle
5
ns
tHZBE
tSK[14]
5
5
5
ns
[12]
tWC
Write Cycle Time
55
60
70
ns
tSCE
CE LOW to Write End
45
45
60
ns
tAW
Address Set-Up to Write End
45
45
55
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
40
40
45
ns
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels
of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
13. High-Z and Low-Z parameters are characterized and are not 100% tested.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
Document #: 38-05585 Rev. *F
Page 4 of 10
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CYK256K16MCCB
MoBL3™
Switching Characteristics Over the Operating Range[10] (continued)
55 ns[14]
Parameter
Description
Min.
60 ns
Max.
Min.
70 ns
Max.
Min.
Max.
Unit
tBW
BLE/BHE LOW to Write End
50
50
55
ns
tSD
Data Set-Up to Write End
25
25
25
ns
tHD
Data Hold from Write End
0
0
0
ns
High-Z[11, 13]
tHZWE
WE LOW to
tLZWE
WE HIGH to Low-Z[11, 13]
25
5
25
25
5
5
ns
ns
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[14, 15, 16]
tRC
ADDRESS
tSK
DATA OUT
tOHA
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle 2 (OE Controlled)[14, 16]
ADDRESS
CE
tRC
tSK
tHZCE
tACE
BHE/BLE
tLZBE
tDBE
tHZBE
OE
tHZOE
t DOE
DATA OUT
t LZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes:
15. Device is continuously selected. OE, CE = VIL.
16. WE is HIGH for Read Cycle.
Document #: 38-05585 Rev. *F
Page 5 of 10
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CYK256K16MCCB
MoBL3™
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[12, 13, 17, 18, 19]
t WC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
DON’T CARE
tHZOE
Write Cycle 2 (CE Controlled)[12, 13, 17, 18, 19]
t WC
ADDRESS
tSCE
CE
tSA
tHA
tAW
tPWE
WE
tBW
BHE/BLE
OE
t HZOE
DATA I/O
DON’T CARE
tSD
tHD
VALID DATA
Notes:
17. Data I/O is high-impedance if OE > VIH.
18. If Chip Enable goes INACTIVE with WE = VIH, the output remains in a high-impedance state.
19. During this period in the DATA I/O waveform, the I/Os could be in the output state and input signals should not be applied.
Document #: 38-05585 Rev. *F
Page 6 of 10
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CYK256K16MCCB
MoBL3™
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[18, 19]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
t HA
tSA
tPWE
WE
tSD
DATAI/O
DON’T CARE
tHD
VALID DATA
t LZWE
t HZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[18, 19]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
DON’T CARE
Document #: 38-05585 Rev. *F
tHD
VALID DATA
Page 7 of 10
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CYK256K16MCCB
MoBL3™
Truth Table [20]
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H
X
X
X
X
High Z
Deselect/Power-Down
Standby (ISB)
X
X
X
H
H
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
L
L
Data Out (I/O0 – I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/O0 – I/O7);
High Z (I/O8 – I/O15)
Read
Active (ICC)
L
H
L
L
H
High Z (I/O0 – I/O7);
Data Out (I/O8 – I/O15)
Read
Active (ICC)
L
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (I/O0 – I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/O0 – I/O7);
High Z (I/O8 – I/O15)
Write
Active (ICC)
L
L
X
L
H
High Z (I/O0 – I/O7);
Data In (I/O8 – I/O15)
Write
Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
55
CYK256K16MCCBU-55BVI
60
CYK256K16MCCBU-60BVI
51-85150 48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm)
Industrial
70
CYK256K16MCCBU-70BVI
51-85150 48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm)
Industrial
Package Type
51-85150 48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm)
CYK256K16MCBU-55BVXI
Operating
Range
Industrial
48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm) (Pb-Free)
CYK256K16MCBU-70BVXI
48-ball Fine Pitch BGA (6 mm × 8mm × 1.0 mm) (Pb-Free)
Note:
20. H = Logic HIGH, L = Logic LOW, X = Don’t Care.
Document #: 38-05585 Rev. *F
Page 8 of 10
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CYK256K16MCCB
MoBL3™
Package Diagram
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
4
5
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.10 C
0.21±0.05
0.25 C
0.55 MAX.
B
0.15(4X)
51-85150-*D
C
1.00 MAX
0.26 MAX.
SEATING PLANE
MoBL is a registered trademark, and More Battery Life and MoBL3 are trademarks, of Cypress Semiconductor Corporation. All
product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05585 Rev. *F
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CYK256K16MCCB
MoBL3™
Document History Page
Document Title: CYK256K16MCCB MoBL3™4-Mbit (256K x 16) Pseudo Static RAM
Document Number: 38-05585
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
223482
See ECN
REF
New data sheet
*A
234474
See ECN
SYT
Changed ball E3 on package pinout from NC to DNU
*B
260330
See ECN
PCI
Changed from preliminary to final
*C
298651
See ECN
PCI
Added 60-ns speed bin
*D
314013
See ECN
RKF
Added Pb-Free parts to the Ordering information
*E
397852
See ECN
SYT
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed typo in ordering code from CYK256K16MCCB to
CYK256K16MCCBU in the “Ordering Information” on Page#8
Updated the revision of package diagram of Spec 51-85150 from *B to *D
*F
522566
See ECN
NXR
Changed VIL Max spec from 0.4 V to 0.6 V in DC Electrical Characteristics table
Document #: 38-05585 Rev. *F
Page 10 of 10
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