Ordering number : ENA0194A LV24100LP Bi-CMOS IC FM and AM Tuner IC for Small Portable Equipment Overview The LV24100LP is an innovative FM/AM tuner IC that is capable of configuring an FM/AM radio with just one external component. Since all the FM/AM radio functions are incorporated into a compact VQLP package with dimensions of only 5mm×5mm×0.8mm, this IC can easily incorporate FM/AM tuner function into mobile phones, PDA, MP3 player and other small mobile sets where space is always at a premium. Functions • FM Tuner • AM Tuner • MPX stereo decoder • Tuning Features • No external components required except for an AM bar antenna. • No alignments necessary • Improved selectivity with low FMIF frequency (110kHz) • Built-in adjacent channel interference total reduction (no 114kHz, no 190kHz) • New tuning system • Very high sensitivity reception with low-noise mixer input circuit • Built-in low power standby mode eliminates the need for a power switch circuit. • Composite output for RDS applications • 3-wire bus interface (data, clock, and NR-W) featured • Digital AFC function provided • Soft muting and stereo blend functions (8-step software control) • Support for manual search, automatic search, and auto preset • Support for reception of worldwide bands (reception of all bands in Japan, Europe, and the US enabled by changes in the program.) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. N2107 TI IM 20060801-S00001 No.A0194-1/18 LV24100LP Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max Analog block supply voltage VDD max Digital block supply voltage Digital input voltage VIN1 max Clock, Data, NR_W VDD+0.3 V VIN2 max External_clk_in VDD+0.3 V Allowable power dissipation Pd max Ta≤70°C, Mounted on a specified board * 5.0 V 4.5 V 140 mW Operating temperature Topr -20 to +70 °C Storage temperature Tstg -40 to +125 °C Note: Mounted on a specified board: 40mm×50mm×0.8mm, glass epoxy Operating Condition at Ta = 25°C Parameter Recommended supply voltage Symbol VCC Ratings Unit 3.0 V Digital block supply voltage 3.0 V VCC op 3.0 to 4.8 V VDD op 3.0 to 4.0 V VIO op 1.8 to 4.0 V VDD Operating supply voltage range Conditions Analog block supply voltage Interface voltage Note: The VIO application voltage must be either equivalent to VDD or the VDD value or less. (VIO ≤ VDD) Interface Block Allowable Operation Range at Ta = -20 to +70°C, VIO = 3.0V, VSS = 0V Parameter Symbol Ratings Conditions min Supply voltage VDD Digital block input VIH VIL Low level input voltage range Digital block output IOL Output current at Low level VOL Output voltage at Low level IOL=2mA fclk (Pin29) clock frequency for 3wire_bus Clock input operating frequency External clock operating frequency fclk_ext External clock operating voltage Vclk_ext High level input voltage range (Pin31) clock frequency for external input (Pin31) clock voltage for external input typ Unit max 2.5 4.0 V 0.7VDD VDD V 0 0.6 V 2.0 mA 0.6 V 0.7 MHz 32k 14M Hz 0.7VDD VDD V Note: External clock input (pin31) allows also input of the sine wave signal. Frequency deviation is need 250ppm. No.A0194-2/18 LV24100LP Operating Characteristics at Ta=25°C, VCC=3.0V, VDD=3.0V, VIO=3.0V, VSS=0V, Soft Mute/Soft Stereo=off, with the specified test circuit. Output level setting means control register Block 2, Register 07h Bit 6(VOLSH)=0, Register 09h Bit 0 (nAUBST) =0. Parameter Symbol Ratings Conditions min Current drain (in operation) ICCA_FM Measurement at pin 23 with FM 60dBμV monaural input of the analog section. ICCA_AM Measurement at pin 23 with AM 80dBμV input of the analog section. ICCD Measurement at pins 27 and 40 with FM 60dBμV input in the digital block. Current drain (in standby) ICCA_stb 14 17 9 12 15 0.1 0.5 0.8 3 30 3 30 Measurement at pin 23 in the standby mode of F_range In the PCB mounting conditions mA μA Measurement at pins 27 and 40 in the standby mode of the digital block. FM receive band Unit max 11 the analog block. ICCD_stb typ 76 108 MHz FM receiving characteristics MONO : fc=80MHz, fm=1kHz, 22.5kHz dev. VIN=60dBμV, Audio filter=IHF_BPF 3dB sensitivity -3dB LS 22.5kHz dev. output standard, input -3dB. Practical sensitivity 1 QS1 Input level with S/N=30dB Practical sensitivity 2 (Reference) QS2 Input level with S/N=26dB Demodulator output VO Pin11 output 50 5 11 dBμV 10 16 dBμV 70 110 mV 0 2 dB μV 1.25 Channel balance CB Pin11/pin12 output -2 Signal-to-noise ratio S/N Pin11 output 48 58 dB Total harmonic distortion 1 (MONO) THD1 Pin11 output, 22.5kHz dev. 0.4 1.5 % Total harmonic distortion 2 (MONO) THD2 Pin11 output, 75kHz dev. 1.3 3.0 % 49 dBμV FS Field intensity display level Mute attenuation Mute-Att Input level at which FS3 changes to FS4 35 Pin 11 output 60 70 dB FM receive characteristic STEREO characteristic : fc=80MHz, fm=1kHz, VIN60dBμV, L+R=90% (67.5kHz dev.), Pilot=10% (7.5kHz dev.), Audio filter = IHF_BPF+15kHz_LPF Separation Total harmonic distortion (Main) SEP THD-ST L-mod, Pin11/pin12 output 20 Main-mod (for L+R input), Pin11 output 35 dB 1.3 3.0 % AM receive characteristic : fc=1.2MHz, fm=1kHz, 30% mod, Audio filter = IHF_BPF Demodulation output 1 VO1 VIN=30dBμV, Pin11 output 35 55 80 mVrms Demodulation output 2 VO2 VIN=80dBμV, Pin11 output 30 50 75 mVrms Signal-to-noise ratio 1 S/N1 VIN=30dBμV, Pin11 output 14 21 Signal-to-noise ratio 2 S/N2 VIN=80dBμV, Pin11 output 40 45 Total harmonic distortion THD VIN=80dBμV, Pin11 output Field intensity display level FS Input level at which FS3 changes to FS4 1.0 35 dB dB 3.0 % 49 dBμV No.A0194-3/18 LV24100LP Package Dimensions unit : mm (typ) 3302A Top View Bottom View 0.35 5.0 30 21 20 (0.7) 0.4 5.0 0.35 31 40 11 10 1 0.85MAX 0.05 0 NOM (0.7) 0.2 SANYO : VQLP40(5.0X5.0) CLOCK DATA NR_W VDD NC Vstabi NC VCC NC Vstabi2 Block Diagram and Pin Assigment 30 29 28 27 26 25 24 23 22 21 VDD VCC CLK_IN 31 Power management Digital interface NC 32 Package-GND 33 Tuning system Quadrature oscillator Package-GND 34 Voltage stabilizer Package-GND 35 Selectivity filter Pre-scaler Package-GND 36 MPX 19 NC 18 Package-GND 17 Package-GND 16 Package-GND 15 Package-GND 14 Package-GND 13 Package-GND 12 LINE-OUT-R 11 LINE-OUT-L Demodulator Quadrature mixer Package-GND 37 20 Stereo decoder Package-GND 38 De-emphasis NC 39 Ant-cap. Buffer amp. VI/O 40 GND 1 2 3 4 5 6 7 8 9 10 GND AM-ANT1 AM-ANT2 FM-ANT1 FM-ANT2 GND NC NC NC NC GND Top view No.A0194-4/18 LV24100LP Pin Discription Pin 1 Name I/O GND Description Remarks DC Voltage Analog and Digital GND 2 AM-ANT1 I AM Antenna input 3 AM-ANT2 I AM Antenna GND 4 FM-ANT1 I FM Antenna input 5 FM-ANT2 I FM Antenna GND 6 GND 7 NC Analog and Digital GND 8 NC 9 NC 10 NC 11 LINE-OUT-L O 12 LINE-OUT-R O 13 Package-shield GND GND for Package-shield 14 Package-shield GND GND for Package-shield 15 Package-shield GND GND for Package-shield 16 Package-shield GND GND for Package-shield 17 Package-shield GND GND for Package-shield 18 Package-shield GND GND for Package-shield 19 NC Radio Lch Line-output 1.2V Radio Rch Line-output 1.2V 20 MPX MPX-signal output 21 Vstabi2 2nd Stabilizer voltage 22 NC 23 VCC 24 NC 25 Vstabi. 26 NC 27 VDD 28 NR_W I 29 DATA I/O Digital interface DATA Digital interface Clock VCC-0.3V 3.0V Analog supply voltage Stabilizer voltage 2.4V Digital supply voltage 30 CLOCK I 31 CLK_IN I Digital interface Read/Write Reference clock-source input for measurement 32 NC 33 Package-shield GND GND for Package-shield 34 Package-shield GND GND for Package-shield 35 Package-shield GND GND for Package-shield 36 Package-shield GND GND for Package-shield 37 Package-shield GND GND for Package-shield 38 Package-shield GND GND for Package-shield 39 NC 40 VI/O Connect to GND if not used Digital interface supply voltage No.A0194-5/18 LV24100LP The PCB mounting conditions which cover FM receiving frequency range 76MHz to 108MHz This IC Package is printed inductor backside of the package for local oscillation. It is necessary to place GND pattern right under the IC package for covering received frequency range 76MHz to 108MHz. This IC is measured under this condition for received frequency range. Then, the GND pattern must be placed at the center of the IC. Printed circuit board LV24100LP Side-A Side-B GND pattern GND pattern LV24100LP Evaluation board side-A PCB layout recommendations 5.0×5.0 5.0×5.0 1 0.8 3.4 0.7 0.8 1 0.8 0.2 2.2 PCB GND Layer Layer X=3.4 0.4 0.8 21 0.35 Substrate layout of LV24100LP 21 PCB pattern light under of LV24100LP At the GND pattern light under of LV24100LP, X=3.4mm is recommended. The limit of X is min=2.2mm and max=3.6mm same as GND shield size of LV24100LP. Please do not arrange other wirings as much as possible within 0.4mm under the GND pattern. No.A0194-6/18 LV24100LP Serial Data Timing • Write timing tW tHD NR_W tDL DATA tCL VIH VIL tCH CLOCK Symbol Ratings Conditions min typ Unit max tW Delay from command to data 750 ns tDL Delay from data stable to data latch time 750 ns tHD Data Hold time 750 ns tCH Clock High-level time 750 ns tCL Clock Low-level time 750 ns • Read timing tW NR_W tSU tHD DATA CLOCK Symbol Ratings Conditions min typ Unit max tW Delay from command to 1st data bit tSU Data Setup time 350 ns THD Data hold time 350 ns 350 ns No.A0194-7/18 LV24100LP • External clock timing (Pin 31) tCH CLK_IN tCL VIH VIL Symbol Ratings Conditions min Unit typ max tCH Clock High-level time 36 - 15625 ns tCL Clock Low-level time 36 - 15625 ns fext External clock frequency 32 - 14000 kHz VIH High level input voltage level 0.7VDD - VDD V VIL Low level input voltage level 0 - 0.6 V Digital Interface • 3-wire bus (For communication line) Access to the LV24100 is done through the 3-wire bus. CLOCK NR_W Data strobe, input to the LV24100 Command (Read or write data), input to the LV24100 Bi-directional pin: DATA Written data in to the LV24100 when NR_W is high, Read data from the LV24100 when NR_W is low. The LV24100 can be configured to generate interrupt through the DATA-line. When interrupt mode is selected, care should be taken that the DATA-line connection to the application micro-controller also supports interrupt. When the required timing window for frequency measurements is not generated by the application micro-controller, an external clock must be connected to CLK_IN pin of the LV24100. • Register map The LV24100 registers are divided in 3 blocks: Block 01h Status and measurement Block 02h FM Control Block 03h AM control To access a register in a block, the block must be first selected by writing the block number to the BLK_SEL register. Block selection can be skipped for subsequent accesses to other registers in the same block. No.A0194-8/18 LV24100LP The mapping is as follows: Block 01h 02h 03h Address Register name Access Operation 00h CHIP_ID R Chip identification 01h BLK_SEL W Block Select 02h MSRC_SEL W Measure source select 03h FM_OSC W DAC control for FM-RF oscillator 04h SD_OSC W DAC control for stereo decoder oscillator 05h IF_OSC W DAC control for IF oscillator 06h CNT_CTRL W Counter control 07h NA - 08h IRQ_MSK W Interrupt mask 09h FM_CAP W CAP bank control for RF-frequency 0Ah CNT_L R Counter value low byte 0Bh CNT_H R Counter value high byte 0Ch CTRL_STAT R Control status 0Dh RADIO_STAT R Radio station status 0Eh IRQ_ID R Interrupt identify 0Fh IRQ_OUT W Set Interrupt on DATA-line 01h BLK_SEL W Access register 01h of block 1 02h RADIO_CTRL1 W Radio control 1 03h IF_CENTER W IF Center Frequency 04h AM_CAP W All to be set to “0” 05h IF_BW W IF Bandwidth 06h RADIO_CTRL2 W Radio control 2 07h RADIO_CTRL3 W Radio control 3 08h STEREO_CTRL W Stereo control 09h AUDIO_CTRL1 W Audio control 1 0Ah AUDIO_CTRL2 W Audio control 2 0Bh PW_SCTRL W Power and soft control 01h BLK_SEL W Access register 01h of block 1 02h AM_ACAP W AM antenna capacitor 03h AM_FE W AM front end control 04h AM_CTRL W AM control Not mentioned registers are not defined and should not be accessed. No.A0194-9/18 LV24100LP Register Description Block x, Register 01h-BLK_SEL-Block Select Register(Write only) 7 6 5 4 3 2 1 0 2 1 0 BN[7:0] Bit 7-0: BN[7:0]: 8-bit block number. For LV24100, the following numbers are valid: 01h. 02h. 03h. Note: This register can be accessed from any block Block 1, Register 00h-CHIP_ID-Chip Identify Register(Read only) 7 6 5 4 3 ID[7:0] Bit 7-0: ID[7:0]: 8-bit chip ID. For LV24100, value 7 should be read Block 1, Register 02h-MSRC_SEL-Measurement Source Select Register(Write-only) 7 MSR_O Bit 7: 6 5 4 3 2 1 0 AFC_LVL AFC_SPD MSS_RF16 MSS_AM MSS_SD MSS_FM MSS_IF 2 1 0 2 1 0 MSR_O: Output measure source to DATA-pin 0 = Measuring source not available at DATA-pin (normal operation). 1 = Measuring source available at DATA-pin (test mode). Bit 6: AFC_LVL: AFC trigger level 0 = AFC is always active (trigger at 0dBμV) 1 = AFC is only active when field strength is above 20dBμV Bit 5: AFC_SPD: AFC speed 0 = AFC adjusts with 3Hz speed 1 = AFC adjusts with 8kHz speed (test mode) Bit 4: MSS_RF16: RF/16 measurement. 0 = Disable RF/16 oscillator measurement 1 = Enable RF/16 oscillator measurement Bit 3: MSS_AM: AM antenna frequency measurement. 0 = Disable AM antenna measurement 1 = Enable AM antenna measurement Bit 2: MSS_SD: Stereo decoder oscillator measurement 0 = Disable stereo decoder oscillator measurement 1 = Enable stereo decoder oscillator measurement Bit 1: MSS_FM: FM RF oscillator measurement 0 Disable FM RF oscillator measurement 1 = Enable FM RF oscillator measurement Bit 0: MSS_IF: IF oscillator measurement 0 = Disable IF oscillator measurement 1 = Enable IF oscillator measurement Note: Only one of the measurement source MSS_xx bits may be set at a time. The FM RF frequency is divided by 256 or 16 before it goes to the measuring circuitry. Block 1, Register 03h-FM_OSC-FM RF Oscillator Register(Write-only) 7 6 5 4 3 FMOSC[7:0] Bit 7-0: FMOSC[7:0]: DAC value to control the FM RF oscillator (fine step) Note: Positive DAC control (i.e. the frequency increases with the register’s value) See also FM_CAP register Block 1, Register 04h-SD_OSC-Stereo Decoder Oscillator Register(Write-only) 7 6 5 4 3 SDOSC[7:0] Bit 7-0: SDOSC[7:0]: DAC value to control the stereo decoder oscillator Note: Positive DAC control(i.e. the frequency increases with the register’s value) No.A0194-10/18 LV24100LP Block 1, Register 05h-IF_OSC-IF Oscillator Register(Write-only) 7 6 5 4 3 2 1 0 IFOSC[7:0] Bit 7-0: IFOSC[7:0]: DAC value to control the IF oscillator Note: Positive DAC control (i.e. the frequency increases with the register’s value) Block 1, Register 06h-CNT_CTRL-Counters Control Register(Write-only) 7 6 5 4 3 2 1 0 CNT1_CLR CTAB2 CTAB1 CTAB0 SWP_CNT_L CNT_EN CNT_SEL CNT_SET Bit 7: CNT1_CLR: Clear counter 1 bit 0 = Normal mode 1 = Clear and keep counter 1 in reset mode Bit 6-4: CTAB[2:0]: Tab select for counter 2 measuring interval bits Bit 3: Value Dec. Stop value 000b 0 Stop after 2 counts 001b 1 Stop after 8 counts 010b 2 Stop after 32 counts 011b 3 Stop after 128 counts 100b 4 Stop after 512 counts 101b 5 Stop after 2048 counts 110b 6 Stop after 8192 counts 111b 7 Stop after 32768 counts SWP_CNT_L: Swap counter 1 and counter 2 bit(Active low) 0 = Clock source 1 to counter 2, clock source 2 to counter 1(swapping) 1 = Clock source 1 to counter 1, clock source 2 to counter 2(no swap) Bit 2: CNT_EN: Enable the currently selected counter bit 0 = Disable counter(stop counting) 1 = Enable counter(counting mode) Bit 1: CNT_SEL: counter select bit 0 = Select counter 1 for measurement 1 = Select counter 2 for measurement Bit 0: CNT_SET: Set counters bit 0 = Normal mode 1 = Set both counter 1 and counter 2 to FFFFh and keep them set Block 1, Register 08h-IRQ_MSK-Interrupt Mask Register(Write-only) 7 6 Reserved IM_MS 5 4 Reserved Bit 7: Reserved: Must be programmed with 0. Bit 6: IM_MS: Mono/Stereo interrupt mask bit 3 2 1 0 IRQ_LVL IM_AFC IM_FS IM_CNT2 0 = Disable mono/stereo change interrupt 1 = Enable mono/stereo change interrupt Bit 5: Reserved: Must be programmed with 0. Bit 4: Reserved: Must be programmed with 0. Bit 3: IRQ_LVL: Interrupt level select bit 0 = Drive DATA-line from low to high when interrupt occurs(active high) 1 = Drive DATA-line from high to low when interrupt occurs(active low) Bit 2: IM_AFC: AFC out of range interrupt mask bit 0 = Disable AFC out of range interrupt 1 = Enable AFC out of range interrupt Bit 1: IM_FS: Field strength change interrupt mask bit 0 = Disable field strength change interrupt 1 = Enable field strength change interrupt Bit 0: IM_CNT2: Counter 2 counting done interrupt mask bit 0 = Disable counter 2 counting done interrupt 1 = Enable counter 2 counting done interrupt No.A0194-11/18 LV24100LP Block 1, Register 09h-FM_CAP-FM RF Capacitor Bank Register(Write-only) 7 6 5 4 3 2 1 0 2 1 0 2 1 0 FMCAP[7:0] Bit 7-0: FMCAP[7:0]: CAP bank value to control the FM RF frequency (coarse steps) Note: 7½ bit CAP value (Bit[7:6]: Combination 10b and 01b results in the same CAP-range) Negative control: de RF frequency decreases when increasing the register’s value See also FM_OSC register Block 1, Register 0Ah-CNT_L-Counter Value Low Register(Read-only) 7 6 5 4 3 CNT_LSB[7:0] Bit 7-0: CNT_LSB[7:0]: Lower 8-bit value of the 16 bit counter Block 1, Register 0Bh-CNT_H-Counter Value High Register(Read-only) 7 6 5 4 3 CNT_MSB[7:0] Bit 7-0: CNT_MSB[7:0]: Upper 8-bit value of the 16 bit counter Block 1, Register 0Ch-CTRL_STAT-Control Status Register(Read-only) 7 6 5 4 REV3 REV2 REV1 REV0 Bit 7-4: REV[3:0]: should be read as 0Dh Bit 3-2: Reserved[1:0]: should be read as all 1 Bit 1: COV_FLG: counter overflow flag 3 2 Reserved 1 0 COV_FLG AFC_FLG 1 0 0 = No overflow of the internal counter 1 = The last counting loop causes overflow of the internal counter Bit 0: AFC_FLG: AFC out of range bit 0 = AFC is within control range 1 = AFC is out of control range Note: Reading this register will clear AFC, count 2 done interrupt. COV_FLG is clear when CLR_CNT1 bit of CNT_CTRL register is high Block 1, Register 0Dh-RADIO_STAT-Radio Station Status Register(Read-only) 7 6 5 4 RSS_MS Bit 7: 3 2 RSS_FS RSS_MS: Radio station mono/stereo state bit 0 = Mono 1 = Stereo Bit 6-0: RSS_FS[6:0]: Radio station field strength bits 1111111b = Field strength less then 10dBμV 0111111b = Field strength between 10 to 20dBμV 0011111b = Field strength between 20 to 30dBμV 0001111b = Field strength between 30 to 40dBμV 0000111b = Field strength between 40 to 50dBμV 0000011b = Field strength between 50 to 60dBμV 0000001b = Field strength between 60 to 70dBμV 0000000b = Field strength above 70dBμV Note: Reading this register will clear field strength and mono/stereo interrupt No.A0194-12/18 LV24100LP Block 1, Register 0Eh-IRQ_ID-Interrupt Identify Register(Read-only) 7 6 Reserved 5 4 3 II_CNT2 Reserved II_AFC Bit 7: Reserved: should be read as 1 Bit 6: Reserved: should be read as 1 Bit 5: II_CNT2: Counter 2 counting done flag 2 1 Reserved 0 II_FS_MS 0 = No counting 2 counting done interrupt 1 = Measuring with counter 2 is done Bit 4: Reserved: should be read as 0 Bit 3: II_AFC: AFC out of range interrupt bit 0 = No AFC interrupt 1 = AFC fails to hold the RF-frequency in range Bit 2: Reserved: should be read as 0 Bit 1: Reserved: should be read as 0 Bit 0: II_FS_MS: Field strength and Mono/stereo interrupt bit 0 = No change in either the field strength or the mono/stereo mode 1 = Change in field strength bits detected or mono/stereo mode has changed Block 1, Register 0Fh-IRQ_OUT-Set Interrupt Out Register(Write Only) 7 6 5 4 3 2 1 0 IRQO_VAL[7:0] Bit 7-0: IRQO_VAL[7:0]: Write any value to this register will select the interrupt as output on the DATA-line of the LV24100 (the DATA-line can then be used as interrupt pin) Block 2, Register 02h-RADIO_CTRL1-Radio Control 1 Register(Write-only) 7 6 5 4 3 2 1 0 EN_MEAS EN_AFC Reserved AM_CD2 DIR_AFC RST_AFC AM_CD1 AM_CD0 Bit 7: EN_MEAS: Enable measurement bit 0 = Normal mode 1 = Measurement mode Bit 6: EN_AFC: Enable AFC bit 0 = Disable AFC 1 = Enable AFC Bit 5: EN_RF16:Enable RF16 Divider bit 0 = Disable RF16 1 = Enable RF16 Bit 4: AM_CD2: AM clock divider bit 2. Should be kept at 1 in FM mode Bit 3: DIR_AFC: AFC direction bit 0 = AFC normal direction 1 = AFC reverse direction (for test purpose) Bit 2: RST_AFC: Reset AFC bit 0 = Normal operation 1 = Reset AFC to the middle of the control range Bit 1: AM_CD1: AM clock divider bit 1. Should be kept at 1 in FM mode Bit 0: AM_CD0: AM clock divider bit 0. Should be kept at 1 in FM mode Note: The AM_CD[2:0] bits are used to scale the FM-RF frequency down to AM-RF frequency. In FM mode, the AM divider should be turned off. AM_CD[2:0] Divider factor 0 48 1354 Approx. AM-RF (in kHz) 2291 1 64 1015 1718 2 80 812 1375 3 96 677 1145 4 128 507 859 5 160 406 687 6 192 338 572 7 Divider OFF Block 2, Register 03h-IFCEN_OSC-IF Center Frequency Oscillator Register(Write-only) 7 6 5 4 3 2 1 0 IFCOSC[7:0] Bit 7-0: IFCENT[7:0]: value for centering the IF frequency No.A0194-13/18 LV24100LP Block 2, Register 04h-AM_CAP(Write-only) 7 6 5 4 3 2 1 0 3 2 1 0 AM_CAP[7:0] Bit 7-0: AM_CAP[7:0]:all bit to be set to 0 Block 2, Register 05h-IF_BW-IF Bandwidth Register(Write-only) 7 6 5 4 IFBW[7:0] Bit 7-0: IFBW[7:0]: Value for IF bandwidth Block 2, Register 06h-RADIO_CTRL2-Radio Control 2 Register(Write-only) 7 6 5 4 3 2 1 0 VREF2 VREF STABI_BP IF_PM_L DCFB_SPD DCFB_OFF AGCSP Reserved 1 Bit 7: VREF2: VREF2 control bit 0 = VREF2 is ON 1 = VREF2 is OFF VREF: VREF control bit Bit 6: 0 = VREF is ON 1 = VREF is OFF Bit 5: STABI_BP: Voltage stabilizer bypass bit 0 = Internal voltage is Vstabi (normal operation) 1 = Internal voltage is VCC (stabilizer bypassed) Bit 4: IF_PM_L: IF PLL mute bit 0 = IF PLL mute on (presetting IF mode) 1 = IF PLL mute off (normal operation mode) Bit 3: DCFB_SPD: DC feedback speed 0 = normal speed 1 = high speed (test mode) Bit 2: DCFB_OFF: DC feedback control 0 = Enable DC feedback (FM mode) 1 = Turn off the DC feedback (AM mode) Bit 1: AGCSP: AGC speed control bit 0 = Normal speed 1 = High speed (test mode) Bit 0: Reserved: should be written with 0 Block 2, Register 07h-RADIO_CTRL3-Radio Control 3 Register(Write-only) 7 6 5 4 3 2 AGC_SLVL VOLSH Reserved AMUTE_L SE_FM SE_AM Bit 7: AGC_SLVL: AGC set level bit Bit 6: VOLSH: Volume level shift bit 0 Reserved This bit must be set to 1 0 = Normal volume level 1 = Extra volume of 12dB Bit 5: Reserved: should be written with 0 Bit 4: AMUTE_L: Audio mute bit 0 = Audio muted 1 = Audio not muted Bit 3: SE_FM: FM radio select bit 0 = Disable FM radio 1 = Enable FM radio Bit 2: SE_AM: AM radio select bit 0 = Disable AM radio 1 = Enable AM radio Bit 1: Reserved: should be written with 0 Bit 0: Reserved: should be written with 0 Note: Do not set bit 3 and 2 on at the same time. No.A0194-14/18 LV24100LP Block 2, Register 08h-STEREO_CTRL-Stereo Control Register(Write-only) 7 6 FRCST Bit 7: 5 4 FMCS[2:0] 3 2 1 0 DLT_TNE PILOTCANC SD_PM ST_M 2 1 0 FRCST: Force stereo bit 0 = Normal mode 1 = Force stereo mode for test Bit 6-4: FMCS[2:0]: FM channel separation bits Bit 3: DLT_TNE: Delta tune bit 0…7=FM channel separation level 0 = Decrease delta tune 1 = Normal delta tune Bit 2: PILOTCANC: Pilot cancellation bit 0 = No pilot cancellation 1 = Pilot cancellation enabled Bit 1: SD_PM: Stereo decoder PLL mute bit 0 = Stereo decoder PLL not muted(normal operation) 1 = Stereo decoder PLL is muted(presetting mode) Bit 0: ST_M: FM stereo/mono mode bit 0 = Stereo mode 1 = Mono mode Block 2, Register 09h-AUDIO_CTRL1-Audio Control 1 Register(Write-only) 7 6 5 4 3 Reserved Bit 7-1: Reserved: should be written with 0 Bit 0: nAUBST: Audio output level boost bit nAUBST 0 = Boost output level with 3dB 1 = No output level boosting Block 2, Register 0Ah-AUDIO_CTRL2-Audio Control 2 Register(Write-only) 7 6 Reserved 5 4 3 DEEMP Bit 7-6: Reserved: should be written with 1 Bit 5: DEEMP: De-emphasis bit 2 1 0 1 0 Reserved PW_RAD 1 0 Reserved 0 = De-emphasis 50μs. 1 = De-emphasis 75μs. Bit 4-0: Reserved: should be written with 0 Block 2, Register 0Bh-PW_SCTRL-Power and Soft Control Register(Write-only) 7 6 5 4 SS_CTRL Bit 7-5: 3 2 SM_CTRL SS_CTRL: Soft stereo control bits(8 levels) 000b = Minimal soft stereo(off) 111b = Maximal soft stereo level Bit 4-2: SM_CTRL: Soft audio mute bits(8 levels) 000b = Minimal soft audio mute(off) 111b = Maximal soft audio mute level Bit 1: Reserved: should be written with 0 Bit 0: PW_RAD: Radio circuitry power bit 0 = Radio circuitry is switched OFF. 1 = Switch radio circuitry ON Note: PW_RAD is 0 at power up Block 3, Register 02h-AM_ACAP-AM Antenna Capacitor Bank Register(Write-only) 7 6 5 4 3 2 AMCAP[7:0] Bit 7-0: AMCAP[7:0]: CAP bank value to control the AM antenna frequency Note: AM antenna capacitor bank is controlled by 10 bits. The upper 2 bits are located in AM_FE register. Negative control: de frequency decreases when increasing the register’s value. No.A0194-15/18 LV24100LP Block 3, Register 03h-AM_FE-AM Front End Register(Write-only) 7 6 5 4 AGC_LVL 3 2 AGC_GAIN Bit 7-5: AGC_LVL[2:0]: AGC level bits Bit 4: AAGC_EG: AM AGC extra gain Bit 3-2: AAGC_GAIN[1:0]: AM AGC gain setting Bit 1-0: AMCAP[9:8]: Upper bits of AM antenna capacitor bank 1 0 AMCAP9 AMCAP8 1 0 Block 3, Register 04h-AM_CTRL-AM Control Register(Write-only) 7 6 5 4 3 2 AMFE_AT AABSW nFIFAGC AMFE_EN AM_CAL nAMEMG Bit 7: FE_SPD[1:0] AMFE_AT: AM front end attenuator 0 = Disable AM front end attenuator 1 = Enable AM front end attenuator Note: This bit is don’t care for FM and should be 1 for AM Bit 6: AABSW: AM antenna band switch 0 = Switch off AM antenna band 1 = Switch on AM antenna band Bit 5: nFIFAGC: Fast IF AGC(active low) 0 = Fast IF AGC speed 1 = Norma lF AGC speed Note: This bit must be 0 for FM. In AM mode, this bit must be 1 and can be changed to 0 during scanning for AM stations to speed up the scan operation. Bit 4: AMFE_EN: Enable AM front end bit 0 = Disable AM front end 1 = Enable AM front end Bit 3: AM_CAL: AM calibration bit 0 = Disable AM calibration(normal operation) 1 = Enable AM calibration(calibrate AM antenna frequency mode) Note: This bit must be set to 1 before measuring the AM antenna frequency Bit 2: nAMEMG: Extra gain AM mixer bit 0 = Extra mixer gain(normal operation) 1 = No extra mixer gain Bit 1-0: FE_SPD[1:0]: AM front end speed bits No.A0194-16/18 LV24100LP Test Circuit 200Ω 200Ω 200Ω 200Ω Micro-controller VDD(3.0V) 100nF VCC(3.0V) 22μF VCC VDD NR_W DATA CLOCK 100nF 1μF 30 29 28 27 26 25 24 23 22 21 CLK_IN 31 20 32 19 33 18 34 17 LV24100LP 35 16 36 15 37 14 38 13 39 12 40 11 VI/O 1 10nF 2 3 4 5 6 7 8 100nF Line-out-R 100nF Line-out -L 9 10 180μH 50Ω AM SSG 18μH 50Ω 1nF 50Ω FM SSG 50Ω No.A0194-17/18 LV24100LP VDD Application Circuit VCC(3.3V) 200Ω 200Ω 200Ω 200Ω Micro-controller 10Ω or 1μH Option 0.22μF 22μF VCC VDD DATA NR_W CLOCK 0.1μF 4.7Ω or 2.2μH 1μF 30 29 28 27 26 25 24 23 22 21 CLK_IN 31 20 32 19 33 18 34 17 LV24100LP 35 GND* 16 VCC 36 15 37 14 GND* 38 13 Line-out-R 39 12 40 11 VI/O 1 AM ANT 2 3 4 5 6 7 9 10 1μF Headphone Amp. Line-out -L 1μH 1μH 22μF 2.2μH GND FM ANT 240μH GND* : Package shield GND 8 1μF 22μF 100pF SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2007. Specifications and information herein are subject to change without notice. PS No.A0194-18/18