M27C2001 2 Mbit (256Kb x 8) UV EPROM and OTP EPROM ■ 5V ± 10% SUPPLY VOLTAGE in READ OPERATION ■ FAST ACCESS TIME: 55ns ■ LOW POWER CONSUMPTION: 32 32 – Active Current 30mA at 5MHz – Standby Current 100µA ■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V ■ PROGRAMMING TIME: 100µs/byte (typical) ■ ELECTRONIC SIGNATURE 1 1 FDIP32W (F) PDIP32 (B) – Manufacturer Code: 20h – Device Code: 61h DESCRIPTION The M27C2001 is a high speed 2 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large programs and is organised as 262,144 by 8 bits. The FDIP32W (window ceramic frit-seal package) and LCCC32W (leadless chip carrier package) have a transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C2001 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages. Table 1. Signal Names LCCC32W (L) PLCC32 (K) Figure 1. Logic Diagram VCC VPP 18 8 A0-A17 A0-A17 Address Inputs Q0-Q7 Data Outputs E Chip Enable E G Output Enable G P Program VPP Program Supply VCC Supply Voltage VSS Ground April 1999 TSOP32 (N) 8 x 20 mm P Q0-Q7 M27C2001 VSS AI00716B 1/16 M27C2001 VCC P A17 A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3 1 32 A7 A6 A5 A4 A3 A2 A1 A0 Q0 9 M27C2001 25 A14 A13 A8 A9 A11 G A10 E Q7 17 VSS Q3 Q4 Q5 Q6 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 M27C2001 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 A12 A15 A16 VPP VCC P A17 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS Figure 2B. LCC Pin Connections Q1 Q2 Figure 2A. DIP Pin Connections AI00718 AI00717 Figure 2C. TSOP Pin Connections A11 A9 A8 A13 A14 A17 P VCC VPP A16 A15 A12 A7 A6 A5 A4 1 8 9 16 32 M27C2001 (Normal) 25 24 17 AI01153B 2/16 G A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 A3 The operationg modes of the M27C2001 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M27C2001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C2001 has a standby mode which reduces the supply current from 30mA to 100µA. The M27C2001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. M27C2001 Table 2. Absolute Maximum Ratings (1) Symbol Parameter Value Unit Ambient Operating Temperature (3) –40 to 125 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage (except A9) –2 to 7 V Supply Voltage –2 to 7 V –2 to 13.5 V –2 to 14 V TA VCC VA9 (2) A9 Voltage Program Supply Voltage VPP Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes E G P A9 VPP Q0-Q7 Read VIL VIL X X VCC or VSS Data Out Output Disable VIL V IH X X VCC or VSS Hi-Z Program VIL V IH VIL Pulse X VPP Data In Verify VIL VIL VIH X VPP Data Out Program Inhibit VIH X X X VPP Hi-Z Standby VIH X X X VCC or VSS Hi-Z Electronic Signature VIL VIL VIH VID VCC Codes Mode Note: X = VIH or VIL, VID = 12V ± 0.5V. Table 4. Electronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h Device Code VIH 0 1 1 0 0 0 0 1 61h Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. 3/16 M27C2001 Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V 1.5V 0.8V and 2V Input and Output Timing Ref. Voltages Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 1N914 3V 1.5V 3.3kΩ 0V DEVICE UNDER TEST Standard 2.4V OUT CL 2.0V 0.8V 0.4V AI01822 CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condit ion Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output 4/16 control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. M27C2001 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol Parameter Test Condition Min Max Unit 0V ≤ VIN ≤ VCC ±10 µA 0V ≤ VOUT ≤ VCC ±10 µA E = VIL , G = VIL, IOUT = 0mA, f = 5MHz 30 mA E = VIH 1 mA E > VCC – 0.2V 100 µA V PP = VCC 10 µA ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current ICC1 Supply Current (Standby) TTL ICC2 Supply Current (Standby) CMOS IPP Program Current VIL Input Low Voltage –0.3 0.8 V VIH (2) Input High Voltage 2 VCC + 1 V VOL Output Low Voltage 0.4 V VOH IOL = 2.1mA Output High Voltage TTL IOH = –400µA 2.4 V Output High Voltage CMOS IOH = –100µA VCC – 0.7V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V. Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27V2001 Symbol Alt Parameter Test Condition -55 (3) Min tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV -70 Max Min -80 -90 Max Min Max Unit Min Max E = VIL , G = V IL 55 70 80 90 ns Chip Enable Low to Output Valid G = VIL 55 70 80 90 ns tOE Output Enable Low to Output Valid E = VIL 30 35 40 40 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 30 0 30 0 30 0 30 ns t GHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 30 0 30 0 30 0 30 ns tAXQX tOH Address Transition to Output Transition E = VIL , G = V IL 0 0 0 0 ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. 3. In case of 45ns speed see High Speed AC measurament conditions. 5/16 M27C2001 Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27V2001 Symbol Alt Parameter Test Condition -10 Min tAVQV tACC Address Valid to Output Valid tELQV tCE tGLQV -12 Max Min -15/-20/-25 Max Min Unit Max E = VIL, G = VIL 100 120 150 ns Chip Enable Low to Output Valid G = VIL 100 120 150 ns tOE Output Enable Low to Output Valid E = VIL 50 50 60 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 30 0 40 0 50 ns tGHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 30 0 40 0 50 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 0 ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A17 VALID tAVQV VALID tAXQX E tGLQV tEHQZ G tELQV Q0-Q7 tGHQZ Hi-Z AI00719B Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C2001 are in the ’1’ state. Data is introduced by selectively programming ’0’s into the desired bit locations. Although only ’0’s will be programmed, both ’1’s and ’0’s can be present in the data word. The only way to change a ’0’ to a ’1’ is by die exposition to ultravio- 6/16 let light (UV EPROM). The M27C2001 is in the programming mode when VPP input is at 12.75V, E is at VIL and P is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V ±0.25V. M27C2001 Table 9. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Parameter Test Condition Min 0 ≤ V IN ≤ VIH Max Unit ±10 µA 50 mA 50 mA ILI Input Leakage Current ICC Supply Current IPP Program Current VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage 0.4 V VOH Output High Voltage TTL VID A9 Voltage E = VIL IOL = 2.1mA IOH = –400µA 2.4 V 11.5 12.5 V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. Table 10. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol Alt Parameter Test Condition Min Max tAVPL tAS Address Valid to Program Low 2 µs tQVPL tDS Input Valid to Program Low 2 µs tVPHPL tVPS VPP High to Program Low 2 µs t VCHPL tVCS VCC High to Program Low 2 µs tELPL tCES Chip Enable Low to Program Low 2 µs tPLPH tPW Program Pulse Width 95 tPHQX tDH Program High to Input Transition 2 µs tQXGL tOES Input Transition to Output Enable Low 2 µs tGLQV tOE Output Enable Low to Output Valid tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 tGHAX tAH Output Enable High to Address Transition 0 105 Unit µs 100 ns 130 ns ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. 7/16 M27C2001 Figure 6. Programming and Verify Modes AC Waveforms VALID A0-A17 tAVPL Q0-Q7 DATA IN tQVPL DATA OUT tPHQX VPP tVPHPL tGLQV tGHQZ VCC tVCHPL tGHAX E tELPL P tPLPH tQXGL G PROGRAM VERIFY AI00720 Figure 7. Programming Flowchart VCC = 6.25V, VPP = 12.75V n=0 P = 100µs Pulse NO ++n = 25 YES FAIL NO VERIFY ++ Addr YES Last Addr NO YES CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V AI00715C 8/16 PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 26.5 seconds. Programming with PRESTO II consists of applying a sequence of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple M27C2001s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27C2001 may be common. A TTL low level pulse applied to a M27C2001’s P input, with E low and VPP at 12.75V, will program that M27C2001. A high level E input inhibits the other M27C2001s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E and G at VIL, P at VIH, VPP at 12.75V and VCC at 6.25V. M27C2001 On-Board Programming The M27C2001 can be directly programmed in the application circuit. See the relevant Application Note AN620. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27C2001. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27C2001 with VPP=VCC=5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at V IL during Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device identifier code. For the STMicroelectronics M27C2001, these two identifier bytes are given in Table 4 and can be read-out on outputs Q0 to Q7. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27C2001 are such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Data shows that constant exposure to room level fluorescent lighting could erase a typical M27C2001 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C2001 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C2001 window to prevent unintentional erasure. The recommended erasure procedure for the M27C2001 is exposure to short wave ultraviolet light which has wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating. The M27C2001 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. 9/16 M27C2001 Table 11. Ordering Information Scheme Example: M27C2001 -55 X C 1 X Device Type M27 Supply Voltage C = 5V Device Function 2001 = 2Mb, 256Kb x8 Speed -55 -70 -80 -90 -10 (1) = 55 ns = 70 ns = 80 ns = 90 ns = 100 ns Not for New Design -12 = 120 ns -15 = 150 ns -20 = 200 ns -25 = 250 ns V CC Tolerance X = ± 5% blank = ± 10% Package F = FDIP32W B = PDIP32 L = LCCC32W C = PLCC32 N = TSOP32: 8 x 20mm Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Optio ns X = Additional Burn-in TR = Tape & Reel Packing Note: 1. High Speed, see AC Characteristics section for further information. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 10/16 M27C2001 Table 12. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data Symb mm Typ inches Min Max A Typ Min 5.72 Max 0.225 A1 0.51 1.40 0.020 0.055 A2 3.91 4.57 0.154 0.180 A3 3.89 4.50 0.153 0.177 B 0.41 0.56 0.016 0.022 B1 – – – – C 1.45 0.23 0.30 0.009 0.012 D 41.73 42.04 1.643 1.655 – – 1.500 – – 0.600 D2 38.10 E 15.24 E1 – – 13.06 13.36 0.057 – – 0.514 0.526 e 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – eB 16.18 18.03 0.637 0.710 L 3.18 S 1.52 2.49 – – α 4° 11° N 32 ∅ 7.11 0.125 0.060 0.098 – – 4° 11° 0.280 32 Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline A2 A3 A1 B1 B A L e α eA D2 C eB D S N ∅ E1 E 1 FDIPW-a Drawing is not to scale. 11/16 M27C2001 Table 13. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data mm Symb Typ inches Min Max A – A1 Min Max 5.08 – 0.200 0.38 – 0.015 – A2 3.56 4.06 0.140 0.160 B 0.38 0.51 0.015 0.020 – – – – C 0.20 0.30 0.008 0.012 D 41.78 42.04 1.645 1.655 B1 1.52 Typ 0.060 D2 38.10 – – 1.500 – – E 15.24 – – 0.600 – – 13.59 13.84 0.535 0.545 E1 e1 2.54 – – 0.100 – – eA 15.24 – – 0.600 – – eB 15.24 17.78 0.600 0.700 L 3.18 3.43 0.125 0.135 S 1.78 2.03 0.070 0.080 α 0° 10° 0° 10° N 32 32 Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline A2 A1 B1 B A L e1 α eA D2 C eB D S N E1 E 1 PDIP Drawing is not to scale. 12/16 M27C2001 Table 14. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, with window, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min Max 2.28 0.090 B 0.51 0.71 0.020 0.028 D 11.23 11.63 0.442 0.458 E 13.72 14.22 0.540 0.560 – – – – 0.39 – 0.015 – e 1.27 e1 0.050 e2 7.62 – – 0.300 – – e3 10.16 – – 0.400 – – h 1.02 – – 0.040 – – j 0.51 – – 0.020 – – L 1.14 1.40 0.045 0.055 L1 1.96 2.36 0.077 0.093 K 10.50 10.80 0.413 0.425 K1 8.03 8.23 0.316 0.324 N 32 32 Figure 10. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, with window, Package Outline e2 D j x 45o e N 1 L1 K E e3 e1 B K1 A h x 45o L LCCCW-a Drawing is not to scale. 13/16 M27C2001 Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data Symb mm Typ inches Min Max A 2.54 A1 Typ Min Max 3.56 0.100 0.140 1.52 2.41 0.060 0.095 A2 – 0.38 – 0.015 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 D 12.32 12.57 0.485 0.495 D1 11.35 11.56 0.447 0.455 D2 9.91 10.92 0.390 0.430 E 14.86 15.11 0.585 0.595 E1 13.89 14.10 0.547 0.555 E2 12.45 13.46 0.490 0.530 – – – – 0.00 0.25 0.000 0.010 – – – – e 1.27 F R 0.89 0.050 0.035 N 32 32 Nd 7 7 Ne 9 9 CP 0.10 0.004 Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline D D1 A1 A2 1 N B1 E1 E Ne e D2/E2 F B 0.51 (.020) 1.14 (.045) A Nd R PLCC Drawing is not to scale. 14/16 CP M27C2001 Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data mm inches Symb Typ Min Max A Typ Min 1.20 Max 0.047 A1 0.05 0.15 0.002 0.007 A2 0.95 1.05 0.037 0.041 B 0.15 0.27 0.006 0.011 C 0.10 0.21 0.004 0.008 D 19.80 20.20 0.780 0.795 D1 18.30 18.50 0.720 0.728 E 7.90 8.10 0.311 0.319 - - - - L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° N 32 e 0.50 0.020 32 CP 0.10 0.004 Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C TSOP-a A1 α L Drawing is not to scale. 15/16 M27C2001 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://w ww.st.com 16/16