TI1 MC79L15ACLPM Negative-voltage regulator Datasheet

SLVS011D − OCTOBER 1982 − REVISED AUGUST 2003
D
D
D
D
D
D
D
D PACKAGE
(TOP VIEW)
3-Terminal Regulators
Output Current Up To 100 mA
No External Components Required
Internal Thermal-Overload Protection
Internal Short-Circuit Current Limiting
Direct Replacement for Industry-Standard
MC79L00 Series
Available in 5% or 10% Selections
OUTPUT
INPUT†
INPUT†
NC
1
8
2
7
3
6
4
5
NC
INPUT†
INPUT†
COMMON
† Internally connected
NC − No internal connection
description/ordering information
LP PACKAGE
(TOP VIEW)
This
series
of
fixed
negative-voltage
OUTPUT
integrated-circuit voltage regulators is designed
INPUT
for a wide range of applications. These include
COMMON
on-card regulation for elimination of noise and
distribution problems associated with single-point
regulation. In addition, they can be used to control series pass elements to make high-current voltage-regulator
circuits. One of these regulators can deliver up to 100 mA of output current. The internal current-limiting and
thermal-shutdown features essentially make the regulators immune to overload. When used as a replacement
for a Zener-diode and resistor combination, these devices can provide an effective improvement in output
impedance of two orders of magnitude, with lower bias current.
ORDERING INFORMATION
TJ
OUTPUT
VOLTAGE
TOLERANCE
NOMINAL
OUTPUT
VOLTAGE
(V)
PACKAGE†
SOIC (D)
−5
TO-226 / TO-92 (LP)
5%
0°C
0
C to 125
125°C
C
SOIC (D)
−12
TO-226 / TO-92 (LP)
−15
10%
−12
TO-226 / TO-92 (LP)
TO-226 / TO-92 (LP)
ORDERABLE
PART NUMBER
Tube of 75
MC79L05ACD
Reel of 2500
MC79L05ACDR
Bulk of 1000
MC79L05ACLP
Reel of 2000
MC79L05ACLPR
Tube of 75
MC79L12ACD
Reel of 2500
MC79L12ACDR
Bulk of 1000
MC79L12ACLP
Reel of 2000
MC79L12ACLPR
Bulk of 1000
MC79L15ACLP
Ammo of 2000
MC79L15ACLPM
Reel of 2000
MC79L15ACLPR
Bulk of 1000
MC79L12CLP
TOP-SIDE
MARKING
79L05A
79L05AC
79L12A
79L12AC
79L15AC
79L12C
−15
SOIC (D)
Tube of 75
MC79L15CD
79L15C
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
! "#$ %!&
% "! "! '! ! !( !
%% )*& % "!+ %! !!$* $%!
!+ $$ "!!&
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLVS011D − OCTOBER 1982 − REVISED AUGUST 2003
equivalent schematic
COMMON
OUTPUT
INPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage: MC79L05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 V
MC79L12, MC79L15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −35 V
Package thermal impedance, θJA (see Notes 1 and 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
LP package . . . . . . . . . . . . . . . . . . . . . . . . . . 140°C/W
Operating free-air, case, or virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
VI
IO
TJ
2
Input voltage
MIN
MAX
MC79L05
−7
−20
MC79L12
−14.5
−27
MC79L15
−17.5
−30
Output current
Operating virtual junction temperature
0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
100
mA
125
°C
SLVS011D − OCTOBER 1982 − REVISED AUGUST 2003
electrical characteristics at specified virtual junction temperature, VI = −10 V, IO = 40 mA (unless
otherwise noted)
PARAMETER
Output voltage‡
Input regulation
Ripple rejection
Output regulation
VI = −7 V to −20 V,
IO = 1 mA to 40 mA
VI = −10 V, IO = 1 mA to 70 mA
VI = −7 V to −20 V
VI = −8 V to −20 V
Output noise voltage
Dropout voltage
IO = 40 mA
Bias current
VI = −8 V to −20 V
IO = 1 mA to 40 mA
MC79L05AC
TJ
MIN
TYP
MAX
MIN
TYP
MAX
25°C
−4.6
−5
−5.4
−4.8
−5
−5.2
0°C to 125°C
−4.5
−5.5
−4.75
−5.25
0°C to 125°C
−4.5
−5.5
−4.75
−5.25
25°C
VI = −8 V to −18 V, f = 120 Hz
IO = 1 mA to 100 mA
IO = 1 mA to 40 mA
f = 10 Hz to 100 kHz
Bias current change
MC79L05C
TEST CONDITIONS†
25°C
40
200
150
150
100
49
25°C
25°C
40
25°C
1.7
41
49
V
mV
dB
60
60
30
30
mV
µV
40
1.7
V
25°C
6
6
125°C
5.5
5.5
1.5
1.5
0.2
0.1
0°C to 125°C
UNIT
mA
mA
† All characteristics are measured with a 0.33-µF capacitor across the input and a 0.1-µF capacitor across the output. Pulse-testing techniques are
used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately.
‡ This specification applies only for dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI = −19 V, IO = 40 mA (unless
otherwise noted)
PARAMETER
Output voltage‡
Input regulation
Ripple rejection
Output regulation
VI = −14.5 V to −27 V,
IO = 1 mA to 40 mA
VI = −19 V, IO = 1 mA to 70 mA
VI = −14.5 V to −27 V
VI = −16 V to −27 V
Output noise voltage
Dropout voltage
IO = 40 mA
Bias current
VI = −16 V to −27 V
IO = 1 mA to 40 mA
MC79L12AC
TJ
MIN
TYP
MAX
MIN
TYP
MAX
25°C
−11.1
−12
−12.9
−11.5
−12
−12.5
0°C to 125°C
−10.8
−13.2
−11.4
−12.6
0°C to 125°C
−10.8
−13.2
−11.4
−12.6
25°C
VI = −15 V to −25 V, f = 120 Hz
IO = 1 mA to 100 mA
IO = 1 mA to 40 mA
f = 10 Hz to 100 kHz
Bias current change
MC79L12C
TEST CONDITIONS†
25°C
36
250
250
200
200
42
25°C
37
42
UNIT
V
mV
dB
100
100
50
50
mV
25°C
80
80
µV
25°C
1.7
1.7
V
25°C
6.5
6.5
125°C
6
6
1.5
1.5
0.2
0.1
0°C to 125°C
mA
mA
† All characteristics are measured with a 0.33-µF capacitor across the input and a 0.1-µF capacitor across the output. Pulse-testing techniques are
used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately.
‡ This specification applies only for dc power dissipation permitted by absolute maximum ratings.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SLVS011D − OCTOBER 1982 − REVISED AUGUST 2003
electrical characteristics at specified virtual junction temperature, VI = −23 V, IO = 40 mA (unless
otherwise noted)
PARAMETER
Output voltage‡
Input regulation
Ripple rejection
Output regulation
VI = −17.5 V to −30 V,
IO = 1 mA to 40 mA
VI = −23 V, IO = 1 mA to 70 mA
VI = −17.5 V to −30 V
VI = −17.5 V to −30 V
VI = −18.5 V to −28.5 V, f = 120 Hz
IO = 1 mA to 100 mA
Output noise voltage
IO = 1 mA to 40 mA
f = 10 Hz to 100 kHz
Dropout voltage
IO = 40 mA
Bias current
Bias current change
MC79L15C
TEST CONDITIONS†
VI = −20 V to −30 V
IO = 1 mA to 40 mA
MC79L15AC
TJ
MIN
TYP
MAX
MIN
TYP
MAX
25°C
−13.8
−15
−16.2
−14.4
−15
−15.6
0°C to 125°C
−13.5
−16.5
−14.25
−15.75
0°C to 125°C
−13.5
−16.5
−14.25
−15.75
25°C
25°C
33
300
300
250
250
39
25°C
25°C
90
25°C
1.7
34
39
V
mV
dB
150
150
75
75
mV
µV
90
1.7
V
25°C
6.5
6.5
125°C
6
6
1.5
1.5
0.2
0.1
0°C to 125°C
UNIT
mA
mA
† All characteristics are measured with a 0.33-µF capacitor across the input and a 0.1-µF capacitor across the output. Pulse-testing techniques are
used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately.
‡ This specification applies only for dc power dissipation permitted by absolute maximum ratings.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MC79L05ACD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L05A
MC79L05ACDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L05A
MC79L05ACDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L05A
MC79L05ACDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L05A
MC79L05ACDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L05A
MC79L05ACDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L05A
MC79L05ACLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L05AC
MC79L05ACLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L05AC
MC79L05ACLPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L05AC
MC79L05ACLPRE3
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L05AC
MC79L12ACD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L12A
MC79L12ACDE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L12A
MC79L12ACDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L12A
MC79L12ACDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L12A
MC79L12ACDRE4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 125
79L12A
MC79L12ACLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L12AC
MC79L12ACLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L12AC
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MC79L12ACLPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L12AC
MC79L12ACLPRE3
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L12AC
MC79L12CLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L12C
MC79L15ACLP
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L15AC
MC79L15ACLPE3
ACTIVE
TO-92
LP
3
1000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L15AC
MC79L15ACLPR
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L15AC
MC79L15ACLPRE3
ACTIVE
TO-92
LP
3
2000
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
0 to 125
79L15AC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MC79L05ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
MC79L12ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MC79L05ACDR
SOIC
D
8
2500
340.5
338.1
20.6
MC79L12ACDR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
PACKAGE OUTLINE
LP0003A
TO-92 - 5.34 mm max height
SCALE 1.200
SCALE 1.200
TO-92
5.21
4.44
EJECTOR PIN
OPTIONAL
5.34
4.32
(1.5) TYP
SEATING
PLANE
(2.54)
NOTE 3
2X
4 MAX
(0.51) TYP
6X
0.076 MAX
SEATING
PLANE
2X
2.6 0.2
3X
12.7 MIN
3X
3X
0.55
0.38
0.43
0.35
2X 1.27 0.13
FORMED LEAD OPTION
STRAIGHT LEAD OPTION
OTHER DIMENSIONS IDENTICAL
TO STRAIGHT LEAD OPTION
3X
2.67
2.03
4.19
3.17
3
2
1
3.43 MIN
4215214/B 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Lead dimensions are not controlled within this area.
4. Reference JEDEC TO-226, variation AA.
5. Shipping method:
a. Straight lead option available in bulk pack only.
b. Formed lead option available in tape and reel or ammo pack.
c. Specific products can be offered in limited combinations of shipping medium and lead options.
d. Consult product folder for more information on available options.
www.ti.com
EXAMPLE BOARD LAYOUT
LP0003A
TO-92 - 5.34 mm max height
TO-92
0.05 MAX
ALL AROUND
TYP
FULL R
TYP
METAL
TYP
(1.07)
3X ( 0.85) HOLE
2X
METAL
(1.5)
2X (1.5)
2
1
(R0.05) TYP
3
2X (1.07)
(1.27)
SOLDER MASK
OPENING
2X
SOLDER MASK
OPENING
(2.54)
LAND PATTERN EXAMPLE
STRAIGHT LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X
0.05 MAX
ALL AROUND
TYP
( 1.4)
2X ( 1.4)
METAL
3X ( 0.9) HOLE
METAL
(R0.05) TYP
2
1
(2.6)
SOLDER MASK
OPENING
3
2X
SOLDER MASK
OPENING
(5.2)
LAND PATTERN EXAMPLE
FORMED LEAD OPTION
NON-SOLDER MASK DEFINED
SCALE:15X
4215214/B 04/2017
www.ti.com
TAPE SPECIFICATIONS
LP0003A
TO-92 - 5.34 mm max height
TO-92
13.7
11.7
32
23
(2.5) TYP
0.5 MIN
16.5
15.5
11.0
8.5
9.75
8.50
19.0
17.5
6.75
5.95
2.9
TYP
2.4
3.7-4.3 TYP
13.0
12.4
FOR FORMED LEAD OPTION PACKAGE
4215214/B 04/2017
www.ti.com
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