Holtek HT1647 4-level gray scale 64 16 lcd controller for i/o mcu Datasheet

HT1647
4-Level Gray Scale 64´16 LCD Controller for I/O MCU
PATENTED
PAT No. : 099352
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage: 2.7V~5.2V
· R/W address auto increment
· Built-in 32kHz RC oscillator
· Built-in buzzer driver (2kHz/4kHz)
· External 32.768kHz crystal oscillator or 32kHz fre-
· Power down command reduces power consumption
quency source input
· Software configuration feature
· Standby current: < 1mA at 3V, < 2mA at 5V
· Data mode and Command mode instructions
· Internal resistor type: 1/5 bias or 1/4 bias, 1/16 duty
· Three data accessing modes
· Two selectable LCD frame frequencies: 89Hz or
· Provides VLCD pin to adjust LCD operating voltage
170Hz
· Provides three kinds of bias current programming
· Max. 64´16 patterns, 64 segments and 16 commons
· Control of TN-type, STN-type LCDs and ECB-type
· Built-in bit-map display RAM: 2048 bits (=64´16´2
LCDs
· Four-level gray scale output for TN-type, STN-type
bits)
· Built-in internal resistor type bias generator
LCDs panel
· Six-wire interface (four data wires)
· Four-color output for ECB-type LCDs panel
· Eight kinds of time base/WDT selection
· 100-pin QFP package and in chip form
· Time base or WDT overflow output
Applications
· Leisure products
· Cellular phone
· Games
· Global positioning system
· Personal digital assistant
· Consumer electronics
General Description
4-level gray scale display. It displays 4-level gray scale
output when the HT1647 drives a TN-type, STN-type
LCDs. It displays four color output when the HT1647
drives an ECB-type. HT1647 uses PWM (Pulse Width
Modulation) technique. The software configuration feature of the HT1647 make it suitable for multiple LCD applications including LCD modules and display
subsystems. Only six lines (CS, WR, DB0~DB3) are required for the interface between the host controller and
the HT1647.
HT1647 is a peripheral device specially designed for I/O
type MCU used to expand the display capability. The
max. display segment of the device are 1024 patterns
(64 segments and 16 commons). It also supports four
data bits interface, buzzer sound, Watchdog Timer or
time base timer functions. The HT1647 is a memory
mapping and multi-function LCD controller. Since the
HT1647 can control ECB-type (Electrically Controlled
Birefringence) LCDs in addition to current TN-type
(Twisted Nematic) or STN-type (Super Twisted Nematic) LCDs, it can support 4-color display as well as
Rev. 1.40
1
November 9, 2010
PATENTED
HT1647
Block Diagram
O S C O
D is p la y R A M
O S C I
C S
C o n tro l
&
T im in g
C ir c u it
R D
W R
D B 0
C O M 0
L C D D r iv e r /
B ia s C ir c u it
C O M 1 5
S E G 0
D B 3
S E G 6 3
V D D
V L C D
V S S
B Z
W a tc h d o g T im e r
&
T im e B a s e G e n e r a to r
T o n e F re q u e n c y
G e n e ra to r
B Z
N o te : C S : C h ip s
B Z , B Z : T o
W R , R D : W
D B 0 ~ D B 3 :
C O M 0 ~ C O
IR Q : T im e
IR Q
e le c tio n
n e o u tp u ts
R IT E c lo c k , R E A D c lo c k
D a ta b u s
M 1 5 , S E G 0 ~ S E G 6 3 : L C D o u tp u ts
b a s e o r W D T o v e r flo w o u tp u t
Pin Assignment
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
1 0 0
1
4 4
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
C S
R D
W R
D B 0
D B 1
D B 2
D B 3
V S S
O S C I
O S C O
V D D
V L C D
IR Q
B Z
B Z
T 1
T 2
T 3
T 4
N C
C O M 0
C O M 1
C O M 2
C O M 3
C O M 4
C O M 5
C O M 6
C O M 7
C O M 8
C O M 9
8 1
8 0
H T 1 6 4 7
1 0 0 Q F P -A
5 1
5 0
3 0
3 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
C O M
C O M
1 3
1 2
1 1
1 0
9
8
7
1 5
1 4
2
6
5
4
3
2
1
0
1 3
1 2
1 1
1 0
Rev. 1.40
November 9, 2010
PATENTED
HT1647
Pad Assignment
1 4
S E G 5 6
1 5
S E G 5 7
1 6
S E G 5 8
1 7
S E G 5 9
1 8
S E G 6 0
1 9
S E G 6 1
2 0
S E G 6 2
2 1
S E G 6 3
2 2
S E G 1 7
S E G 5 5
S E G 1 8
1 3
S E G 1 9
S E G 5 4
S E G 2 0
1 2
S E G 2 1
S E G 5 3
S E G 2 2
1 1
S E G 2 3
1 0
S E G 5 2
S E G 2 4
S E G 5 1
S E G 2 5
9
S E G 2 6
S E G 5 0
S E G 2 7
8
S E G 2 8
S E G 4 9
S E G 2 9
7
S E G 3 0
S E G 4 8
S E G 3 1
S E G 4 7
6
S E G 3 2
5
S E G 3 3
S E G 4 6
S E G 3 4
4
S E G 3 5
S E G 4 5
S E G 3 6
3
S E G 3 7
S E G 4 4
S E G 3 8
2
S E G 3 9
S E G 4 3
S E G 4 0
1
S E G 4 1
S E G 4 2
9 9
9 8
9 7
9 6
9 5
9 4
9 3
9 2
9 1
9 0
8 9
8 8
8 7
8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
7 5
(0 , 0 )
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 6
3 7
3 8
3 9
4 0
S E G 1 1
6 8
S E G 1 0
6 7
S E G 9
6 6
S E G 8
6 5
S E G 7
6 4
S E G 6
6 3
S E G 5
6 2
S E G 4
6 1
S E G 3
6 0
S E G 2
5 9
S E G 1
5 8
S E G 0
5 7
C O M 1 5
5 6
C O M 1 4
5 5
C O M 1 3
5 4
C O M 1 2
5 3
C O M 1 1
5 2
C O M 1 0
5 1
C O M 9
5 0
C O M 8
4 1
4 3
4 4
4 5
4 6
4 7
4 8
4 9
C O M 6
C O M 7
T 4
T 3
T 2
T 1
B Z
B Z
IR Q
V L C D
V D D
O S C O
O S C I
V S S
D B 3
D B 2
D B 1
D B 0
4 2
C O M 5
2 5
S E G 1 2
6 9
C O M 4
W R
3 5
S E G 1 3
7 0
C O M 3
2 4
S E G 1 4
7 1
C O M 2
R D
S E G 1 5
7 2
C O M 1
2 3
S E G 1 6
C O M 0
C S
7 4
7 3
Chip size: 3865 ´ 3770 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
-1774.50
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
1708.30
1409.80
1281.80
1150.00
1022.00
890.20
762.20
630.40
502.40
370.60
242.60
110.80
-17.20
34
35
36
37
38
39
40
41
42
43
44
45
46
-331.40
-194.50
-48.00
87.40
235.20
383.40
530.40
678.60
875.00
1003.00
1134.80
1262.80
1394.60
-1600.00
-1558.30
-1600.00
-1600.00
-1600.00
-1600.00
-1600.00
-1600.00
-1712.30
-1712.30
-1712.30
-1712.30
-1712.30
67
68
69
70
71
72
73
74
75
76
77
78
79
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1471.10
1343.10
1211.30
1083.30
951.50
795.30
927.10
1055.10
1186.90
1314.90
1446.70
1574.70
1706.50
1708.30
1708.30
1708.30
1708.30
1708.30
Rev. 1.40
3
November 9, 2010
PATENTED
HT1647
Pad No.
X
Y
Pad No.
X
Y
Pad No.
X
Y
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1779.30
-1690.00
-1690.00
-1690.00
-1430.20
-1294.80
-1149.50
-1013.90
-872.80
-738.30
-600.10
-465.60
-149.00
-277.00
-408.80
-536.80
-668.60
-796.60
-928.80
-1056.80
-1189.00
-1375.40
-1515.40
-1651.00
-1599.90
-1599.90
-1599.90
-1599.90
-1600.00
-1600.00
-1600.00
-1600.00
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
1522.60
1654.40
1782.40
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
1775.70
-1712.30
-1712.30
-1712.30
-1411.10
-1283.10
-1151.30
-1023.30
-891.50
-763.50
-631.70
-503.70
-371.90
-243.90
-112.10
15.90
147.70
275.70
407.50
535.50
667.30
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
823.50
691.70
563.70
431.90
303.90
172.10
44.10
-87.70
-215.70
-347.50
-475.50
-607.30
-735.30
-867.10
-995.10
-1126.90
-1254.90
-1386.70
-1514.70
-1646.50
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
1708.30
Pad Description
Pad No.
23
Pad Name
CS
I/O
Description
I
Chip selection input with pull-high resistor. When the CS is logic high, the
data and command read from or write to the HT1647 are disabled. The serial
interface circuit is also reset. But if the CS is at a logic low level and is input to
the CS pad, the data and command transmission between the host controller and the HT1647 are all enabled.
24
RD
I
READ clock input with pull-high resistor. Data in the RAM of the HT1647 are
clocked out on the rising edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next falling edge to
latch the clocked out data.
25
WR
I
WRITE clock input with pull-high resistor. Data on the DATA line are latched
into the HT1647 on the rising edge of the WR signal.
26~29
DB0~DB3
I/O
Parallel data input/output with a pull-high resistor
30
VSS
¾
Negative power supply for logic circuit, ground
31
OSCI
I
32
OSCO
O
33
VDD
¾
34
VLCD
I
Power supply for LCD driver circuit
35
IRQ
O
Time base or Watchdog Timer overflow flag, NMOS open drain output.
36, 37
BZ, BZ
O
2kHz or 4kHz frequency output pair (tristate output buffer)
38~41
T1~T4
I
Not connected
42~57
COM0~COM15
O
LCD common outputs
58~99,
1~22
SEG0~SEG63
O
LCD segment outputs
Rev. 1.40
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left
open.
Positive power supply for logic circuit
4
November 9, 2010
PATENTED
HT1647
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+5.5V
Storage Temperature ............................-50°C to 125°C
Input Voltage.............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-25°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
VDD
IDD1
IDD2
IDD11
IDD22
ISTB
VIL
VIH
IOL1
IOH1
IOL2
IOH2
IOL3
IOH3
IOL4
Parameter
Operating Voltage
Operating Current
Operating Current
Operating Current
Operating Current
Standby Current
Input Low Voltage
Input High Voltage
BZ, BZ, IRQ Sink Current
BZ, BZ Source Current
DB0~DB3 Sink Current
DB0~DB3 Source Current
LCD Common Sink Current
LCD Common Source Current
LCD Segment Sink Current
IOH4
LCD Segment Source Current
RPH
Pull-high Resistor
Rev. 1.40
Ta=25°C
Test Conditions
VDD
Conditions
¾
¾
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
Min.
Typ.
Max.
Unit
2.7
¾
5.2
V
No load/LCD ON
On-chip RC oscillator
¾
150
250
mA
¾
250
370
mA
No load/LCD ON
Crystal oscillator
¾
135
200
mA
¾
200
300
mA
No load/LCD OFF
On-chip RC oscillator
¾
15
30
mA
¾
50
70
mA
No load/LCD OFF
Crystal oscillator
¾
2
10
mA
¾
3
10
mA
¾
¾
1
mA
¾
¾
2
mA
0
¾
0.6
V
0
¾
1.0
V
2.4
¾
3
V
No load, Power down mode
DB0~DB3, WR, CS, RD
DB0~DB3, WR, CS, RD
4.0
¾
5
V
3V
VOL=0.3V
1.2
2.5
¾
mA
5V
VOL=0.5V
3
6
¾
mA
3V
VOH=2.7V
-0.9
-1.8
¾
mA
5V
VOH=4.5V
-2
-4
¾
mA
3V
VOL=0.3V
1.2
2.5
¾
mA
5V
VOL=0.5V
3
6
¾
mA
3V
VOH=2.7V
-0.9
-1.8
¾
mA
5V
VOH=4.5V
-2
-4
¾
mA
3V
VOL=0.3V
80
160
¾
mA
5V
VOL=0.5V
180
360
¾
mA
3V
VOH=2.7V
-40
-80
¾
mA
5V
VOH=4.5V
-90
-180
¾
mA
3V
VOL=0.3V
50
100
¾
mA
5V
VOL=0.5V
120
240
¾
mA
3V
VOH=2.7V
-30
-60
¾
mA
5V
VOH=4.5V
-70
-140
¾
mA
5V
3V
5V
DB0~DB3, WR, CS, RD
5
150
250
410
kW
60
125
210
kW
November 9, 2010
PATENTED
HT1647
A.C. Characteristics
Symbol
fSYS1
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
3V
System Clock
3V
System Clock
Crystal oscillator
5V
3V
fSYS3
fLCD1
System Clock
External clock source
40
kHz
¾
32.768
¾
kHz
¾
32.768
¾
kHz
¾
32
¾
kHz
32
¾
kHz
89/170 111/213
Hz
Crystal oscillator
External clock source
¾
n: Number of COM
3V
Duty cycle 50%
5V
3V
4-Bit Data Clock (RD Pin)
Duty cycle 50%
5V
4-Bit Interface Reset Pulse Width
(Figure 3)
32
61/117
5V
tCS
24
Hz
3V
fCLK2
kHz
On-chip RC oscillator
LCD Frame Frequency
4-Bit Data Clock (WR Pin)
40
89/170 111/213
5V
fCLK1
32
¾
LCD Frame Frequency
LCD Common Period
22
61/117
LCD Frame Frequency
tCOM
Unit
5V
3V
fLCD3
Max.
3V
5V
fLCD2
Typ.
On-chip RC oscillator
5V
fSYS2
Min.
¾
CS
¾
64
¾
Hz
¾
64
¾
Hz
¾
64
¾
Hz
¾
64
¾
Hz
¾
n/fLCD
¾
sec
¾
¾
150
kHz
¾
¾
300
kHz
¾
¾
75
kHz
¾
¾
150
kHz
¾
250
¾
ns
¾
¾
ms
¾
¾
ms
Write mode
3.34
Read mode
6.67
Write mode
1.67
Read mode
3.34
3V
tCLK
WR, RD Input Pulse Width (Figure 1)
5V
tr, tf
Rise/Fall Time Serial Data Clock 3V
Width (Figure 1)
5V
¾
¾
120
¾
ns
tsu
Setup Time for DB to WR, RD Clock 3V
Width (Figure 2)
5V
¾
¾
120
¾
ns
th
Hold Time for DB to WR, RD Clock 3V
Width (Figure 2)
5V
¾
¾
120
¾
ns
tsu1
Setup Time for CS to WR, RD Clock 3V
Width (Figure 3)
5V
¾
¾
100
¾
ns
th1
Hold Time for CS to WR, RD Clock 3V
Width (Figure 3)
5V
¾
¾
100
¾
ns
Rev. 1.40
6
November 9, 2010
PATENTED
HT1647
V A L ID
tf
W R , R D
C lo c k
9 0 %
5 0 %
1 0 %
D B
tr
tC
V
tC
L K
ts
D D
G N D
W R , R D
C lo c k
L K
tC
5 0 %
ts
W R , R D
C lo c k
th
u 1
1
S
F IR S T
C lo c k
L A S T
C lo c k
th
u
5 0 %
D D
G N D
G N D
V
D D
G N D
V
5 0 %
V
Figure 2
Figure 1
C S
D A T A
5 0 %
D D
G N D
Figure 3
Functional Description
a system power down command. But if the external
clock source is chosen as the system clock, using the
SYS DIS command can neither turn the oscillator off nor
carry out the power down mode. The crystal oscillator
option can be applied to connect an external frequency
source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the
case in the external 32kHz clock source operation. At
the initial system power on, the HT1647 is at the SYS
DIS state.
System Oscillator
The HT1647 system clock is used to generate the time
base/Watchdog Timer (WDT) clock frequency, LCD
driving clock, and tone frequency. The clock source
may be from an on-chip RC oscillator (32kHz), a crystal
oscillator (32.768kHz), or an external 32kHz clock by
the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias
generator will turn off. That command is available only
for the on-chip RC oscillator or for the crystal oscillator.
Once the system clock stops, the LCD display will become blank, and the time base/WDT loses its function
as well.
Display Memory - RAM Structure
The static display RAM is organized into 512´4 bits and
stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in
the RAM can be accessed by the READ, WRITE and
READ-MODIFY-WRITE commands. The following is a
mapping from the RAM to the LCD patterns.
The LCD OFF command is used to turn the LCD bias
generator off. After the LCD bias generator switches off
by issuing the LCD OFF command, using the SYS DIS
command reduces power consumption, thus serving as
O S C I
O S C O
C r y s ta l O s c illa to r
3 2 7 6 8 H z
E x te r n a l C lo c k S o u r c e
3 2 k H z
S y s te m
C lo c k
O n - c h ip R C O s c illa to r
3 2 k H z
System Oscillator Configuration
Rev. 1.40
7
November 9, 2010
PATENTED
C O M 1 5
HT1647
C O M 1
C O M 1 4
C O M 0
S E G 0
7
0
S E G 1
1 5
8
S E G 2
2 3
1 6
S E G 3
3 1
2 4
S E G 6 3
5 1 1
5 0 4
D 3
D 2
D 1
D 0
A d d r
D a ta
D 3
D 2
D 1
D 0
A d d r e s s 9 B its
(A 8 , A 7 , ...., A 0 )
A d d r
D a ta
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
: T w o b it s o f R A M m a p t o L C D 's o n e p ix e l a n d d e c id e 4 - le v e l g r a y s c a le
o r 4 - c o lo r d is p la y c o n c u r r e n tly .
Display Memory - RAM Structure
Gray Scale Level Decision
Gray Scale Display
HT1647 uses PWM technique to provide 4-level gray
scale display. Two bits of RAM data code ((D3, D2) or
(D1, D0)) decide one pixel level of LCDs, level 1~level
divided by 4. Every level must be defined as one kind of
gray scale by PWM data (namely B4~B0) previously.
If the user choose 89Hz frame frequency, a max. of 24
sections can be programmed to suit a satisfactory gray
scale in every level. Similarly, if the user choose 170Hz
frame frequency, a max. of 13 sections can be programmed to suit a satisfactory gray scale in every level.
HT1647 provides 5-bit PWM data to control the length of
the section. In other words, a max. Of 24 gray scales are
generated by 5-bit binary PWM data. At FRAME 89Hz
mode, the HT1647 only provides a max. of 24 adjustable gray scales although 32 is the expressed max.
value by 5 bits binary code. When 5 bits binary code
value is more than 23, the PWM control circuit uniformly
regards 23. To increase PWM data indicates to increase
the length of the active segment signal. The varied
length of the active segment signal displays varied gray
scale in TN-type, STN-type LCDs (refer to table 1). Similarly, it displays varied color in ECB-type LCDs. The
color display is derived from ECB-type LCD specification. At FRAME 170Hz mode, the HT1647 only provides
a max. of 13 adjustable gray scales although 32 is the
expressed max. value by 5 bits binary code. When the 5
bits binary code value is more than 12, the PWM control
circuit uniformly regards 12. The user must appoint four
kinds of PWM data to four kinds of different gray scale
level by commanding PWM data (refer to table 2).
RAM Data Code
(D3, D2) or (D1, D0)
Choice Gray Scale Level
(1, 1)
Level 1
(1, 0)
Level 2
(0, 1)
Level 3
(0, 0)
Level 4
RAM Data Defined Gray Scale Level
Frame Frequency
HT1647 provides two kinds of frame frequency option
by command code; 89Hz and 170Hz respectively.
FRAME 89Hz provides 89Hz frame frequency and active segment signal width can be divided into 24 sections concurrently. FRAME 170Hz provides 170Hz
frame frequency and active segment signal width can be
divided into 13 sections concurrently. The 24 sections
display a particularly gray scale more than the 13 sections by PWM data. The default is FRAME 89Hz.
Name
Command Code
Function
FRAME 170Hz
X100-0001-1000-XXXX
Select 170Hz frame frequency and active segment signal
width can be divided into 13 sections
FRAME 89Hz
X100-0001-1101-XXXX
Select 89Hz frame frequency and active segment signal width
can be divided into 24 sections
Frame Frequency Selection Command Code
Rev. 1.40
8
November 9, 2010
PATENTED
HT1647
Relationship Table between PWM Data and Gray Scale
V a lu e
0
1
2
3
5
4
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
5 b its P W M
B 4 B 3 B 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
1
0
1
0
1
1
0
1
1
0
1
d a ta
B 1 B 0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
(O N
1
1
1
1
1
1
1
1
1
1
2
2
2
P W M
w id th ) G r a y S c a le
V a lu e
d a ta
1 3
B 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
B 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
B 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
B 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3 1
1
1
1
1
1
0
0 (0 /2 3 )
1 /2 3
2 /2 3
3 /2 3
4 /2 3
5 /2 3
6 /2 3
7 /2 3
8 /2 3
9 /2 3
0 /2 3
1 /2 3
2 /2 3
3 /2 3
4 /2 3
5 /2 3
6 /2 3
7 /2 3
8 /2 3
9 /2 3
0 /2 3
1 /2 3
2 /2 3
1 (2 3 /2 3 )
1 (2 4 /2 3 )
5 b its P W M
B 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
(O N
1
1
1
1
P W M
w id
0 (0 /1
1 /1 2
2 /1 2
3 /1 2
4 /1 2
5 /1 2
6 /1 2
7 /1 2
8 /1 2
9 /1 2
0 /1 2
1 /1 2
(1 2 /1
(1 3 /1
th )
2 )
G r a y S c a le
2 )
2 )
1 (3 1 /1 2 )
Table 2: FRAME 170Hz Mode
Note:
The varied PWM data displays various gray scale
in TN-type, STN-type LCDs.
The color display derives from ECB-type LCD¢s
specification.
3 1
1
1
1
1
1
1 (3 1 /2 3 )
Table 1: FRAME 89Hz Mode
Name
Command Code
Function
GRS LEVEL 1
X100-001 B4-B3 B2 B1 B0-XXXX
Set PWM data in gray scale level 1
GRS LEVEL 2
X100-010 B4-B3 B2 B1 B0-XXXX
Set PWM data in gray scale level 2
GRS LEVEL 3
X100-011 B4-B3 B2 B1 B0-XXXX
Set PWM data in gray scale level 3
GRS LEVEL 4
X100-100 B4-B3 B2 B1 B0-XXXX
Set PWM data in gray scale level 4
Four Kinds of Gray Scale Level Command Code
1 6
V
1
2
1 6
1
2
L C D
V 1
V 2
C O M
V 3
V 4
V
S S
W
V
L C D
W '
V 1
V 2
S E G
V 3
V
V 4
S S
W '
C O M ~ S E G
V
L C D
3 /5 V
L C D
1 /5 V
L C D
-1 /5 V
L C D
-3 /5 V
L C D
-V
L C D
W
O N
1 fr
N o t e : " W '" R e a l a c t iv e s e g m e n t s ig n a l w
" W " M a x . a c tiv e s e g m e n t s ig n a l w
P W M ( O N w id t h ) : W '/ W , 0 £ W '/ W £
a m
id
id
1
O N
O F F
e
th ( a d ju s ta b le w id th b y P W M
th
( r e fe r to ta b le 1 & ta b e l 2 )
d a ta )
Example of Waveform (B Type) in 1/5 Bias, 1/16 Duty Cycle Drive
Rev. 1.40
9
November 9, 2010
PATENTED
HT1647
Time Base and Watchdog Timer - WDT
Command Format
The time base generator and WDT share the same
counter which is divided by 256. The IRQ clock can be programmed as 1Hz, 2Hz, ...., 128Hz output. TIMER
DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will remain at a logic low level until the
CLR WDT or the IRQ DIS command is issued.
The HT1647 can be configured by software setting.
There are two mode commands to configure the
HT1647 resource and to transfer the LCD display data.
The configuration mode of the HT1647 is called command mode, and its command mode ID is 100. The
command mode consists of a system configuration
command, a system frequency selection command, an
LCD configuration command, a tone frequency selection command, a bias current selection command, a
gray scale level selection command, a timer/WDT setting command, and an operating command. The data
mode, on the other hand, includes READ, WRITE, and
READ-MODIFY-WRITE operations.
If an external clock is selected as the system frequency
source, the SYS DIS command turns out invalid and the
power down mode fails to be carried out until the external clock source is removed.
Buzzer Tone Output
A simple tone generator is implemented in the HT1647.
The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate
a single tone.
The following are the data mode ID and the command
mode ID:
Operation
By executing the TONE 4K and TONE 2K commands
there are two tone frequency outputs selectable that can
turn on the tone output. The TONE 4K and TONE 2K
commands set the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned off by invoking
the TONE OFF command. The tone outputs, namely BZ
and BZ, are a pair of differential driving outputs used to
drive a piezo buzzer. Once the system is disabled or the
tone output is inhibited, the BZ and the BZ outputs will
remain at low level.
Mode
ID
READ
Data
110
WRITE
Data
101
READ-MODIFY-WRITE
Data
101
Command
100
COMMAND
If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the
non-successive address data mode, the CS pin should
be set to ²1² and the previous operation mode will also
be reset. The CS pin returns to ²0², so a new operation
mode ID should be issued first.
T im e B a s e
C lo c k S o u r c e
V
C L R
IR Q
T IM E R E N /D IS
/2 5 6
T im e r
W D T
/4
W D T E N /D IS
D D
Q
D
C K
IR Q
E N /D IS
R
C L R W D T
Time Base and WDT Configurations
Name
Command Code
Function
TONE OFF
X100-0000-1000-XXXX
Turn-off tone output
TONE 4K
X100-0001-0000-XXXX
Turn-on tone output, tone frequency is 4kHz
TONE 2K
X100-0001-0001-XXXX
Turn-on tone output, tone frequency is 2kHz
Buzzer Tone Output Command Code
Rev. 1.40
10
November 9, 2010
PATENTED
HT1647
Bias Generator
The HT1647 bias voltage belongs to internal resistor
type. It provides two kinds of bias option named 1/5 bias
and 1/4 bias respectively. It is recommended to select
1/5 bias to fit TN-type, STN-type LCDs and select 1/4
bias to fit ECB-type LCDs. It also provides three kinds of
bias current option by programming to suitably drive an
LCD panel. The three kinds of bias current are large,
middle, and small, respectively. Usually, large panel
LCD can be excellently displayed by large bias current.
Relatively, it consumes large current when LCD ON
command is used. Small bias current provides low
power consumption during On condition when the LCD
is normally displayed. The following are the reference
value table.
VLCD
Bias
Large Bias Current
Middle Bias Current
Small Bias Current
4V
1/5
300mA
100mA
40mA
4V
1/4
375mA
125mA
50mA
V D D
V D D
*
V L C D
*
V R
V L C D
R
V R
R
V 1
V 1
R
V 2
R
V 2
*V
R
*V
R
L C D
V 3
L C D
V 3
R
R
V 4
V 4
R
R
V S S
V S S
1 /5 b ia s
1 /4 b ia s
* T h e v o lta g e a p p lie d to V L C D p in m u s t b e e q u a l to o r lo w e r th a n V D D .
* A d ju s t V R to fit L C D d is p la y , a t V D D = 5 V , V L C D = 4 V , V R = 1 5 k W ± 2 0 % .
Internal Resistor Type Bias Generator Configurations
Interfacing
RD signal, and the clocked out data will then appear on
the DB0~DB3 lines. It is recommended that the host
controller read correct data during the interval between
the rising edge and the next falling edge of the RD signal.
The WR line is the WRITE clock input. The data, address, and command on the DB0~DB3 lines are all
clocked into the HT1647 on the rising edge of the WR
signal. There is an optional IRQ line to be used as an interface between the host controller and the HT1647.
The IRQ pin can be selected as a timer output or a WDT
overflow flag output by the S/W setting. The host controller can perform the time base or the WDT function by
connecting with the IRQ pin of the HT1647.
Only six lines are required to interface with the HT1647.
The CS line is used to initialize the serial interface circuit
and to terminate the communication between the host
controller and the HT1647. If the CS pin is set to 1, the
data and command issued between the host controller
and the HT1647 are first disabled and then initialized.
Before issuing a mode command or mode switching, a
high level pulse is required to initialize the serial interface of the HT1647. The DB0~DB3 are the 4-bit parallel
data input/output lines. Data to be read or written or
commands to be written have to pass through the
DB0~DB3 lines. The RD line is the READ clock input.
Data in the RAM are clocked out on the falling edge of the
Rev. 1.40
11
November 9, 2010
PATENTED
HT1647
Timing Diagrams
READ mode (command ID code : 1 1 0)
C S
W R
R D
A 8
A 7
A 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D B 2
1
A 6
A 2
D 2
1
A 6
A 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
A 5
A 1
D 1
A 5
A 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
0
A 4
A 0
D 0
0
A 4
A 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
C o m m a n d ID
A d d re s s (M A )
M e m o ry
D a ta (M A )
C o m m a n d ID
A d d re s s (M A )
M e m o ry
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
D a ta (M A + 9 )
D a ta (M A + 1 5 )
1
D B 1
D B 0
1
D a ta (M A + 1 0 )
D a ta (M A + 1 1 )
D a ta (M A + 1 2 )
D a ta (M A + 1 3 )
D a ta (M A + 1 4 )
A 7
A 3
D 3
A 8
A 7
A 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D B 2
1
A 6
A 2
D 2
1
A 6
A 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
A 5
A 1
D 1
A 5
A 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
A 4
A 0
D 0
1
A 4
A 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
M e m o ry
D a ta (M A )
C o m m a n d ID
A d d re s s (M A )
M e m o ry
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
D a ta (M A + 4 )
D a ta (M A + 5 )
D a ta (M A + 6 )
D a ta (M A + 7 )
D a ta (M A + 8 )
D a ta (M A + 9 )
D a ta (M A + 1 0 )
D a ta (M A + 1 1 )
D a ta (M A + 1 2 )
D a ta (M A + 1 3 )
D a ta (M A + 1 4 )
D a ta (M A + 1 5 )
c o d e
A 8
c o d e
D B 3
A d d re s s (M A )
D a ta (M A + 8 )
D 3
D a ta (M A + 7 )
A 3
D a ta (M A + 6 )
A 7
D a ta (M A + 5 )
A 8
D a ta (M A + 4 )
D B 3
( S in g le a d d r e s s r e a d in g )
( S u c c e s s iv e a d d r e s s r e a d in g )
WRITE mode (command ID code : 1 0 1)
C S
W R
R D
0
D B 1
1
D B 0
0
C o m m a n d ID
c o d e
c o d e
( S in g le a d d r e s s w r itin g )
Rev. 1.40
( S u c c e s s iv e a d d r e s s w r itin g )
12
November 9, 2010
PATENTED
HT1647
READ-MODIFY-WRITE mode (command ID code : 1 0 1)
C S
W R
R D
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D 3
D B 2
1
A 6
A 2
D 2
D 2
1
A 6
A 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D 2
D B 1
0
A 5
A 1
D 1
D 1
A 5
A 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D 1
D B 0
1
A 4
A 0
D 0
D 0
1
A 4
A 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
C o m m a n d ID c o d e
A d d re s s (M A )
M e m o ry
D a ta (M A )
D a ta (M A )
C o m m a n d ID c o d e
A d d re s s (M A )
M e m o ry
D a ta (M A )
D a ta (M A )
D a ta (M A + 5 )
D a ta (M A + 6 )
D a ta (M A + 6 )
C 8
C 4
C 0
0
( S in g le a d d r e s s a c c e s s in g )
D a ta (M A + 5 )
A 3
D a ta (M A + 4 )
A 7
D a ta (M A + 4 )
A 8
D a ta (M A + 3 )
D 3
D a ta (M A + 3 )
D 3
D a ta (M A + 2 )
A 3
D a ta (M A + 2 )
A 7
D a ta (M A + 1 )
A 8
D a ta (M A + 1 )
D B 3
( S u c c e s s iv e a d d r e s s a c c e s s in g )
Command mode (command ID code : 1 0 0)
C S
W R
R D
D B 3
X
C 8
1
D B 2
0
D B 1
D B 0
0
C 4
C 0
C 7
C 3
X
C 6
C 2
C 5
C 1
X
1
0
X
X
0
C 8
C 4
C 0
C 8
C 4
C 7
C 3
X
C 7
C 3
C 6
C 2
X
C 6
C 2
C 5
C 1
X
C 5
C 1
C 0
C 8
C 4
C 0
C 8
C 4
C 0
C 8
C 4
C 0
X
C 7
C 3
X
C 7
C 3
X
C 7
C 3
X
C 7
C 3
X
C 6
C 2
X
C 6
C 2
X
C 6
C 2
X
C 6
C 2
X
X
C 5
C 1
X
C 5
C 1
X
C 5
C 1
X
C 5
C 1
X
X
C o m m a n d 6
C o m m a n d 5
C o m m a n d 4
C o m m a n d 3
C o m m a n d 2
C o m m a n d 1
C o m m a n d ID
C o m m a n d
c o d e
C o m m a n d ID c o d e
( S in g le c o m m a n d )
( S u c c e s s iv e c o m m a n d )
Note: ²X² stands for don¢t care
Rev. 1.40
13
November 9, 2010
PATENTED
HT1647
Application Circuits
Host Controller with an HT1647 Display System
C S
*
V D D
R D
*V R
W R
D B 0 ~ D B 3
M C U
*R
V L C D
H T 1 6 4 7
B Z
P ie z o
IR Q
B Z
O S C I
C lo c k O u t
O S C O
C O M 0 ~ C O M 1 5
S E G 0 ~ S E G 6 3
E x te r n a l C lo c k 1 ( 3 2 k H z )
E x te r n a l C lo c k 2 ( 3 2 k H z )
* 1 /5 B ia s ( o r 1 /4 B ia s ) , 1 /1 6 D u ty
O n - c h ip O S C
L C D
P a n e l
C ry s ta l
3 2 7 6 8 H z
*Note: The connection of IRQ and RD pin can be selected depending on the MCU.
The voltage applied to VLCD pin must be equal to or lower than VDD.
Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW ± 20%.
It is recommended to select 1/5 bias to fit TN-type, STN-type LCDs and select 1/4 bias to fit ECB-type LCDs.
Adjust R (external pull high resistance) to fit user¢s time base clock.
Instruction Set Summary
Command Code
D/C
READ
Name
A8110-A7A6A5A4A3A2A1A0D3D2D1D0
D
Read data from the RAM
WRITE
A8101-A7A6A5A4A3A2A1A0D3D2D1D0
D
Write data to the RAM
READ-MODIFYA8101-A7A6A5A4A3A2A1A0D3D2D1D0
WRITE
D
Read and Write data to the RAM
SYS DIS
X100-0000-0000-XXXX
C
Turn Off both system oscillator and LCD bias
Yes
generator
SYS EN
X100-0000-0001-XXXX
C
Turn On system oscillator
LCD OFF
X100-0000-0010-XXXX
C
Turn Off LCD display
LCD ON
X100-0000-0011-XXXX
C
Turn On LCD display
TIMER DIS
X100-0000-0100-XXXX
C
Disable time base output
Yes
WDT DIS
X100-0000-0101-XXXX
C
Disable WDT time-out flag output
Yes
TIMER EN
X100-0000-0110-XXXX
C
Enable time base output
WDT EN
X100-0000-0111-XXXX
C
Enable WDT time-out flag output
TONE OFF
X100-0000-1000-XXXX
C
Turn Off tone outputs
CLR TIMER
X100-0000-1101-XXXX
C
Clear the contents of the time base generator
CLR WDT
X100-0000-1111-XXXX
C
Clear the contents of the WDT stage
TONE 4K
X100-0001-0000-XXXX
C
Turn on tone output, tone frequency output:
4kHz
TONE 2K
X100-0001-0001-XXXX
C
Turn on tone output, tone frequency output:
2kHz
Rev. 1.40
14
Function
Def.
Yes
Yes
November 9, 2010
PATENTED
Name
Command Code
D/C
HT1647
Function
Def.
IRQ DIS
X100-0001-0010-XXXX
C
Disable IRQ output
IRQ EN
X100-0001-0011-XXXX
C
Enable IRQ output
RC 32K
X100-0001-0100-XXXX
C
System clock source, on-chip RC oscillator
EXT (XTAL)
X100-0001-0101-XXXX
C
System clock source, external 32kHz clock
source or crystal oscillator 32.768kHz
LARGE BIAS
X100-0001-0110-XXXX
C
Large bias current option
MIDDLE BIAS
X100-0001-0111-XXXX
C
Middle bias current option
SMALL BIAS
X100-0001-1000-XXXX
C
Small bias current option
BIAS 1/5
X100-0001-1001-XXXX
C
LCD 1/5 bias option
BIAS 1/4
X100-0001-1010-XXXX
C
LCD 1/4 bias option
FRAME 170Hz
X100-0001-1100-XXXX
C
Selects 170Hz frame frequency and active
segment signal width can be divided into 13
sections
FRAME 89Hz
X100-0001-1101-XXXX
C
Selects 89Hz frame frequency and active
segment signal width can be divided into 24 Yes
sections
GRS LEVEL1
X100-001 B4-B3 B2 B1 B0-XXXX
C
Sets PWM data in gray scale level 1
GRS LEVEL2
X100-010 B4-B3 B2 B1 B0-XXXX
C
Sets PWM data in gray scale level 2
GRS LEVEL3
X100-011 B4-B3 B2 B1 B0-XXXX
C
Sets PWM data in gray scale level 3
GRS LEVEL4
X100-100 B4-B3 B2 B1 B0-XXXX
C
Sets PWM data in gray scale level 4
F1
X100-1010-0000-XXXX
C
Time base clock output: 1Hz
The WDT time-out flag after: 4s
F2
X100-1010-0001-XXXX
C
Time base clock output: 2Hz
The WDT time-out flag after: 2s
F4
X100-1010-0010-XXXX
C
Time base clock output: 4Hz
The WDT time-out flag after: 1s
F8
X100-1010-0011-XXXX
C
Time base clock output: 8Hz
The WDT time-out flag after: 1/2s
F16
X100-1010-0100-XXXX
C
Time base clock output: 16Hz
The WDT time-out flag after: 1/4s
F32
X100-1010-0101-XXXX
C
Time base clock output: 32Hz
The WDT time-out flag after: 1/8s
F64
X100-1010-0110-XXXX
C
Time base clock output: 64Hz
The WDT time-out flag after: 1/16s
F128
X100-1010-0111-XXXX
C
Time base clock output: 128Hz
The WDT time-out flag after: 1/32s
TEST
X100-1111-1111-XXXX
C
Test mode, user don¢t use.
NORMAL
X100-1111-1110-XXXX
C
Normal mode
Note:
Yes
Yes
Yes
Yes
Yes
Yes
²X² stands for don¢t care
A8~A0: RAM address
D3~D0: RAM data
B4~B0: PWM data
D/C: Data/Command mode
Def.: Power-on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command
mode ID. If successive commands have been issued, the command mode ID except for the first command will
be omitted. The tone frequency source and the time base/WDT clock frequency source can be derived from an
on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller
should initialize the HT1647 after power-on reset, otherwise, power on reset may fail, which in turn leads to the
malfunctioning of the HT1647.
Rev. 1.40
15
November 9, 2010
PATENTED
HT1647
Package Information
100-pin QFP (14mm´20mm) Outline Dimensions
C
H
D
8 0
G
5 1
I
5 0
8 1
F
A
B
E
3 1
1 0 0
K
a
J
1
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.728
¾
0.756
B
0.547
¾
0.555
C
0.965
¾
0.992
D
0.783
¾
0.791
E
¾
0.026
¾
F
¾
0.012
¾
G
0.098
¾
0.122
H
¾
¾
0.134
I
¾
0.004
¾
J
0.039
¾
0.055
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 1.40
3 0
Dimensions in mm
Min.
Nom.
Max.
A
18.50
¾
19.20
B
13.90
¾
14.10
C
24.50
¾
25.20
D
19.90
¾
20.10
E
¾
0.65
¾
F
¾
0.30
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.1
¾
J
1.00
¾
1.40
K
0.10
¾
0.20
a
0°
¾
7°
16
November 9, 2010
PATENTED
HT1647
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
17
November 9, 2010