PHILIPS HEF4007UBT Dual complementary pair and inverter Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4007UB
gates
Dual complementary pair and
inverter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Dual complementary pair and inverter
HEF4007UB
gates
DESCRIPTION
The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and
three p-channel enhancement mode MOS transistors.
Fig.1 Schematic diagram.
PINNING
Fig.2 Pinning diagram.
HEF4007UBP(N):
drain connections from the 1st and 2nd
p-channel transistors
DN1, DN2
drain connections from the 1st and 2nd
n-channel transistors
SN2, SN3
source connections to the 2nd and 3rd
n-channel transistors
DN/P3
common connection to the 3rd p-channel
and n-channel transistor drains
G1 to G3
gate connections to n-channel and
p-channel of the three transistor pairs
See Family Specifications for VIH/VIL unbuffered stages
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
January 1995
DP1, DP2
FAMILY DATA, IDD LIMITS category GATES
14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4007UBT(D):
source connections to 2nd and 3rd
p-channel transistors
14-lead DIL; plastic
(SOT27-1)
HEF4007UBD(F):
SP2, SP3
2
Philips Semiconductors
Product specification
HEF4007UB
gates
Dual complementary pair and inverter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYPICAL EXTRAPOLATION
FORMULA
TYP.
MAX.
40
80
ns
13 ns + (0,55 ns/pF) CL
20
40
ns
9 ns + (0,23 ns/pF) CL
15
30
ns
7 ns + (0,16 ns/pF) CL
40
75
ns
13 ns + (0,55 ns/pF) CL
20
40
ns
9 ns + (0,23 ns/pF) CL
15
30
ns
7 ns + (0,16 ns/pF) CL
Propagation delays
Gn → DN ; DP
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
Output transition times
HIGH to LOW
5
60
120
ns
10 ns + (1,0 ns/pF) CL
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
60
120
ns
10 ns + (1,0 ns/pF) CL
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
VDD
V
TYPICAL FORMULA FOR P (µW)
10
tTHL
15
5
LOW to HIGH
Dynamic power
10
5
tTLH
4500 fi + ∑ (foCL) × VDD2
dissipation per
10
20 000 fi + ∑ (foCL) ×
package (P)
15
50 000 fi + ∑ (foCL) ×
VDD2
VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
Philips Semiconductors
Product specification
Dual complementary pair and inverter
Fig.3
Typical drain current ID and output voltage VO as
functions of input voltage; VDD = 5 V; Tamb = 25 °C.
Fig.4
Typical drain current ID and output voltage VO as
functions of input voltage; VDD = 10 V; Tamb = 25 °C.
Fig.5
January 1995
HEF4007UB
gates
4
Typical drain current ID and output voltage VO as
functions of input voltage; VDD = 15 V; Tamb = 25 °C.
Philips Semiconductors
Product specification
HEF4007UB
gates
Dual complementary pair and inverter
APPLICATION INFORMATION
Some examples of applications for the HEF4007UB are:
• High input impedance amplifiers
• Linear amplifiers
• (Crystal) oscillators
• High-current sink and source drivers
• High impedance buffers.
Fig.6
Voltage gain (Vo/Vi) as a function of supply
voltage.
Fig.7
This is also an example of an
analogue amplifier using one
HEF4007UB gate.
Fig.8
Test set-up for measuring graphs of Figs 6
and 7.
January 1995
5
Supply current as a function of supply
voltage.
Philips Semiconductors
Product specification
Dual complementary pair and inverter
HEF4007UB
gates
Fig.9 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also graph Fig.10).
A: average,
B: average + 2 s,
C: average − 2 s, in where ‘s’ is the observed standard deviation.
Fig.10 Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 °C.
January 1995
6
Philips Semiconductors
Product specification
Dual complementary pair and inverter
Figures 11 to 14 show some applications in which the HEF4007UB is used.
Fig.11 4 MHz crystal oscillator.
Fig.12 High current sink driver.
Fig.13 High current source driver.
January 1995
7
HEF4007UB
gates
Philips Semiconductors
Product specification
HEF4007UB
gates
Dual complementary pair and inverter
FUNCTION TABLE for Fig.14.
INPUT
DISABLE
OUTPUT
H
L
L
L
L
H
X
H
open
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
NOTE
Rules for maintaining electrical isolation between
transistors and monolithic substrate:
• Pin number 14 must be maintained at the most positive
(or equally positive) potential with respect to any other
pin of the HEF4007UB.
• Pin number 7 must be maintained at the most negative
(or equally negative) potential with respect to any other
pin of the HEF4007UB.
Violation of these rules will result in improper transistor
operation and/or possible permanent damage to the
HEF4007UB.
Fig.14 High impedance buffer.
January 1995
8
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