Micro Linear ML6423CS-2 Dual s-video lowpass filter with phase and sinx/x equalization Datasheet

June 1999
PRELIMINARY
ML6423*
Dual S-Video Lowpass Filter with
Phase and Sinx/x Equalization
GENERAL DESCRIPTION
FEATURES
The ML6423 monolithic BiCMOS 6th-order filter provides
a two-channel fixed frequency lowpass filtering for video
applications. This dual phase equalized filter with sinx/x
correction is designed for reconstruction filtering at the
output of a Video DAC. A composite sum output
eliminates the need for a third DAC.
■ 5.5 or 9.6MHz bandwidth with 6dB gain
Cutoff frequencies are either 5.5MHz or 9.6MHz. Each
channel incorporates a 6th-order lowpass filter, a first
order allpass filter, a gain boost circuit, and a 75W coax
cable driver. A control pin (RANGE) is provided to allow
the inputs to swing from 0 to 1V, or 0.5 to 1.5V, by
providing a 0.5V offset to the input.
The 2X gain filters are powered from a single 5V supply,
and can drive 1VP-P into 75W (0.5V to 1.5V), or 2VP-P into
150W (0.5V to 2.5V) with the internal coax drivers.
■ >40dB stopband rejection
■ No external components or clocks
■ ±10% frequency accuracy over maximum supply
and temperature variation
■ <2% differential gain, <2° differential phase
■ <20ns group delay variation
■ 5V ±10% operation
■ Composite (sum) output
■ High sink current for AC coupled loads, ML6423-5
* This Product Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
10
7
4
13
VCCB
VCCC
VCC
VCCA
VOUTA (Y)
VINA (Y)
16
LOWPASS
FILTER A
BUF
ALLPASS
FILTER
SINX/X
EQUALIZER
2X
BUF
2kΩ
12
3.43kΩ
IBIAS
2kΩ
∑
15 RANGE
2X
BUF
VOUTB (CV)
8
3.43kΩ
VINC (C)
1
LOWPASS
FILTER C
BUF
ALLPASS
FILTER
SINX/X
EQUALIZER
2X
BUF
2kΩ
VOUTC (C)
6
3.43kΩ
IBIAS
2kΩ
GND
GNDA
2
14
Filter A
Filter C
ML6423-1
5.50MHz
5.50MHz
GNDC
3
ML6423-2
9.6MHz
9.6MHz
GNDB
9
ML6423-5
9.6MHz
9.6MHz
1
ML6423
PIN CONFIGURATION
ML6423
16-Pin Wide SOIC (S16W)
VINC
1
16
VINA
GND
2
15
RANGE
GNDC
3
14
GNDA
VCC
4
13
VCCA
NC
5
12
VOUTA
VOUTC
6
11
NC
VCCC
7
10
VCCB
VOUTB
8
9
GNDB
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
PIN
NAME
FUNCTION
1
VINC
Signal input to filter C. Input
impedance is 4kW.
10
VCCB
Power supply voltage for output B.
11
NC
No Connect
2
GND
Power and logic ground.
12
3
GNDC
Ground pin for filter C.
VOUTA
Output of filter A. Drive is 1VP-P into
75W (0.5V to 1.5V) or 2VP-P into 150W
(0.5V to 2.5V).
4
VCC
Positive supply: 4.5V to 5.5V.
13
NC
No Connect
VCCA
Power supply voltage for filter A.
5
14
GNDA
Ground pin for filter A.
6
VOUTC
Output of filter C. Drive is 1VP-P into
75W (0.5V to 1.5V) or 2VP-P into 150W
(0.5V to 2.5V).
15
RANGE
7
VCCC
Power supply voltage for filter C.
8
VOUTB
Sum of Filter A and Filter C. Drive is
1VP-P into 75W (0.5V to 1.5V) or 2VP-P
into 150W (0.5V to 2.5V).
Input signal range select. When
RANGE is low (0), the input signal
range is 0.5V to 1.5V, with an output
range of 0.5V to 2.5V. When RANGE
is high (1) the input signal range is 0V
to 1V, while the output range is 0.5V
to 2.5V.
16
9
GNDB
Ground pin for output B.
VINA
Signal input to filter A. Input
impedance is 4kW.
2
ML6423
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.
Storage Temperature .................................. –65° to 150°C
Lead Temperature (Soldering 10 sec) ..................... 150°C
Thermal Resistance (qJA) ..................................... 65°C/W
Supply Voltage (VCC) ...................................... –0.3 to 7V
GND .................................................. –0.3 to VCC +0.3V
Logic Inputs ........................................ –0.3 to VCC +0.3V
Input Current per Pin ............................................ ±25mA
Supply Voltage ................................................. 5V ±10%
Temperature Range ...................................... 0°C to 70°C
OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
Unless otherwise specified VCC = 5V ± 10%, RL =75W or 150W, VOUT = 2VP-P for 150W Load and VOUT = 1VP-P for 75W
Load, TA = Operating Temperature Range (Notes 1, 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
3k
4
5
kW
±2
%
GENERAL
RIN
Input Impedance
DR/RIN
Input R Matching
IBIAS
Input Current
VIN = 0.5V, RANGE = low
VIN = 0.0V, RANGE = high
Differential Gain
Differential Phase
V IN
CL
Input Range
45
–210
µA
µA
VIN = 0.8V to 1.5V
at 3.58 & 4.43 MHz
1
%
VIN = 0.8V to 1.5V
at 3.58 & 4.43 MHz
1
deg
RANGE = Low
0.5
1.5
V
RANGE = High
0.0
1.0
V
Peak Overshoot
2T, 0.7VP-P pulse
2.0
Crosstalk Rejection
fIN = 3.58, fIN = 4.43MHz
Channel to Channel
Group Delay Matching
(fC = 5.5MHz)
fIN = 100kHz
±3
ns
Channel to Channel
Gain Matching
fIN = 100kHz
±1.5
%
Output Current
RL = 0 (short circuit)
75
mA
45
dB
Load Capacitance
Composite Chroma/Luma delay
%
35
pF
fC = 5.5MHz
±15
ns
fC = 9.6MHz
±8
ns
5.50MHZ FILTER
Bandwidth (monotonic passband)
–0.55dB (Note 4)
4.95
5.50
6.05
MHz
Subcarrier Frequency Gain
fIN = 3.58MHz
0.9
1.4
2.3
dB
ML6423-1
fIN = 4.43MHz
1.1
1.6
2.5
dB
Attenuation
fIN = 10MHz
20
25
dB
fIN = 50MHz
45
55
dB
Output Noise
Group Delay
BW = 30MHz
1
180
mVRMS
ns
3
ML6423
ELECTRICAL CHARACTERISTICS
SYMBOL
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.50MHZ FILTER (Continued)
Small Signal Gain
VIN = 100mVP-P at 100kHz,
Filter A or C
5.5
6
6.5
dB
Composite (CV) Small Signal Gain
VINA, C = 100mVP-P at 100kHz
11
12
13
dB
Bandwidth (monotonic passband)
–2dB (Note 4)
8.6
9.6
10.6
MHz
Subcarrier Frequency Gain
fIN = 3.58MHz
–0.1
0.4
1.1
dB
ML6423-2
fIN = 4.43MHz
–0.1
0.6
1.3
dB
Subcarrier Frequncy Gain
fIN = 3.58MHz
–0.1
0.4
1.9
dB
ML6423-5
fIN = 4.43MHz
–0.1
0.6
1.1
dB
Attenuation
fIN = 17MHz
20
25
dB
fIN = 85MHz
45
55
dB
9.6MHZ FILTER
Output Noise
BW = 30MHz
1
mVRMS
100
ns
12
13
dB
Group Delay
I CC
Composite (CV) Small Signal Gain
VINA, C = 100mVP-P at 100kHz
11
ML6423-5 Supply Current RL = 150W
VIN = 0.5V (Note 5)
140
175
mA
VIN = 1.5V
170
215
mA
ML6423-5 VOUTA, VOUTB sink current
VIN = 0.5V
8.3
11.5
mA
ML6423-5 VOUTC sink current
VIN = 0.5V
4.3
6.5
mA
ML6423-5 Output DC Level
VIN = 0.5V, Range = Low
0.5
V
DIGITAL AND DC
VIL
Logic Input Low
Range
VIH
Logic Input High
Range
IIL
Logic Input Low
VIN = GND
IIL
Logic Input High
VIN = VCC
ICC
Supply Current RL = 150W
VIN = 0.5V (Note 5)
VIN = 1.5V
Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
Note 2: Maximum resistance on the outputs is 500W in order to improve step response.
Note 3: Connect all ground pins to the ground plane via the shortest path.
Note 4: The bandwidth is the –3dB frequency of the unboosted filter. This represents the attenuation that results from
boosting the gain from the –3dB point at the specified frequency.
Note 5: Power dissipation: PD = (ICC ´ VCC) – [3(VOUT2/RL)]
4
0.8
V
VCC – 0.8
V
–1
µA
1
µA
110
135
mA
140
175
mA
16
16
6
6
–4
–4
–14
–14
AMPLITUDE (dB)
AMPLITUDE (dB)
ML6423
–24
–34
–44
–24
–34
–44
–54
–54
–64
–64
–74
–74
–84
100K
1M
10M
FREQUENCY (Hz)
–84
100K
100M
Figure 1a. Stop-Band Amplitude vs. Frequency
(fC = 5.5MHz)
1M
10M
FREQUENCY (Hz)
100M
Figure 1b. Stop-Band Amplitude vs. Frequency
(fC = 9.6MHz)
7.5
7.5
7.0
7.0
6.5
6.5
ML6423-2
ML6423-1
5.5
5.0
4.5
ML6422-2
5.5
5.0
4.5
4.0
4.0
3.5
3.5
3.0
3.0
2.5
100K
1M
FREQUENCY (Hz)
2.5
100K
5.5MHz 10M
1M
FREQUENCY (Hz)
5.5MHz 10M
Figure 2a. Pass-Band Amplitude vs. Frequency
(fC = 5.5MHz)
Figure 2b. Pass-Band Amplitude vs. Frequency
(fC = 9.6MHz)
220
130
200
125
180
120
160
115
GROUP DELAY (ns)
GROUP DELAY (ns)
6.0
AMPLITUDE (dB)
AMPLITUDE (dB)
6.0
140
120
100
110
105
100
80
95
60
90
40
85
20
100K
5.5MHz
FREQUENCY (Hz)
Figure 3a. Group Delay vs. Frequency
(fC = 5.5MHz)
10MHz
80
100K
5M
FREQUENCY (Hz)
9.3M 10M
Figure 3b. Group Delay vs. Frequency
(fC = 9.6MHz)
5
ML6423
FUNCTIONAL DESCRIPTION
APPLICATION GUIDELINES
The ML6423 single-chip dual video filter is intended for
low cost professional and consumer video applications.
Each of the two channels incorporates an input buffer
amplifier, a 6th-order lowpass filter, a 1st-order allpass
equalizer, sinx/x equalizer and an output 2X gain
amplifier capable of driving 75W to ground. A third
output (B) is the sum of the A and C inputs and have the
identical output amplifier as the A and C channels.
OUTPUT & INPUT CONSIDERATIONS
The ML6423 can be driven by a DAC with RANGE down
to 0V. When RANGE is low the input range is 0.5V to
1.5V. When the input signal range is 0V to 0.1V, RANGE
should be tied high. In this case, an offset is added to the
input so that the output swing is kept between 0.5V to
2.5V. The output amplifier is capable of driving up to
24mA of peak current; therefore the output voltage should
not exceed 1.8V when driving 75W to ground.
The dual filters have 2X gain. The circuit has 2X gain
(6dB) when connected to a 150W load, and 0dB gain
when driving a 75W load via a 75W series output resistor.
The output may be either AC or DC coupled. For AC
coupling, the –3dB point should be 5Hz or less. There
must also be a DC path of £500W to ground for output
biasing. The ML6423-5 provides higher sink current to
better drive AC coupled loads.
The input resistance is 4kW. The input may be either DC
or AC coupled. (Note that each input sources 80 to 125µA
of bias current). The ML6423 is designed to be directly
driven by a DAC. For current output video DACs, a 75W
or 150W resistor to ground may need to be added to the
DAC output (filter input).
SUPPLY NOISE
CLAMPING
+5V
FB2
+
0.1µF
1nF
1µF
INPUT
DECOUPLING
0.1µF
VINC
+
100µF
INPUT SIGNAL
= 1VP-P
85Ω
100Ω
100Ω
100µF
1
DC
BIAS
VINC
VINA
16
1k
2
1nF 3
0.1µF
VOUTC
4
6
75Ω
0.1µF 7
1nF
8
GND
GNDC
VCC
NC
VOUTC
VCCC
VOUTB
RANGE
GNDA
VCCA
VOUTA
NC
VCCB
GNDB
15
14 0.1µF
13
1nF
12
75Ω
11
10 0.1µF
9
1nF
75Ω
Figure 4. ML6423 AC Coupled DC Bias Test Circuit
6
VINA
0.1µF
1kΩ
5
VOUTB
100µF
+
85Ω
2.56kΩ
INPUT
TERMINATION
RESISTOR
FB1
1µF
2.56kΩ
VOUTA
ML6423
APPLICATION GUIDELINES (Continued)
LAYOUT CONSIDERATIONS
In order to obtain full performance from these dual filters,
layout is very important. Good high frequency decoupling
is required between each power supply and ground.
Otherwise, oscillations and/or excessive crosstalk may
occur. A ground plane is recommended.
Each filter has its own supply and ground pins. In the test
circuit, 0.1µF capacitors are connected in parallel with
1nF capacitors on all VCC pins for maximum noise
rejection (Figure 4).
Further noise reduction is achieved by using series ferrite
beads. In typical applications, this degree of bypassing
may not be necessary.
Since there are two filters and a sum output driver in one
package, space the signal leads away from each other as
much as possible.
Composite: When one or more composite signals need to
be filtered, then the 5.5MHz and 9.6MHz filters permit
filtering of one, two, or three composite signals.
Over Sampling: While the ML6423 filters can eliminate
the need for over sampling combined with digital
filtering, there are times when over sampling is used. For
these situations, 9.3MHz could be used in place of
5.5MHz.
NTSC/PAL: A 5.5MHz cutoff frequency provides good
filtering for 4.2MHz, 5.0MHz and 5.5MHz signals
without the need to change filters on a production basis.
Sinx/x: For digital video system with output D/A
converters, there is a fall off in response with frequency
due to discrete sampling. The fall off follows a sinx/x
response (Figure 5a). The ML6423 filters have a
complementary boost to provide a flatter overall
response. The boost is designed for 13.5MHz Y/C and CV
sampling and 6.75MHz U/V sampling.
POWER CONSIDERATIONS
The ML6423 power dissipation follows the formula:
PD = (ICC ™ VCC ) -
V
! RL
OUT
2
"#
#$
™3
This is a measure of the amount of current the part sinks
(current in – current out to the load).
In a typical application (Figure 5b) the ML6423 is used as
the final output device in a video processing chain. In this
case, inputs to the ML6423 are supplied by DAC outputs
with their associated load resistors (typically 75W or
150W). Resistance values should be adjusted to provide
1VP-P at the input of the ML6423. The ML6423 will drive
75W source termination resistors (making the total load
150W) so that no external drivers or amplifiers are
required.
Under worst case conditions:
PD = (0.175 ™ 5.5) -
4
15. ™ 3 "# = 8725. mW
! 75 #$
THEORETICAL SINX/X
CORRECTION FOR
13.5MHz SAMPLING
2
2
The ML6423 provides several choices in filter cutoff
frequencies depending on the application.
S-Video: For Y/C (S-video) and Y/C + CV (Composite
Video) systems the 5.5MHz or 9.6MHz filters are
appropriate. In NTSC the C signal occupies the
bandwidth from about 2.6MHz to about 4.6MHz, while
in PAL the C signal occupies the bandwidth from about
3.4MHz to about 5.4MHz. In both cases, a 5.5MHz
lowpass filter provides adequate rejection for both
sampling and reconstruction. In addition, using the same
filter for both Y/C and CV maintains identical signal
timing without adjustments.
AMPLITUDE
FILTER SELECTION
0
–2
SINX/X ERROR FOR
TYPICAL DAC AT 13.5MHz
–4
0
1
2
3
4
5
FREQUENCY (MHz)
6
7
Figure 5a. Sinx/x Frequency Response
7
ML6423
10
IDEAL SINX/X RESPONSE
0
–3dB REFERENCE MARKER
AMPLITUDE (dB)
–10
A. ML6423 AMPLITUDE RESPONSE
–20
B. SIGNAL DISTORTION SPECTRUM
–30
C. RECONSTRUCTED SIGNAL
SPECTRUM
–40
–50
–60
0
5
10
15
20
25
FREQUENCY (MHz)
Figure 6. ML6423 Reconstruction Performance in the Frequency Domain
FILTER PERFORMANCE
The reconstruction performance of a filter is based on its
ability to remove the high band spectral artifacts that
result from the sampling process without distorting the
valid signal spectral contents within the passband. For
video signals, the effect of these artifacts is a variation of
the amplitude of small detail elements in the picture
(such as highlights or fine pattern details) as the elements
move relative to the sampling clock. The result is similar
to the aliasing problem and causes a “winking” of details
as they move in the picture.
+5V
DAC
INPUTS
Y
DAC
(CURRENT SOURCING
ML6423
75Ω
+
C
DAC
(CURRENT SOURCING
ANALOG
OUTPUTS
Y
CV
75Ω
C
75Ω
DAC LOAD
ADJUSTED FOR
1VP-P
Figure 5b. Typical ML6423 Reconstruction Application
8
Figure 6 shows the problem in the frequency domain.
Curve A shows the amplitude response of the ML6423
filter, while curve B shows the signal spectrum as it is
distorted by the sampling process. Curve C shows the
composite of the two curves which is the result of passing
the sampled waveform through the ML6423. It is clear
that the distortion artifacts are reduced significantly.
Ultimately it is the time domain signal that is viewed on a
TV monitor, so the effect of the reconstruction filter on
the time domain signal is important. Figure 7 shows the
sampling artifacts in the time domain. Curve A is the
original signal, curve B is the result of CCIR601 sampling,
and curve C is the same signal filtered through the
ML6423. Again the distortions in the signal are essentially
removed by the filter.
In an effort to measure the time domain effectiveness of a
reconstruction filter, Figure 8 was generated from a swept
frequency waveform. Curves A, B, and C are generated as
in Figure 7, but additional curves D and E help quantify
the effect of filtering in the time domain. Curves D and E
represent the envelopes (instantaneous amplitudes) of
curves B and C. Again, it is evident in curve D that the
envelope varies significantly due to the sampling process.
In curve E, filtering with the ML6423 removes these
artifacts and generates an analog output signal that rivals
the oversampled (and more ideal) signal waveforms. The
ML6423 reduces the amplitude variation from over 6% to
less than 1%.
ML6423
A. OVERSAMPLED
WAVEFORMS
B. CCIR601 SAMPLED
WAVEFORMS
C. ML6423
RECONSTRUCTED
WAVEFORMS
Figure 7. ML6423 Reconstruction Performance in the Time Domain
A. OVERSAMPLED
SIGNAL
B. CCIR601 SAMPLED
SIGNAL
C. ML6423 FILTERED
SIGNAL
D. CCIR601 SAMPLED
WAVEFORM
>6%
E. ML6423 FILTERED
WAVEFORM
<1%
Figure 8. Amplitude Ripple of Reconstructed Swept Pulses
9
ML6423
PHYSICAL DIMENSIONS inches (millimeters)
Package: S16W
16-Pin Wide SOIC
0.400 - 0.414
(10.16 - 10.52)
16
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.090 - 0.094
(2.28 - 2.39)
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE
0.005 - 0.013
(0.13 - 0.33)
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
ORDERING INFORMATION
PART NUMBER
BW (MHZ)
TEMPERATURE RANGE
PACKAGE
ML6423CS-1 (EOL)
ML6423CS-2 (EOL)
ML6423CS-5 (Obsolete)
5.5/5.5
9.6/9.6
9.6/9.6
0°C to 70°C
0°C to 70°C
0°C to 70°C
16-pin Wide SOIC (S16W)
16-pin Wide SOIC (S16W)
16-pin Wide SOIC (S16W)
© Micro Linear 2000.
property of their respective owners.
is a registered trademark of Micro Linear Corporation. All other trademarks are the
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116;
5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376;
5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174;
5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223;
5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents
of this publication and reserves the right to make changes to specifications and product descriptions at any time without
notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted
by this document. The circuits contained in this document are offered as possible applications only. Particular uses or
applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged
to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including
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www.microlinear.com
10
DS6423-01
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