ON ASM1232LPSF 5 v p power supply monitor and reset circuit Datasheet

ASM1232LP, ASM1232LPS
5 V mP Power Supply
Monitor and Reset Circuit
Description
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5 V Supply Monitor
Selectable Watchdog Period
Debounce Manual Push−button Reset Input
Precision Temperature−compensated Voltage Reference and
Comparator
Power−up, Power−down and Brown Out Detection
250 ms Minimum Reset Time
Active LOW Open Drain Reset Output and Active HIGH Push−pull
Output
Selectable Trip Point Tolerance: 5% or 10%
Low−cost Surface Mount Packages: 8−pin/16−pin SO, 8−pin DIP and
8−pin Micro SO Packages
Wide Operating Temperature −40°C to +85°C (N Suffixed Devices)
Applications
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August, 2011 − Rev. 3
MICRO−8
U SUFFIX
CASE 846AA
SOIC−8
S SUFFIX
CASE 751BD
SOIC−16
S SUFFIX
CASE 751BG
PIN CONFIGURATIONS
1
VCC
PBRST
TD
TOL
GND
NC
DIP/SO/MicroSO
(Top View)
1
NC
TD
NC
TOL
ST
RESET
RESET
NC
VCC
PBRST
NC
Microprocessor Systems
Computers
Controllers
Portable Equipment
Intelligent Instruments
Automotive Systems
© Semiconductor Components Industries, LLC, 2011
PDIP−8
P SUFFIX
CASE 646AA
ASM1232LP
ASM1232LPS−2
ASM1232LPU
Features
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ASM1232LPS
The ASM1232LP/LPS is a fully integrated microprocessor
Supervisor. It can halt and restart a “hung−up” microprocessor, restart
a microprocessor after a power failure. It has a watchdog timer and
external reset override.
A precision temperature−compensated reference and comparator
circuits monitor the 5 V, VCC input voltage status. During power−up or
when the VCC power supply falls outside selectable tolerance limits,
both RESET and RESET become active. When VCC rises above the
threshold voltage, the reset signals remain active for an additional
250 ms minimum, allowing the power supply and system
microprocessor to stabilize. The trip point tolerance signal, TOL,
selects the trip level tolerance to be either 5% or 10%.
Each device has both a push−pull, active HIGH reset output and an
open drain active LOW reset output. A debounced manual reset input,
PBRST, activates the reset outputs for a minimum period of 250 ms.
There is a watchdog timer to stop and restart a microprocessor that is
“hung−up”. The watchdog timeouts periods are selectable: 150 ms,
610 ms and 1200 ms. If the ST input is not strobed LOW before the
time−out period expires, a reset is generated.
Devices are available in 8−pin DIP, 16−pin SO and compact 8−pin
MicroSO packages.
NC
ST
NC
RESET
NC
GND
RESET
SO
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
1
Publication Order Number:
ASM1232LP/D
ASM1232LP, ASM1232LPS
Figure 1. Typical Operating Circuit
Figure 2. Block Diagram
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ASM1232LP, ASM1232LPS
Table 1. PIN DESCRIPTION
Pin #
8−Pin Package
Pin #
16−Pin Package
Pin
Name
1
2
PBRST
2
4
TD
Watchdog time delay selection. (tTD = 150 ms for TD = GND, tTD = 610 ms
for TD = Open, and tTD = 1200 ms for TD = VCC).
3
6
TOL
Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC) trip
point tolerance.
4
8
GND
Ground.
5
9
RESET
Active HIGH reset output. RESET is active:
1. If VCC falls below the reset voltage trip point.
2. If PBRST is LOW.
3. If ST is not strobed LOW before the timeout period set by TD expires.
4. During power−up.
6
11
RESET
Active LOW reset output. (See RESET).
7
13
ST
Strobe input.
8
15
VCC
5 V power.
1,3,5,7,10,12,14,16
NC
No internal connection.
Function
Debounced manual pushbutton RESET input.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Unit
Voltage on VCC (Note 1)
−0.5
7
V
Voltage on ST, TD (Note 1)
−0.5
VCC + 0.5
V
Voltage on PBRST, RESET, RESET (Note 1)
−0.5
VCC + 0.5
V
Operating Temperature Range (N suffixed devices)
−40
+85
°C
Operating Temperature Range (others)
0
70
°C
+260
°C
+125
°C
HBM
2
KV
MM
200
V
Soldering Temperature (for 10 sec)
Storage Temperature
ESD rating
−55
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Voltages are measured with respect to ground
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ASM1232LP, ASM1232LPS
Table 3. DC ELECTRICAL CHARACTERISTICS (Unless otherwise stated, 4.5 V ≤ VCC ≤ 5.5 V and over the operating
temperature range of 0°C to 70°C (−40°C to +85°C. for N devices). All Voltages are referenced to ground.)
Max
Unit
Supply Voltage
VCC
4.5
5.5
V
ST and PBRST Input High Level
VIH
2
VCC + 0.3
V
ST and PBRST Input Low Level
VIL
−0.3
0.8
V
VCC Trip Point (TOL = GND)
VCCTP
4.50
4.62
4.74
V
VCC Trip Point (TOL = VCC)
VCCTP
4.25
4.37
4.49
V
Watchdog Timeout Period
tTD
TD = GND
62.5
150
250
ms
Watchdog Timeout Period
tTD
TD = VCC
500
1200
2000
ms
Watchdog Timeout Period
tTD
TD Floating
250
610
1000
ms
Output Voltage
VOH
I = −500 mA
(Note 4)
VCC − 0.5
VCC − 0.1
V
Output Current
IOH
Output = 2.4 V
(Note 3)
−8
−10
mA
Output Current
IOL
Output = 0.4 V
10
Input Leakage
IIL
(Note 2)
−1.0
VOL
(Note 4)
Parameter
RESET Low Level
Symbol
Internal Pull−up Resistor
Conditions
Min
(Note 2)
Typ
mA
1.0
mA
0.4
V
40
kW
Operating Current (CMOS)
ICC1
30
mA
Input Capacitance
CIN
5
pF
COUT
10
pF
Output Capacitance
PBRST Manual Reset
Minimum Low Time
tPB
Reset Active Time
tRST
ST Pulse Width
tST
VCC Fail Detect to RESET or RESET
VCC Slew Rate
PBRST = VIL
ms
20
250
(Note 5)
tPDLY
VCC Detect to RESET or RESET inactive
tRPU
tRISE = 5 ms
250
tR
4.25 V to 4.75 V
0
VCC Slew Rate
8
300
PBRST Stable LOW to RESET and
RESET Active
ms
ns
5
4.75 V to 4.25 V
1000
20
tRPD
tF
610
ms
ms
610
20
ms
1000
ms
ns
2. PBRST is internally pulled HIGH to VCC through a nominal 40 kW resistor.
3. RESET is an open drain output.
4. RESET remains within 0.5 V of VCC on power−down until VCC falls below 2 V. RESET remains within 0.5 V of ground on power−down until
VCC falls below 2.0 V.
5. Must not exceed the minimum watchdog time−out period (tTD). The watchdog circuit cannot be disabled. To avoid a reset, ST must be strobed.
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ASM1232LP, ASM1232LPS
Detailed Description
Trip Point Tolerance Selection
The ASM1232LP/LPS monitors the microprocessor or
micro controller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
The TOL input is used to determine the level VCC can vary
below 5 V without asserting a reset. With TOL connected to
VCC, RESET and RESET become active whenever VCC
falls below 4.5 V. RESET and RESET become active when
the VCC falls below 4.75 V if TOL is connected to ground.
After VCC has risen above the trip point set by TOL,
RESET and RESET remain active for a minimum time
period of 250 ms. On power−down, once VCC falls below the
reset threshold RESET stays LOW and is guaranteed to be
0.4 V or less until VCC drops below 1.2 V. The active HIGH
reset signal is valid down to a VCC level of 1.2 V also.
RESET and RESET outputs
RESET is an active HIGH signal developed by a CMOS
push−pull output stage and is the logical opposite to RESET.
RESET is an active LOW signal. It is developed with an
open drain driver. A pull up resistor of typical value 10 kW
to 50 kW is required to connect with the output.
TRIP Point Voltage (V)
Tolerance
Min
Nom
Max
TOL = VCC
10%
4.25
4.37
4.49
TOL = GND
5%
4.5
4.62
4.74
Tolerance Select
Figure 3. Timing Diagram: Power Up
Figure 4. Timing Diagram: Power Down
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ASM1232LP, ASM1232LPS
Application Information
When PBRST is held LOW for the minimum time tPB,
both resets become active and remain active for a minimum
time period of 250 ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20 ms. No external pull−up resistor is required,
since PBRST is pulled HIGH by an internal 40 kW resistor.
The PBRST can be driven from a TTL or CMOS logic line
or shorted to ground with a mechanical switch.
Manual Reset Operation
Push−button switch input, PBRST, allows the user to
override the internal trip point detection circuits and issue
reset signals. The pushbutton input is debounced and is
pulled HIGH through an internal 40 kW resistor.
Figure 5. Timing Diagram: Pushbutton Reset
Figure 6. Application Circuit: Pushbutton Reset
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ASM1232LP, ASM1232LPS
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that
is “hung−up”. The mP must toggle the ST input within a set
period (as selectable through TD input) to verify proper
software execution. If the ST is not toggled low within the
minimum timeout period, reset signals become active. In
power−up after the supply voltage returns to an in−tolerance
condition, the reset signal remains active for 250 ms
minimum, allowing the power supply and system
microprocessor to stabilize. ST pulses as short as 20 ns can
be detected.
Figure 7. Timing Diagram: Strobe Input
Timeouts periods of approximately 150 ms, 610 ms or 1,200 ms are selected through the TD pin.
Watchdog Time−out Period (ms)
Min
Nom
Max
GND
62.5
150
250
Floating
250
610
1000
VCC
500
1200
2000
TD Voltage level
The watchdog timer cannot be disabled. It must be strobed with a high−to−low transition to avoid watchdog timeout and reset.
Figure 8. Application Circuit: Watchdog Timer
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ASM1232LP, ASM1232LPS
PACKAGE DIMENSIONS
Micro8t/TSSOP8 3x3
CASE 846AA−01
ISSUE O
D
HE
PIN 1 ID
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
E
e
b 8 PL
0.08 (0.003)
T B
M
S
A
DIM
A
A1
b
c
D
E
e
L
HE
S
SEATING
−T− PLANE
0.038 (0.0015)
A
A1
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
MIN
−−
0.05
0.25
0.13
2.90
2.90
L
c
SOLDERING FOOTPRINT*
8X
1.04
0.041
0.38
0.015
3.20
0.126
6X
8X
4.24
0.167
0.65
0.0256
5.28
0.208
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.016
0.021
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
ASM1232LP, ASM1232LPS
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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ASM1232LP, ASM1232LPS
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
E1
E
MIN
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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ASM1232LP, ASM1232LPS
PACKAGE DIMENSIONS
SOIC−16, 150 mils
CASE 751BG−01
ISSUE O
SYMBOL
E1
E
MIN
NOM
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
D
9.80
9.90
10.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
0.25
1.27 BSC
e
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
PIN#1 IDENTIFICATION
TOP VIEW
D
h
q
A
e
b
A1
c
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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ASM1232LP, ASM1232LPS
Table 4. ORDERING INFORMATION
Package
Operating
Temperature
Range
Maximum
Supply
Current (mA)
Voltage
Monitoring
Application
Package Marking
ASM1232LP
8L PDIP
0°C to +70°C
30
5V
ASM1232LP
ASM1232LPN
8L PDIP
−40°C to +85°C
30
5V
ASM1232LPN
Part Number (Note 6)
TIN−LEAD DEVICES
ASM1232LPS
16L SOIC
0°C to +70°C
30
5V
ASM1232LPS
ASM1232LPS−2
8L SOIC
0°C to +70°C
30
5V
ASM1232LPS−2
ASM1232LPSN
16L SOIC
−40°C to +85°C
30
5V
ASM1232LPSN
ASM1232LPSN−2
8L SOIC
−40°C to +85°C
30
5V
ASM1232LPSN−2
ASM1232LPU
8L MSOP
0°C to +70°C
30
5V
ASM1232LP
ASM1232LPUN
8L MSOP
−40°C to +85°C
30
5V
ASM1232LPN
ASM1232LPF
8L PDIP
0°C to +70°C
30
5V
ASM1232LPF
ASM1232LPNF
8L PDIP
−40°C to +85°C
30
5V
ASM1232LPNF
ASM1232LPS−2F
8L SOIC
0°C to +70°C
30
5V
ASM1232LPS−2F
ASM1232LPSF
16L SOIC
0°C to +70°C
30
5V
ASM1232LPSF
ASM1232LPSN−2F
8L SOIC
−40°C to +85°C
30
5V
ASM1232LPSN−2F
ASM1232LPSNF
16L SOIC
−40°C to +85°C
30
5V
ASM1232LPSNF
ASM1232LPUF
8L MSOP
0°C to +70°C
30
5V
ASM1232LPF
ASM1232LPUNF
8L MSOP
−40°C to +85°C
30
5V
ASM1232LPNF
LEAD FREE DEVICES
6. For parts to be packed in Tape and Reel, add “−T” at the end of the part number.
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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ASM1232LP/D
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