CY2SSTV857-32 Differential Clock Buffer/Driver DDR400/PC3200-Compliant Features Description • Operating frequency: 60 MHz to 230 MHz The CY2SSTV857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV857-32 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV857-32 features differential feedback clock outpts and inputs. This allows the CY2SSTV857-32 to be used as a zero delay buffer. • Supports 400 MHz DDR SDRAM • 10 differential outputs from one differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps When used as a zero delay buffer in nested clock trees, the CY2SSTV857-32 locks onto the input reference and translates with near-zero delay to low-skew outputs. • Power management control input • High-impedance outputs when input clock < 20 MHz • 2.6V operation • Pin-compatible with CDC857-2 and -3 • 48-pin TSSOP and 40 QFN package • Industrial temperature of –40°C to 85°C • Conforms to JEDEC DDR specification Block Diagram Pin Configuration 3 2 Test and Powerdown Logic PD 37 AVDD 16 5 6 10 9 22 23 CLK CLK# FBIN FBIN# 13 14 36 35 Y3 Y3# Y4 Y4# 1 48 VS S Y0 # 2 47 Y5 # Y5 Y0 3 46 VD D Q 4 45 VD D Q Y1 5 44 Y6 Y1 # 6 43 Y6 # VS S 7 42 VS S VS S 8 Y2 # 9 Y2 10 VD D Q 11 VS S 40 Y7 # 39 Y7 38 VD D Q 37 PD# 36 FB IN Y5 Y5# VD D Q 12 CLK 13 44 43 Y6 Y6# C LK# 14 35 FB IN # VD D Q 15 34 VD D Q 39 Y7 Y7# Y8 Y8# AVD D 16 33 FB O U T # AVS S 17 32 FB O U T VS S 18 31 VS S Y3 # 19 30 Y8 # 29 30 27 26 32 33 Y9 Y9# FBOUT FBOUT# Y3 20 29 Y8 VD D Q 21 28 VD D Q Y4 22 27 Y9 Y4 # 23 26 Y9 # VS S 24 25 VS S Rev 1.0, November 21, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 41 46 47 40 PLL Y2 Y2# VS S CY2SSTV857-32 20 19 Y0 Y0# Y1 Y1# Page 1 of 8 Tel:(408) 855-0555 Fax:(408) 855-0550 www.SpectraLinear.com CY2SSTV857-32 Y6# Y6 VDDQ Y5 Y5# Y0# Y0 VDDQ Y1 Y1# 40 QFN Package 40 39 38 37 36 35 34 33 32 31 30 Y7# 29 28 Y7 27 PD# 26 FBIN 6 25 FBIN# VDDQ 7 24 VDDQ AVDD 8 23 VDDQ AVSS VSS 9 22 FBOUT# VSS 1 Y2# Y2 2 3 VDDQ 4 CLK 5 CLK# 40 QFN CY2SSTV857-32 FBOUT Y8# Y8 VDDQ Y9 Y9# Y4# Y4 VDDQ y3 Y3# 10 11 12 13 14 15 16 17 18 19 20 21 VDDQ Pin Description Pin # 48 TSSOP Pin # 40 QFN Pin Name I/O[1] Pin Description Electrical Characteristics 13, 14 5,6 CLK, CLK# I Differential Clock Input. 35 25 FBIN# I Feedback Clock Input. Connect to FBOUT# for Differential Input accessing the PLL. 36 26 FBIN I Feedback Clock Input. Connect to FBOUT for accessing the PLL. 3, 5, 10, 20, 22 37,39,3,12,14 Y(0:4) O Clock Outputs. 2, 6, 9, 19, 23 36,40,2,11,15 Y#(0:4) O Clock Outputs. Y(9:5) O Clock Outputs. 26, 30, 40, 43, 47 16,20,30,31,35 Y#(9:5) O Clock Outputs. 32 21 FBOUT O Feedback Clock Output. Connect to FBIN for Differential Outputs normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 33 22 FBOUT# O Feedback Clock Output. Connect to FBIN# for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 37 27 PD# I Power Down Input. When PD# is set HIGH, all Q and Q# outputs are enabled and switch at the same frequency as CLK. When set LOW, all Q and Q# outputs are disabled Hi-Z and the PLL is powered down. 4, 11,12,15, 21, 28, 34, 38, 45 4,7,13,18,23,24, 28,33,38 VDDQ 2.6V Power Supply for Output Clock Buffers. 2.6V Nominal 16 8 AVDD 2.6V Power Supply for PLL. When VDDA is at 2.6V Nominal GND, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (PD# = 0), the PLL is powered down. 27, 29, 39, 44, 46 17,19,29,32,34 LV Differential Input Differential Outputs Differential Outputs 1, 7, 8, 18, 24, 25, 1,10 31, 41, 42, 48 VSS Common Ground. 0.0V Ground 17 AVSS Analog Ground. 0.0V Analog Ground 9 Note: 1. A bypass capacitor (0.1PF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. Rev 1.0, November 21, 2006 Page 2 of 8 CY2SSTV857-32 Zero Delay Buffer When VDDA is strapped LOW, the PLL is turned off and bypassed for test purposes. When used as a zero delay buffer the CY2SSTV857-32 will likely be in a nested clock tree application. For these applications, the CY2SSTV857-32 offers a differential clock input pair as a PLL reference. The CY2SSTV857-32 then can lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Power Management Output enable/disable control of the CY2SSTV857-32 allows the user to implement power management schemes into the design. Outputs are three-stated/disabled when PD# is asserted LOW (see Table 1). Table 1. Function Table Inputs AVDD PD# GND GND X X 2.6V 2.6V 2.6V Outputs CLK CLK# Y Y# FBOUT FBOUT# H L H H H L L H L L L H H L H L H H H < 20 MHz PLL H L H BYPASSED/OFF L H L BYPASSED/OFF Z Z Z Z Off Z Z Z Z OFF H L H L H On L H L H L On < 20 MHz Hi-Z Hi-Z Hi-Z HI-Z Off CLKIN FBIN t(phase error) FBOUT Yx tsk(o) Yx Yx tsk(o) Figure 1. Phase Error and Skew Waveforms Rev 1.0, November 21, 2006 Page 3 of 8 CY2SSTV857-32 CLKIN Yx or FBIN tpd Figure 2. Propagation Delay Time tPLH, tPHL Yx tC(n) tC(n+1) Figure 3. Cycle-to-cycle Jitter = 2.5" = 0.6" (Split to Terminator) DDR _SDRAM represents a capacitive load CLK 120 Ohm PLL DDR SDRAM CLK# VTR VCP FBIN 120 Ohm DDR SDRAM FBIN# FBOUT FBOUT# 120 Ohm 0.3" Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< 8 pF Figure 4. Clock Structure # 1 Rev 1.0, November 21, 2006 Page 4 of 8 CY2SSTV857-32 = 2.5" = 0.6" (Split to Terminator) DDR-SDRAM represents a capacitive load CLK DDR-SDRAM DDR-SDRAM Stack PLL 120 Ohm DDR-SDRAM CLK# VTR 120 Ohm VCP FBIN 120 Ohm DDR-SDRAM FBIN# DDR-SDRAM Stack FBOUT FBOUT# DDR-SDRAM 0.3" Output load capacitancce for 4 DDR-SDRAM Loads: 10 pF < CL < 16 pF Figure 5. Clock Structure # 1 VDDQ VDDQ V D D Q /2 14 pF OUT VTR 60 O hm RT = 120 O hm OUT# 60 O hm VCP R e c e iv e r 14 pF V D D Q /2 Figure 6. Differential Signal Using Direct Termination Resistor Rev 1.0, November 21, 2006 Page 5 of 8 CY2SSTV857-32 Absolute Maximum Conditions[2] Storage Temperature: ................................ –65°C to + 150°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Operating Temperature:................................ –40°C to +85°C VSS < (Vin or Vout) < VDDQ. Maximum Power Supply: ................................................ 3.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDDQ). Input Voltage Relative to VSS:............................... VSS – 0.3V Input Voltage Relative to VDDQ or AVDD: ........... VDDQ + 0.3V DC Electrical Specifications[3] Parameter Description Condition VDDQ Supply Voltage Operating VIL Input Low Voltage PD# Min. Typ. Max. Unit 2.375 – – 2.625 V – 0.3 × VDDQ V 0.7 × VDDQ 0.36 – – V – VDDQ + 0.6 V (VDDQ/2) + 0.2 V VIH Input High Voltage VID Differential Input Voltage[4] CLK, FBIN VIX Differential Input Crossing Voltage[5] CLK, FBIN IIN Input Current [CLK, FBIN, PD#] VIN = 0V or VIN = VDDQ –10 – 10 µA IOL Output Low Current VDDQ = 2.375V, VOUT = 1.2V 26 35 – mA IOH Output High Current VDDQ = 2.375V, VOUT = 1V 28 –32 – mA VOL Output Low Voltage VDDQ= 2.375V, IOL = 12 mA – – 0.6 V VOH Output High Voltage VDDQ = 2.375V, IOH = –12 mA VOUT Output Voltage Swing[6] VOC Output Crossing Voltage[7] IOZ IDDQ High-Impedance Output Current VO = GND or VO = VDDQ Dynamic Supply Current[8] All VDDQ, FO = 200 MHz IDD PLL Supply Current VDDA only IDDS Standby Supply Current PD# = 0 and CLK/CLK# = 0 MHz Cin Input Pin Capacitance (VDDQ/2) – 0.2 VDDQ/2 1.7 – – V 1.1 – VDDQ – 0.4 V (VDDQ/2) – 0.2 VDDQ/2 (VDDQ/2) + 0.2 V –10 – 10 µA – 235 300 mA – 9 12 mA – – 100 µA 2 – 3.5 pF AC Electrical Specifications [9, 10] Parameter Description fCLK Operating Clock Frequency Condition AVDD, VDDQ = 2.6V r 0.1V Min. Typ. Max. Unit 60 – 230 MHz tDC Input Clock Duty Cycle 40 – 60 % tLOCK Maximum PLL Lock Time – – 100 Ps DTYC Duty Cycle[11] 60 MHz to 100 MHz 49 50 51 % 101 MHz to 170 MHz 48 – 52 % 2 V/ns – 3 25 ns – 3 8 ns tsl(o) Output Clocks Slew Rate tPZL, tPZH Output Enable Time[12] (all outputs) tPLZ, tPHZ Output Disable Time[12] (all 20%–80% of VOD outputs) 1 Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Unused inputs must be held HIGH or LOW to prevent them from floating. 4. Differential input signal voltage specifies the differential voltage VTR–VCPI required for switching, where VTR is the true input level and VCP is the complementary input level. See Figure 6. 5. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signal must be crossing. 6. For load conditions see Figure 6. 7. The value of VOC is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120: resistor. See Figure 6. 8. All outputs switching load with 14 pF in 60: environment. See Figure 6. 9. Parameters are guaranteed by design and characterization. Not 100% tested in production. 10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 50 kHz with a down spread or –0.5%. 11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWHC/tC, where the cycle time(tC) decreases as the frequency goes up. 12. Refers to transition of non-inverting output. Rev 1.0, November 21, 2006 Page 6 of 8 CY2SSTV857-32 AC Electrical Specifications(continued)[9, 10] Parameter Description Condition Cycle to Cycle Jitter [10] tCCJ [10, 13] tjit(h-per) Half-period jitter tPLH(tPD) Low-to-High Propagation Delay, CLK to Y tPHL(tPD) High-to-Low Propagation Delay, CLK to Y tSK(O) Any Output to Any Output Skew[14] tPHASE Phase Min. Typ. Max. Unit f > 66 MHz –75 – 75 ps f > 66 MHz –100 – 100 ps 1.5 3.5 7.5 ns 1.5 3.5 7.5 ns – – 100 ps –50 – 50 ps Test Mode only Error[14] Ordering Information Part Number Package Type Product Flow CY2SSTV857ZC–32 48-pin TSSOP Commercial, 0q to 70qC CY2SSTV857ZC–32T 48-pin TSSOP–Tape and Reel Commercial, 0q to 70qC CY2SSTV857LFC–32[15] 40-pin QFN Commercial, 0q to 70qC 40-pin QFN–Tape and Reel Commercial, 0q to 70qC CY2SSTV857ZI–32 48-pin TSSOP Industrial, –40q to 85qC CY2SSTV857ZI–32T 48-pin TSSOP–Tape and Reel Industrial, –40q to 85qC CY2SSTV857LFI–32[15] 40-pin QFN Industrial, –40q to 85qC 40-pin QFN–Tape and Reel Industrial, –40q to 85qC CY2SSTV857LFC–32T [15] [15] CY2SSTV857LFI–32T Lead-Free CY2SSTV857ZXC–32 48-pin TSSOP Commercial, 0q to 70qC CY2SSTV857ZXC–32T 48-pin TSSOP–Tape and Reel Commercial, 0q to 70qC 40-pin QFN Commercial, 0q to 70qC 40-pin QFN–Tape and Reel Commercial, 0q to 70qC CY2SSTV857ZXI–32 48-pin TSSOP Industrial, –40q to 85qC CY2SSTV857ZXI–32T 48-pin TSSOP–Tape and Reel Industrial, –40q to 85qC CY2SSTV857LFXC–32[15] CY2SSTV857LFXC–32T [15] 857-32 0327L11 *SWR# Marketing Part Number Date Code and Fab Location Lot Code Figure 7. Actual Marking on the Device Notes: 13. Period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 14. All differential input and output terminals are terminated with 120:/16 pF, as shown in Figure 5. 15. The ordering part number differs from the marking on the actual device. See Figure 7 for the actual marking on the device. Rev 1.0, November 21, 2006 Page 7 of 8 CY2SSTV857-32 Package Drawing and Dimension 48-lead (240-mil) TSSOP II Z4824 0.500[0.019] 24 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 7.950[0.313] 8.255[0.325] PACKAGE WEIGHT 0.33gms 5.994[0.236] 6.198[0.244] PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 25 48 12.395[0.488] 12.598[0.496] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.500[0.020] BSC 0.851[0.033] 0.950[0.037] 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0.508[0.020] 0.762[0.030] 0°-8° 0.100[0.003] 0.200[0.008] SEATING PLANE DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-220 40-lead QFN 6 x 6 MM LF40A BOTTOM VIEW SIDE VIEW TOP VIEW 0.08[0.003] A C 1.00[0.039] MAX. 5.90[0.232] 6.10[0.240] 0.05[0.002] MAX. 0.80[0.031] MAX. 5.70[0.224] 5.80[0.228] 0.18[0.007] 0.28[0.011] 0.20[0.008] REF. 0.60[0.024] DIA. PIN1 ID 0.20[0.008] R. N N 1 1 2 2 0.45[0.018] 0.30[0.012] 0.50[0.020] 4.45[0.175] 4.55[0.179] 5.90[0.232] 6.10[0.240] 5.70[0.224] 5.80[0.228] E-PAD (PAD SIZE VARY BY DEVICE TYPE) 0°-12° 0.50[0.020] C SEATING PLANE 0.24[0.009] 0.60[0.024] (4X) 4.45[0.175] 4.55[0.179] While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 21, 2006 Page 8 of 8