LINER LTC2485 24-bit adc with easy drive input current cancellation and i2c interface Datasheet

LTC2485
24-Bit ∆Σ ADC with Easy Drive
Input Current Cancellation
and I2C Interface
Description
Features
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Easy Drive™ Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
GND to VCC Input/Reference Common Mode Range
2-Wire I2C Interface
Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
2ppm (0.25LSB) INL, No Missing Codes
1ppm Offset and 15ppm Full-Scale Error
Selectable 2x Speed Mode
No Latency: Digital Filter Settles in a Single Cycle
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
Six Addresses Available and One Global Address for
Synchronization
Available in a Tiny (3mm × 3mm)
10-Lead DFN Package
Applications
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Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Strain Gauge Transducers
Instrumentation
Industrial Process Control
DVMs and Meters
The LTC®2485 combines a 24-bit plus sign No Latency
∆Σ™ analog-to-digital converter with patented Easy Drive
technology and I2C digital interface. The patented sampling
scheme eliminates dynamic input current errors and the
shortcomings of on-chip buffering through automatic
cancellation of differential input current. This allows large
external source impedances and input signals, with rail-torail input range to be directly digitized while maintaining
exceptional DC accuracy.
The LTC2485 includes an on-chip oscillator. The LTC2485
can be configured through an I2C interface to reject line
frequencies. 50Hz, 60Hz or simultaneous 50Hz/60Hz
line frequency rejection can be selected as well as a 2x
speed-up mode.
The LTC2485 allows a wide common mode input range
(0V to VCC) independent of the reference voltage. The
reference can be as low as 100mV or can be tied directly
to VCC. The LTC2485 includes an on-chip trimmed oscillator eliminating the need for external crystals or oscillators. Absolute accuracy and low drift are automatically
maintained through continuous, transparent, offset and
full-scale calibration.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ∆∑ and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Typical Application
+FS Error vs RSOURCE at IN+ and IN–
80
0.1µF
10k
1µF
IDIFF = 0
VIN+
SENSE
REF+
VCC
LTC2485
VIN–
10k
0.1µF
GND
REF–
SCL
SDA
CA0/f0
CA1
2-WIRE
I2C INTERFACE
6 ADDRESSES
+FS ERROR (ppm)
VCC
VCC = 5V
= 5V
60 VREF
VIN+ = 3.75V
– = 1.25V
40 VIN
fO = GND
20 TA = 25°C
CIN = 1µF
0
–20
–40
2485 TA01a
–60
–80
For more information www.linear.com/LTC2485
1
10
100
1k
RSOURCE (Ω)
10k
100k
2485 TA01b
2485fd
1
LTC2485
Absolute Maximum Ratings
Pin Configuration
(Notes 1, 2)
TOP VIEW
Supply Voltage (VCC) to GND....................... – 0.3V to 6V
Analog Input Voltage to GND........ –0.3V to (VCC + 0.3V)
Reference Input Voltage to GND... –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND....... –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2485C..................................................... 0°C to 70°C
LTC2485I .................................................– 40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
REF+
1
VCC
2
10 CA0/f0
9 CA1
REF –
3
IN+
4
7 SDA
IN–
5
6 SCL
11
8 GND
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2485CDD#PBF
LTC2485CDD#TRPBF
LBST
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC2485IDD#PBF
LTC2485IDD#TRPBF
LBST
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical Characteristics (Normal Speed)
The l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
●
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
●
2
1
10
ppm of VREF
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13)
●
0.5
2.5
µV
Offset Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF
25
ppm of VREF
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
Output Noise
5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 12)
Internal PTAT Signal
TA = 27°C
2
MIN
TYP
MAX
24
Bits
10
●
nV/°C
0.1
ppm of VREF/°C
25
●
ppm of VREF
0.1
ppm of VREF/°C
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
0.6
390
UNITS
µVRMS
450
mV
2485fd
For more information www.linear.com/LTC2485
LTC2485
Electrical Characteristics (2x Speed)
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
●
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
●
2
1
10
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13)
●
0.5
2
mV
Offset Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN– = 0.75VREF, IN+ = 0.25VREF
5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Output Noise
MIN
TYP
MAX
UNITS
24
Bits
100
nV/°C
25
●
ppm of VREF
0.1
ppm of VREF/°C
25
●
ppm of VREF
0.1
ppm of VREF/°C
0.84
µVRMS
Converter Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
●
140
dB
Input Common Mode Rejection
50Hz ± 2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
●
140
dB
Input Common Mode Rejection
60Hz ±2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
●
140
dB
Input Normal Mode Rejection
50Hz ±2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7)
●
110
120
dB
Input Normal Mode Rejection
60Hz ±2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 8)
●
110
120
dB
Input Normal Mode Rejection
50Hz/60Hz ±2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 9)
●
87
Reference Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
●
120
140
dB
Power Supply Rejection DC
VREF = 2.5V, IN– = IN+ = GND
120
dB
Power Supply Rejection, 50Hz ±2%
VREF = 2.5V, IN– = IN+ = GND (Notes 7, 9)
120
dB
Power Supply Rejection, 60Hz ±2%
= 2.5V, IN– = IN+ = GND (Notes 8, 9)
120
dB
VREF
MIN
TYP
MAX
UNITS
dB
Analog Input and Reference
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
CONDITIONS
MIN
GND – 0.3V
VCC + 0.3V
V
IN–
Absolute/Common Mode IN– Voltage
GND – 0.3V
VCC + 0.3V
V
FS
Full-Scale of the Differential Input (IN+ – IN–)
●
0.5VREF
TYP
MAX
UNITS
V
LSB
Least Significant Bit of the Output Code
●
FS/224
VIN
Input Differential Voltage Range (IN+ – IN–)
●
–FS
+FS
V
VREF
Reference Voltage Range (REF+ – REF–)
●
0.1
VCC
V
2485fd
For more information www.linear.com/LTC2485
3
LTC2485
Analog Input and Reference
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
(IN+)
IN+ Sampling Capacitance
11
pF
CS (IN–)
IN– Sampling Capacitance
11
pF
CS
CS (VREF)
VREF Sampling Capacitance
IDC_LEAK (IN+)
IN+ DC Leakage Current
Sleep Mode, IN+ = GND
●
–10
11
1
10
nA
pF
IDC_LEAK (IN–)
IN– DC Leakage Current
Sleep Mode, IN– = GND
●
–10
1
10
nA
IDC_LEAK (VREF)
REF+, REF– DC Leakage Current
Sleep Mode, VREF = VCC
●
–100
1
100
nA
I2C Digital Inputs and Digital Outputs
The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
●
VIL
Low Level Input Voltage
●
0.7VCC
V
VIL(CA1)
Low Level Input Voltage for Address Pin
●
VIH(CA0/f0,CA1)
High Level Input Voltage for Address Pins
●
RINH
Resistance from CA0/f0, CA1 to VCC to Set
Chip Address Bit to 1
●
10
kΩ
RINL
Resistance from CA1 to GND to Set Chip
Address Bit to 0
●
10
kΩ
RINF
Resistance from CA0/f0, CA1 to VCC or
GND to Set Chip Address Bit to Float
●
2
II
Digital Input Current
●
–10
VHYS
Hysteresis of Schmitt Trig­ger Inputs
(Note 5)
VOL
Low Level Output Voltage SDA
I = 3mA
●
tOF
Output Fall Time from VIHMIN to VILMAX
Bus Load CB 10pF to 400pF (Note 14)
●
tSP
Input Spike Suppression
IIN
Input Leakage
CI
Capacitance for Each I/O Pin
●
CB
Capacitance Load for Each Bus Line
●
400
pF
CCAX
External Capacitive Load On-Chip Address
Pins (CA0/f0,CA1) for Valid Float
●
10
pF
V
0.05VCC
V
0.95VCC
V
MΩ
10
µA
0.05VCC
V
20+0.1CB
●
0.1VCC ≤ VIN ≤ VCC
0.3VCC
●
VIH(EXT,OSC)
High Level CA0/f0 External Oscillator
2.7V ≤ VCC < 5.5V
●
VIL(EXT,OSC)
Low Level CA0/f0 External Oscillator
2.7V ≤ VCC < 5.5V
●
0.4
V
250
ns
50
ns
1
µA
10
pF
VCC – 0.5V
V
0.5
V
Power Requirements
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
4
CONDITIONS
MIN
●
Conversion Mode (Note 11)
Sleep Mode (Note 11)
●
●
TYP
MAX
5.5
V
160
1
250
2
µA
µA
2.7
UNITS
2485fd
For more information www.linear.com/LTC2485
LTC2485
Timing Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
MAX
UNITS
fEOSC
External Oscillator Frequency Range
CONDITIONS
●
MIN
10
TYP
1000
kHz
tHEO
External Oscillator High Period
●
0.125
100
µs
tLEO
External Oscillator Low Period
●
0.125
100
µs
tCONV_1
Conversion Time for 1x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
●
●
●
●
157.2
131.0
144.1
160.3
133.6
146.9
41036/fEOSC
163.5
136.3
149.9
ms
ms
ms
ms
tCONV_2
Conversion Time for 2x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
●
●
●
●
78.7
65.6
72.2
80.3
66.9
73.6
20556/fEOSC
81.9
68.2
75.1
ms
ms
ms
ms
I2C Timing Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 15)
SYMBOL
PARAMETER
CONDITIONS
MIN
fSCL
SCL Clock Frequency
●
0
TYP
MAX
UNITS
400
kHz
tHD(SDA)
Hold Time (Repeated) START Condition
●
0.6
µs
tLOW
LOW Period of the SCL Clock Pin
●
1.3
µs
tHIGH
HIGH Period of the SCL Clock Pin
●
0.6
µs
tSU(STA)
Set-Up Time for a Repeated START Condition
●
0.6
tHD(DAT)
Data Hold Time
●
0
tSU(DAT)
Data Set-Up Time
●
100
tr
Rise Time for Both SDA and SCL Signals
(Note 14)
●
20+0.1CB
300
ns
tf
Fall Time for Both SDA and SCL Signals
(Note 14)
●
20+0.1CB
300
ns
tSU(STO)
Set-Up Time for STOP Condition
●
0.6
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2, FS = 0.5VREF;
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
µs
0.9
µs
ns
µs
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The external oscillator is connected to the CA0/f0 pin. The
external oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses the internal oscillator.
Note 12: The output noise includes the contribution of the internal
calibration operations.
Note 13: Guaranteed by design and test correlation.
Note 14: CB = capacitance of one bus line in pF.
Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.
2485fd
For more information www.linear.com/LTC2485
5
LTC2485
Typical Performance Characteristics
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
–45°C
1
25°C
0
85°C
–1
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
2
INL (ppm OF VREF)
2
INL (ppm OF VREF)
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
1
–45°C, 25°C, 90°C
0
–1
–2
–2
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
1
–45°C, 25°C, 90°C
0
–1
–2
–3
–1.25
2.5
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
2
INL (ppm OF VREF)
3
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
–0.75
–3
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–0.75
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2485 G03
2485 G02
2485 G01
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
25°C
4
0
8
85°C
12
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
85°C
–45°C
–4
4
–45°C
0
–4
2
–12
–1.25
2.5
12
12
6
4
–0.75
–4
–12
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2485 G06
2485 G07
3
4
0
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (µV)
1.25
VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V
4 TA = 25°C, RMS NOISE = 0.60µV
6
0
1.8
–0.25
0.25
0.75
INPUT VOLTAGE (V)
Long-Term ADC Readings
8
2
1.2
–0.75
5
10,000 CONSECUTIVE
READINGS
RMS = 0.59µV
VCC = 2.7V
AVERAGE = –0.19µV
VREF = 2.5V
10 VIN = 0V
TA = 25°C
2
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (µV)
–45°C
0
Noise Histogram (7.5sps)
14
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
Noise Histogram (6.8sps)
8
85°C
2485 G05
14
10,000 CONSECUTIVE
READINGS
RMS = 0.60µV
VCC = 5V
AVERAGE = –0.69µV
VREF = 5V
10 VIN = 0V
TA = 25°C
25°C
4
–8
2485 G04
6
8
–8
–8
–12
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
25°C
ADC READING (µV)
TUE (ppm OF VREF)
8
12
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
TUE (ppm OF VREF)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TUE (ppm OF VREF)
12
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
2
1
0
–1
–2
–3
–4
1.2
1.8
2485 G08
–5
0
10
30
40
20
TIME (HOURS)
50
60
2485 G09
2485fd
For more information www.linear.com/LTC2485
LTC2485
Typical Performance Characteristics
RMS Noise
vs Input Differential Voltage
RMS NOISE (ppm OF VREF)
0.9
RMS Noise vs VIN(CM)
1.0
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.9
0.8
RMS NOISE (µV)
0.8
0.7
0.6
RMS Noise vs Temperature (TA)
1.0
0.7
0.6
0.5
0.4
2.5
–1
0
2
1
3
5
4
RMS NOISE (µV)
RMS NOISE (µV)
RMS Noise vs VREF
0.6
0.3
VCC = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.9
0.7
0.8
0.7
0.6
0.5
0.5
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
0.4
5.5
0
1
2
3
VREF (V)
0
–0.1
–0.2
–0.3
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2485 G16
0.1
0
–0.1
–0.2
–0.3
–1
0
1
3
2
VIN(CM) (V)
5
4
0.2
0.1
0.3
REF+ = 2.5V
– = GND
0
Offset Error vs VREF
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.2
0.1
0
–0.1
–0.1
–0.2
–0.3
2.7
6
2485 G15
Offset Error vs VCC
REF
VIN = 0V
VIN(CM) = GND
TA = 25°C
90
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
0.2
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.3
0.1
75
Offset Error vs VIN(CM)
2485 G14
Offset Error vs Temperature
0.2
5
4
2485 G13
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
0 15 30 45 60
TEMPERATURE (°C)
2485 G12
OFFSET ERROR (ppm OF VREF)
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.4
2.7
0.4
–45 –30 –15
6
2485 G11
1.0
0.8
0.3
0.6
VIN(CM) (V)
RMS Noise vs VCC
0.9
0.7
0.5
2485 G10
1.0
0.8
0.5
0.4
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
0.9
RMS NOISE (µV)
1.0
–0.2
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
2485 G17
–0.3
0
1
2
3
VREF (V)
4
5
2485.G18
2485fd
For more information www.linear.com/LTC2485
7
LTC2485
Typical Performance Characteristics
On-Chip Oscillator Frequency
vs Temperature
310
310
304
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
304
75
300
90
2.5
3.0
3.5
4.0
VCC (V)
4.5
5.0
–60
–80
–120
–140
30600
30650
30700
SUPPLY CURRENT (µA)
SLEEP MODE CURRENT (µA)
1.6
VCC = 5V
1.0
0.8
VCC = 2.7V
0.4
0 15 30 45 60
TEMPERATURE (°C)
75
90
2485 G25
8
120
3
VREF = VCC
+
450 IN– = GND
IN = GND
400 CA0/f0 = EXT OSC
TA = 25°C
2
350
300
250
VCC = 5V
200
0 15 30 45 60
TEMPERATURE (°C)
100
VCC = 3V
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
25
2485 G26
75
90
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
1
0
25°C, 90°C
–1
–2
150
0.2
VCC = 2.7V
140
2485 G24
500
1.8
0
–45 –30 –15
160
Conversion Current
vs Output Data Rate
2.0
0.6
VCC = 5V
2485 G23
Sleep Mode Current
vs Temperature
1M
180
100
–45 –30 –15
30800
30750
FREQUENCY AT VCC (Hz)
2485 G22
1.2
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
200
–80
–120
1.4
10
Conversion Current
vs Temperature
–60
–100
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
1
2485 G21
PSRR vs Frequency at VCC
VCC = 4.1V DC ±0.7V
= 2.5V
V
–20 INREF
+ = GND
– = GND
IN
–40 TA = 25°C
–100
–140
–140
CONVERSION CURRENT (µA)
REJECTION (dB)
–40
0
REJECTION (dB)
–20
5.5
2485 G20
PSRR vs Frequency at VCC
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
TA = 25°C
–80
–120
2485 G19
0
–60
–100
302
0 15 30 45 60
TEMPERATURE (°C)
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
TA = 25°C
–40
306
INL (ppm OF VREF)
300
–45 –30 –15
PSRR vs Frequency at VCC
–20
REJECTION (dB)
FREQUENCY (kHz)
FREQUENCY (kHz)
306
0
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
308
308
302
On-Chip Oscillator Frequency
vs VCC
–45°C
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
2.5
2485 G27
2485fd
For more information www.linear.com/LTC2485
LTC2485
Typical Performance Characteristics
1
0
–45°C, 25°C
–2
1
90°C
0
–45°C, 25°C
–1
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–3
–1.25
1.25
200
–0.75
196
0.6
0.4
VCC = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
240
194
192
190
188
186
180
–1
1
0
3
VIN(CM) (V)
2
4
100
220
0
5.5
–40
210
200
190
2485 G34
160
90
VCC = 4.1V DC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
TA = 25°C
–20
–60
–80
–100
–120
170
5
75
PSRR vs Frequency at VCC
(2x Speed Mode)
180
50
0 15 30 45 60
TEMPERATURE (°C)
2485 G33
REJECTION (dB)
OFFSET ERROR (µV)
OFFSET ERROR (µV)
160
–45 –30 –15
6
5
VCC = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
230
4
4.5
VCC (V)
190
170
240
150
3.5
200
Offset Error vs VREF
(2x Speed Mode)
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
2.7 3
210
2485 G32
Offset Error vs VCC
(2x Speed Mode)
0
220
180
182
5
188.6
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
230
2485 G31
200
183.8
186.2
OUTPUT READING (µV)
Offset Error vs Temperature
(2x Speed Mode)
184
4
181.4
2485 G30
OFFSET ERROR (µV)
OFFSET ERROR (µV)
RMS NOISE (µV)
0.8
3
2
VREF (V)
4
0
179
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
198
1
6
Offset Error vs VIN(CM)
(2x Speed Mode)
1.0
0
8
2485 G29
RMS Noise vs VREF
(2x Speed Mode)
0.2
RMS = 0.86µV
10,000 CONSECUTIVE
AVERAGE = 0.184mV
14 READINGS
VCC = 5V
12 VREF = 5V
VIN = 0V
T = 25°C
10 A
2
2485 G28
250
16
–2
–3
–1.25
0
Noise Histogram
(2x Speed Mode)
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
2
90°C
–1
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
NUMBER OF READINGS (%)
2
INL (ppm OF VREF)
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
INL (ppm OF VREF)
3
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
0
1
2
3
VREF (V)
4
5
2485 G35
–140
1
10
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
1M
2485 G36
2485fd
For more information www.linear.com/LTC2485
9
LTC2485
Typical Performance Characteristics
PSRR vs Frequency at VCC
(2x Speed Mode)
RREJECTION (dB)
–20
–40
0
VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
TA = 25°C
VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
–40 IN– = GND
TA = 25°C
–20
REJECTION (dB)
0
PSRR vs Frequency at VCC
(2x Speed Mode)
–60
–80
–60
–80
–100
–100
–120
–120
–140
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
–140
30600
30650
30700
30750
FREQUENCY AT VCC (Hz)
30800
2485 G38
2485 G37
Pin Functions
REF+ (Pin 1), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF+, is
more positive than the reference negative input, REF –,
by at least 0.1V.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor as close to the part as possible.
IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The voltage on these pins can have any value between GND – 0.3V
and VCC + 0.3V. Within these limits the converter bipolar
input range (VIN = IN+ – IN–) extends from –0.5 • VREF
to 0.5 • VREF. Outside this input range the converter produces unique overrange and underrange output codes.
I2C
Interface. The
SCL (Pin 6): Serial Clock Pin of the
LTC2485 can only act as a slave and the SCL pin only
accepts external serial clock. Data is shifted into the
SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the
SCL clock.
10
SDA (Pin 7): Bidirectional Serial Data Line of the I2C Interface. In the transmitter mode (Read), the conversion result
is output through the SDA pin, while in the receiver mode
(Write), the device configuration bits are input through the
SDA pin. At data input mode, the pin is high impedance;
while at data output mode, it is an open-drain N-channel
driver and therefore an external pull-up resistor or current
source to VCC is needed.
GND (Pin 8): Ground. Connect this pin to a ground plane
through a low impedance connection.
CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is
configured as a three state (LOW, HIGH, or Floating) address control bit for the device I2C address.
CA0/f0 (Pin 10): Chip Address Control Pin/External Clock
Input Pin. When no transition is detected on the CA0/f0
pin, it is a two state (HIGH or Floating) address control
bit for the device I2C address. When the pin is driven by
an external clock signal with a frequency fEOSC of at least
10kHz, the converter uses this signal as its system clock
and the fundamental digital filter rejection null is located
at a frequency fEOSC/5120 and sets the Chip Address CA0
internally to a HIGH.
2485fd
For more information www.linear.com/LTC2485
LTC2485
Functional Block Diagram
2
1
4
5
REF+
VCC
IN+
MUX
IN–
TEMP
SENSOR
SCL
REF+
IN+
IN–
I2C
SERIAL
INTERFACE
3RD ORDER
∆Σ ADC
REF–
SDA
CA1
CA0/f0
6
7
9
10
AUTOCALIBRATION
AND CONTROL
REF–
3
GND
8
INTERNAL
OSCILLATOR
2485 FB
2485fd
For more information www.linear.com/LTC2485
11
LTC2485
Applications Information
Converter Operation
Converter Operation Cycle
The LTC2485 is a low power, ∆Σ analog-to-digital converter
with an I2C interface. After power on reset, its operation
is made up of three states. The converter operating cycle
begins with the conversion, followed by the low power sleep
state and ends with the data output/input (see Figure 1).
POWER ON RESET
DEFAULT CONFIGURATION:
EXTERNAL INPUT
50/60Hz REJECTION
1X SPEED, AUTOCAL
CONVERSION
I2C INTERFACE
The LTC2485 communicates through an I2C interface.
The I2C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus.
The connected devices can only pull the bus wires LOW
and they never drive the bus HIGH. The bus wires are
externally connected to a positive supply voltage via a
current-source or pull-up resistor. When the bus is free,
both lines are HIGH. Data on the I2C-bus can be transferred
at rates of up to 100kbit/s in the Standard-mode and up
to 400kbit/s in the Fast-mode. The VCC power should not
be removed from the device when the I2C bus is active to
avoid loading the I2C bus lines through the internal ESD
protection diodes.
SLEEP
NO
ACKNOWLEDGE
YES
DATA OUTPUT
NO
STOP
OR READ
32-BITS
YES
2485 F01
Figure 1. LTC2485 State Transition Diagram
Initially, the LTC2485 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as it is not addressed for a read/write operation. The conversion result is held indefinitely in a static
shift register while the converter is in the sleep state.
The device will not acknowledge an external request during the conversion state. After a conversion is finished,
12
the device is ready to accept a read/write request. Once
the LTC2485 is addressed for a read operation, the device
begins outputting the conversion result under control of
the serial clock (SCL). There is no latency in the conversion result. The data output is 32 bits long and contains
a 24-bit plus sign conversion result. This result is shifted
out on the SDA pin under the control of the SCL. Data
is updated on the falling edges of SCL allowing the user
to reliably latch data on the rising edge of SCL. In write
operation, the device accepts one configuration byte and
the data is shifted in on the rising edges of the SCL. A
new conversion is initiated by a STOP condition following
a valid write operation or at the conclusion of a data read
operation (read out all 32 bits).
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. At the same time any device addressed is considered a slave.
The LTC2485 can only be addressed as a slave. Once addressed, it can receive configuration bits or transmit the
last conversion result. Therefore the serial clock line SCL
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
is an input only and the data line SDA is bidirectional. The
device supports the Standard-mode and the Fast-mode
for data transfer speeds up to 400kbit/s. Figure 2 shows
the definition of timing for Fast/Standard-mode devices
on the I2C-bus.
The START and STOP Conditions
A START condition is generated by transitioning SDA from
HIGH to LOW while SCL is HIGH. The bus is considered to
be busy after the START condition. When the data transfer
is finished, a STOP condition is generated by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is
free again a certain time after the STOP condition. START
and STOP conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated START (Sr) conditions are functionally identical
to the START (S).
Data Transferring
After the START condition, the I2C bus is busy and data
transfer is set between a master and a slave. Data is transferred over I2C in groups of nine bits (one byte) followed
by an acknowledge bit, therefore each group takes nine
SCL cycles. The transmitter releases the SDA line during
the acknowledge clock pulse and the receiver issues an
Acknowledge (ACK) by pulling SDA LOW or leaves SDA
HIGH to indicate a Not Acknowledge (NAK) condition.
Change of data state can only happen while SCL is LOW.
Accessing the Special Features of the LTC2485
The LTC2485 combines a high resolution, low noise ∆Σ
analog-to-digital converter with an on-chip selectable
temperature sensor, programmable digital filter and output
rate control. These special features are selected through a
single 8-bit serial input word during the data input/output
cycle (see Figure 3).
SDA
tLOW
tf
tSU;DAT
tr
tr
tHD;STA
tr
tSP
tBUF
SCL
S
tHD;STA
tHD;DAT
tSU;STA
tHIGH
tSU;STO
Sr
P
S
2485 F02
Figure 2. Definition of Timing for F/S-Mode Devices on the I2C-Bus
1
2
…
7
8
9
1
2
3
4
5
6
7
8
9
SCL
SDA
7-BIT ADDRESS
W
IM
FA
ACK BY
LTC2485
START BY
MASTER
SLEEP
FB
SPD
ACK BY
LTC2485
DATA INPUT
2485 F03
Figure 3. Timing Diagram for Writing to the LTC2485
2485fd
For more information www.linear.com/LTC2485
13
LTC2485
Applications Information
The LTC2485 powers up in a default mode commonly
used for most measurements. The device will remain in
this mode until a valid write cycle is performed. In this
default mode, the measured input is external, the digital
filter simultaneously rejects 50Hz and 60Hz line frequency
noise, and the speed mode is 1x (offset automatically,
continuously calibrated).
The I2C serial interface grants access to any or all special
functions contained within the LTC2485. In order to change
the mode of operation, a valid write address followed by 8
bits of data are shifted into the device (see Table 1). The
first 4 bits are reserved and should be low. The 5th bit
(IM) is used to select the internal temperature sensor as
the conversion input, while the 6th and 7th bits (FA, FB)
combine to determine the line frequency rejection mode.
The 8th bit (SPD) is used to double the output rate by
disabling the offset auto calibration.
Temperature Sensor (IM)
The LTC2485 includes an on-chip temperature sensor.
The temperature sensor is selected by setting IM = 1 in
the serial input data stream. Conversions are performed
directly on the temperature sensor by the converter. While
operating in this mode, the device behaves as a temperature
to bits converter. The digital reading is proportional to the
absolute temperature of the device. This feature allows
the converter to linearize temperature sensors or continuously remove temperature effects from external sensors.
Several applications leveraging this feature are presented
in more detail in the applications section. While operating
in this mode, the speed is set to normal independent of
the control bit (SPD).
Rejection Mode (FA, FB)
IM
FA
FB
0
0
0
0
External Input, 50Hz and 60Hz Rejection,
Auto-Calibration
0
0
1
0
External Input, 50Hz Rejection,
Auto-Calibration
The LTC2485 includes a high accuracy on-chip oscillator with no required external components. Coupled with
a 4th order digital lowpass filter, the LTC2485 rejects
line frequency noise. In the default mode, the LTC2485
simultaneously rejects 50Hz and 60Hz by at least 87dB.
The LTC2485 can also be configured to selectively reject
50Hz or 60Hz to better than 110dB.
0
1
0
0
External Input, 60Hz Rejection,
Auto-Calibration
Speed Mode (SPD)
0
0
0
1
External Input, 50Hz and 60Hz Rejection,
2x Speed
0
0
1
1
External Input, 50Hz Rejection, 2x Speed
0
1
0
1
External Input, 60Hz Rejection, 2x Speed
1
0
0
0
Temperature Input, 50Hz and 60Hz
Rejection, Auto-Calibration
1
0
1
X
Temperature Input, 50Hz Rejection,
Auto-Calibration
1
1
0
X
Temperature Input, 60Hz Rejection,
Auto-Calibration
X
1
1
X
Reserved, Do Not Use
Table 1. Selecting Special Modes
14
SPD COMMENTS
The LTC2485 continuously performs offset calibrations.
Every conversion cycle, two conversions are automatically
performed (default) and the results combined. This result
is free from offset and drift. In applications where the offset
is not critical, the auto-calibration feature can be disabled
with the benefit of twice the output rate.
Linearity, full-scale accuracy and full-scale drift are identical for both 2x and 1x speed modes. In both the 1x and
2x speed there is no latency. This enables input steps or
multiplexer channel changes to settle in a single conversion cycle easing system overhead and increasing the
effective conversion rate.
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
LTC2485 Data Format
After a START condition, the master sends a 7-bit address
followed by a R/W bit. The bit R/W is 1 for a Read request
and 0 for a Write request. If the 7-bit address agrees with
an LTC2485’s address, that device is selected. When the
device is in the conversion state, it does not accept the
request and issues a Not-Acknowledge (NAK) by leaving
SDA HIGH. A write operation will also generate an NAK
signal. If the conversion is complete, it issues an acknowledge (ACK) by pulling SDA LOW.
The LTC2485 has two registers. The output register
contains the result of the last conversion and a user programmable configuration register that sets the converter
operation mode.
The output register contains the last conversion result.
After each conversion is completed, the device automatically enters the sleep state where the supply current is
reduced to 1µA. When the LTC2485 is addressed for a
Read operation, it acknowledges (by pulling SDA LOW)
and acts as a transmitter. The master and receiver can
read up to four bytes from the LTC2485. After a complete
Read operation (4 bytes), the output register is emptied, a
new conversion is initiated, and a following Read request
in the same output phase will be NAKed. The LTC2485
output data stream is 32 bits long, shifted out on the falling
edges of SCL. The first bit is the conversion result sign
bit (SIG), (see Tables 2 and 3). This bit is HIGH if VIN ≥ 0.
It is LOW if VIN <0. The second bit is the most significant
bit (MSB) of the result. The first two bits (SIG and MSB)
can be used to indicate over range conditions. If both bits
are HIGH, the differential input voltage is above +FS and
the following 24 bits are set to LOW to indicate an overrange condition. If both bits are LOW, the input voltage
is below –FS and the following 24 bits are set to HIGH to
indicate an underrange condition. The function of these
two bits is summarized in Table 1. The next 24 bits contain
the conversion results in binary two’s complement format.
The remaining six bits are Sub LSBs below the 24-bit level.
As long as the voltage on the IN+ and IN– pins is maintained within the – 0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS=0.5 • VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
Table 2. LTC2485 Status Bits
INPUT RANGE
BIT 31 SIG
BIT 30 MSB
VIN ≥ 0.5 • VREF
1
1
0V ≤ VIN < 0.5 • VREF
1/0
0
–0.5 • VREF ≤ VIN < 0V
0
1
VIN < – 0.5 • VREF
0
0
Table 3. LTC2485 Output Data Format
DIFFERENTIAL INPUT VOLTAGE VIN *
BIT 31 SIG
BIT 30 MSB
BIT 29
BIT 28
BIT 27
…
BIT 0
VIN* ≥ FS**
1
1
0
0
0
…
0
FS** – 1LSB
1
0
1
1
1
…
1
0.5 • FS**
1
0
1
0
0
…
0
0.5 • FS** – 1LSB
1
0
0
1
1
…
1
1/0***
0
0
0
0
…
0
–1LSB
0
1
1
1
1
…
1
– 0.5 • FS**
0
1
1
0
0
…
0
– 0.5 • FS** – 1LSB
0
1
0
1
1
…
1
– FS**
0
1
0
0
0
…
0
VIN* < –FS**
0
0
1
1
1
…
****
0
* The differential input voltage VIN = IN+ – IN–.
** The full-scale voltage FS = 0.5 • VR0F .
*** The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
**** When operating in the 2x speed mode, the underrange output is 0x3FFFxxx.
2485fd
For more information www.linear.com/LTC2485
15
LTC2485
Applications Information
Initiating a New Conversion
LTC2485 Address
When the LTC2485 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a Read operation. After the device acknowledges
a Read request, the device exits the sleep state and enters
the data output state. The data output state concludes
and the LTC2485 starts a new conversion once a STOP
condition is issued by the master or all 32 bits of data are
read out of the device.
The LTC2485 has two address pins, enabling one in 6
possible addresses, as shown in Table 4.
Table 4. LTC2485 Address Assignment
During the data read cycle, a stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This stop command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NAK cycle).
1 … 7
8
7-BIT
ADDRESS
R
9
SGN
ACK BY
LTC2485
START BY
MASTER
SLEEP
1
2 …
MSB
CA1
CA0/f0 *
ADDRESS
LOW
HIGH
001 01 00
LOW
Floating
001 01 01
Floating
HIGH
001 01 11
Floating
Floating
010 01 00
HIGH
HIGH
010 01 10
HIGH
Floating
010 01 11
* CA0/f0 is treated as HIGH when driven by a valid external clock.
In addition to the configurable addresses listed in Table
4, the LTC2485 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2485s.
9
D23
1
2
3
4
5
6
7
8
9
LSB
ACK BY
MASTER
SUB LSBs
NAK BY
MASTER
DATA OUTPUT
2485 F04
Figure 4. Timing Diagram for Reading from the LTC2485
16
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
The LTC2485 acts as a transmitter or receiver. The device
may be programmed to perform several functions. These
include measuring an external differential input signal or
an integrated temperature sensor, selecting line frequency
rejection (50Hz, 60Hz, or simultaneous 50Hz and 60Hz),
and a 2x speed up mode.
a read operation. At the end of a read operation, a new
conversion begins. At the conclusion of the conversion
cycle, the next result may be read using the method described above. If the conversion cycle is not concluded
and a valid address selects the device, the LTC2485
generates a NAK signal indicating the conversion cycle
is in progress.
Continuous Read
Continuous Read/Write
Operation Sequence
In applications where the configuration does not need to
change for each conversion cycle, the conversion result
can be continuously read. The configuration remains
unchanged from the last value written into the device.
If the device has not been written to since power up, the
configuration is set to the default value (Input External,
simultaneous 50Hz/60Hz rejection, and 1x speed mode).
The operation sequence is shown in Figure 6. When the
conversion is finished, the device may be addressed for
S
R/W
7-BIT ADDRESS
CONVERSION
ACK
Once the conversion cycle is concluded, the LTC2485
can be written to then read from, using the repeated Start
(Sr) command.
Figure 7 shows a cycle which begins with a data Write, a
repeated start, followed by a read, and concluded with a
stop command. The following conversion begins after all
32 bits are read out of the device or after the STOP command and uses the newly programmed configuration data.
DATA
SLEEP
Sr
DATA TRANSFERRING
P
DATA INPUT/OUTPUT
CONVERSION
2485 F05
Figure 5. The LTC2485 Conversion Sequence
S
7-BIT ADDRESS
CONVERSION
R ACK
SLEEP
READ
P
S
7-BIT ADDRESS
CONVERSION
DATA OUTPUT
R ACK
SLEEP
READ
DATA OUTPUT
P
CONVERSION
2485 F06
Figure 6. Consecutive Reading at the Same Configuration
S
7-BIT ADDRESS
CONVERSION
W ACK
SLEEP
WRITE
DATA INPUT
Sr
7-BIT ADDRESS
ADDRESS
R ACK
READ
DATA OUTPUT
P
CONVERSION
2485 F07
Figure 7. Write, Read, Start Conversion
2485fd
For more information www.linear.com/LTC2485
17
LTC2485
Applications Information
Discarding a Conversion Result and Initiating a New
Conversion with Optional Configuration Updating
on all the LTC2485s without changing the configuration
registers.
At the conclusion of a conversion cycle, a Write cycle
can be initiated. Once the Write cycle is acknowledged,
a stop (P) command initiates a new conversion. If a new
configuration is required, this data can be written into the
device and a stop command initiates a new conversion,
see Figure 8.
Synchronizing Multiple LTC2485s with the Global
Address Call
In applications where several LTC2485s are used on the
same I2C bus, all LTC2485s can be synchronized with the
global address call. To achieve this, first all the LTC2485s
must have completed the conversion cycle. The master
issues a Start, followed by the LTC2485 global address
1110111 and a Write request. All LTC2485s will be selected
and acknowledge the request. The master then sends
the write byte (Optional) and ends the Write operation
with a STOP. This will update the configuration registers
(if a write byte was sent) and initiate a new conversion
simultaneously on all the LTC2485s, as shown in Figure 9.
In order to synchronize the start of conversion without
affecting the configuration registers, the Write operation
can be aborted with a STOP. This initiates a new conversion
S
7-BIT ADDRESS
CONVERSION
W ACK
SLEEP
Easy Drive Input Current Cancellation
The LTC2485 combines a high precision delta-sigma
ADC with an automatic differential input current cancellation front end. A proprietary front-end passive sampling
network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2485 without
external amplifiers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see Automatic Input
Current Cancellation section). This unique architecture
does not require on-chip buffers enabling input signals to
swing all the way to ground and up to VCC. Furthermore,
the cancellation does not interfere with the transparent
offset and full-scale auto-calibration and the absolute accuracy (full-scale + offset + linearity) is maintained even
with external RC networks.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
WRITE (OPTIONAL)
DATA INPUT
P
CONVERSION
2485 F08
Figure 8. Start a New Conversion without Reading Old Conversion Result
SCL
SDA
LTC2485
S
LTC2485
GLOBAL ADDRESS
W ACK
ALL LTC2485s IN SLEEP
…
WRITE (OPTIONAL)
DATA INPUT
LTC2485
P
CONVERSION OF ALL LTC2485s
2485 F09
Figure 9. Synchronize the LTC2485s with the Global Address Call
18
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
Frequency Rejection Selection (CA0/f0)
The LTC2485 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz ±2% or 60Hz ±2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip configuration register (the default mode at powerup is simultaneous 50Hz/60Hz rejection).
± 4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/5120
is shown in Figure 10.
–80
–85
NORMAL MODE REJECTION (dB)
(commonly implemented as a SINC or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2485 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
2485 F10
Figure 10. LTC2485 Normal Mode Rejection
When Using an External Oscillator
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2485 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the CA0/f0 pin and turns off the internal oscillator. The chip address for CA0 is internally set HIGH. The
frequency fEOSC of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods tHEO and tLEO
are observed.
Whenever an external clock is not present at the CA0/f0 pin,
the converter automatically activates its internal oscillator
and enters the Internal Conversion Clock mode. CA0/f0
may be tied HIGH or left floating in order to set the chip
address. The LTC2485 operation will not be disturbed if
the change of conversion clock source occurs during the
sleep state or during the data output state while the converter uses an external serial clock. If the change occurs
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2485 provides better than 110dB
normal mode rejection in a frequency range of fEOSC/5120
Table 5 summarizes the duration of the conversion state
of each state and the achievable output data rate as a
function of fEOSC.
Table 5. LTC2485 State Duration
STATE
OPERATING MODE
Conversion
Internal Oscillator
External Oscillator
DURATION
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s for
CA0/f0 = External Oscillator with
Frequency fEOSC Hz (fEOSC/5120 Rejection) 1x Speed Mode
20556/fEOSCs, Output Data Rate ≤ fEOSC/20556 Readings/s for
2x Speed Mode
2485fd
For more information www.linear.com/LTC2485
19
LTC2485
Applications Information
Ease of Use
The LTC2485 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2485 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2485 automatically enters an internal reset state
when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the
conversion result.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR signal,
the LTC2485 starts a normal conversion cycle and follows
the succession of states described in Figure 1. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
When using the internal temperature sensor, if the output
code is normalized to RSDA = VPTAT/VREF, the temperature
is calculated using the following formula:
R
•V
TK = SDA REF in Kelvin
SLOPE
and
RSDA • VREF
– 273 in °C
SLOPE
where SLOPE is nominally 1.4mV/°C.
Since the PTAT signal can have an initial value variation
which results in errors in SLOPE, to achieve absolute temperature measurements, a one-time calibration is needed
to adjust the SLOPE value. The converter output of the
PTAT signal, R0SDA, is measured at a known temperature
T0 (in °C) and the SLOPE is calculated as:
TC =
R0SDA • VREF
T0 + 273
This calibrated SLOPE can be used to calculate the temperature.
If the same VREF source is used during calibration and
temperature measurement, the actual value of the VREF
is not needed to measure the temperature as shown in
the calculation below:
SLOPE =
RSDA • VREF
– 273
SLOPE
R
= SDA • ( T0 + 273) – 273
R0SDA
TC =
On-Chip Temperature Sensor
600
VCC = 5V
IM = 1
SLOPE = 1.40mV/°C
500
VPTAT (µV)
The LTC2485 contains an on-chip PTAT (proportional to
absolute temperature) signal that can be used as a temperature sensor. The internal PTAT has a typical value of 420mV
at 27°C and is proportional to the absolute temperature
value with a temperature coefficient of 420/(27 + 273) =
1.40mV/°C (SLOPE), as shown in Figure 11. The internal
PTAT signal is used in a single-ended mode referenced to
device ground internally. The 1x speed mode with automatic
offset calibration is automatically selected for the internal
PTAT signal measurement as well.
400
300
200
–60
–30
0
30
60
TEMPERATURE (°C)
90
120
2485 F11
Figure 11. Internal PTAT Signal vs Temperature
20
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
Reference Voltage Range
distinct output codes. Since the differential input current
cancellation does not rely on an on-chip buffer, current
cancellation and DC performance is maintained rail-to-rail.
The LTC2485 external reference voltage range is 0.1V
to VCC. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in nanovolts is nearly constant with reference voltage.
A reduced reference voltage will improve the converter
performance when operated with an external conversion
clock (external fO signal) at substantially higher output
data rates (see the Output Data Rate section). VREF must
be ≥1.1V to use the internal temperature sensor.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the performance
of the devices. The effect of the series resistance on the
converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
The reference input is differential. The differential reference input range (VREF = REF+ – REF–) is 100mV to VCC
and the common mode reference input range is 0V to VCC.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase rapidly. Within these limits, the LTC2485 converts the bipolar
differential input signal, VIN = IN+ – IN–, from – FS to +FS
where FS = 0.5 • VREF. Beyond this range, the converter
indicates the overrange or the underrange condition using
IREF+
RSW (TYP)
10k
ILEAK
( )
I IN+
ILEAK
I REF +
ILEAK
VIN+
RSW (TYP)
10k
VCC
=
VIN(CM) − VREF(CM)
0.5 • REQ
(
)
2
VIN 2
1.5 • VREF − VINCM + VREFCM
0.5 • VREF • DT 1.5VREF + VREF(CM) – VIN(CM)
VIN
–
=
−
−
≅
0.5 • REQ
0.5 • REQ
VREF • REQ
REQ
VREF • REQ
 REF + + REF – 
VREFCM = 
 , VREF = REF + − REF –
2


 IN+ + IN− 
VINCM = 

2


REQ = 2.71MΩ INTERNAL OSCILLATOR 60Hz MODE
REQ = 2.98MΩ INTERNAL OSCILLATOR 50Hz AND 60Hz MODE
ILEAK
VCC
ILEAK
–
VREF
AVG
AVG
VIN = IN+ − IN−
RSW (TYP)
10k
ILEAK
( )
= I IN –
where:
CEQ
12pF
(TYP)
ILEAK
IREF–
AVG
( )
VCC
IIN+
VIN–
The input and reference pins of the LTC2485 converter
are directly connected to a network of sampling capacitors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins transferring small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 12.
VCC
VREF+
IIN–
Driving the Input and Reference
RSW (TYP)
10k
ILEAK
(
)
REQ = 0.833 • 1012 / f EOSC EXTERNAL OSCILLATOR
2485 F12
DT IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
WHERE REF– IS INTERNALLY TIED TO GND
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
Figure 12. LTC2485 Equivalent Analog Input Circuit
2485fd
For more information www.linear.com/LTC2485
21
LTC2485
Applications Information
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with R­SW and CEQ (see Figure 12), a first order passive network with a time constant
τ = (RS + RSW) • CEQ. The converter is able to sample the
input signal with better than 1ppm accuracy if the sampling
period is at least 14 times greater than the input circuit time
constant τ. The sampling process on the four input analog
pins is quasi-independent so each time constant should be
considered by itself and, under worst-case circumstances,
the errors may add.
When using the internal oscillator, the LTC2485’s frontend switched-capacitor network is clocked at 123kHz
corresponding to an 8.1µs sampling period. Thus, for
settling errors of less than 1ppm, the driving source
impedance should be chosen such that τ ≤ 8.1µs/14 =
580ns. When an external oscillator of frequency fEOSC is
used, the sampling period is 2.5/fEOSC and, for a settling
error of less than 1ppm, τ ≤ 0.178/fEOSC.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization of the sensor is possible.
For many applications, the sensor output impedance
combined with external bypass capacitors produces RC
time constants much greater than the 580ns required for
1ppm accuracy. For example, a 10kΩ bridge driving a
0.1µF bypass capacitor has a time constant an order of
magnitude greater than the required maximum. Historically,
settling issues were solved using buffers. These buffers
led to increased noise, reduced DC performance (Offset/
Drift), limited input/output swing (cannot digitize signals
near ground or VCC), added system cost and increased
power. The LTC2485 uses a proprietary switching algorithm
that forces the average differential input current to zero
independent of external settling errors. This allows accurate
direct digitization of high impedance sensors without the
need of buffers (see Figures 13 to 15). Additional errors
resulting from mismatched leakage currents must also
be taken into account.
22
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current
is zero, the common mode input current (IIN++ IIN–)/2 is
proportional to the difference between the common mode
input voltage (VINCM) and the common mode reference
voltage (VREFCM).
In applications where the input common mode voltage
is equal to the reference common mode voltage, as in
the case of a balance bridge type application, both the
differential and common mode input current are zero.
The accuracy of the converter is unaffected by settling
errors. Mismatches in source impedances between IN+
and IN– also do not affect the accuracy.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VINCM and VREFCM. For a reference
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74µA (in simultaneous 50Hz/60Hz rejection mode). This
common mode input current has no effect on the accuracy
if the external source impedances tied to IN+ and IN– are
matched. Mismatches in these source impedances lead
to a fixed offset error but do not affect the linearity or fullscale reading. A 1% mismatch in 1kΩ source resistances
leads to a 15ppm shift (74µV) in offset voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the common mode input current varies proportionally with input
voltage. For the case of balanced input impedances, the
common mode input current effects are rejected by the
large CMRR of the LTC2485 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1kΩ source resistances lead
to worst-case gain errors on the order of 15ppm or 1LSB
(for 1V differences in reference and input common mode
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
voltage). Table 6 summarizes the effects of mismatched
source impedance and differences in reference/input common mode voltages.
RSOURCE
VINCM + 0.5VIN
RSOURCE
UNBALANCED INPUT
RESISTANCES
CEXT > 1nF at Both
Varying
VIN(CM) – VREF(CM) IN+ and IN–. Can
Take Large Source
Resistance with
Negligible Error
Minimize IN+ and IN–
Capacitors and Avoid Large
Source Impedance
(< 5k Recommended)
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current and offset
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and 10µV maximum offset voltage.
VINCM – 0.5VIN
IN–
CPAR
≅20pF
CEXT
2485 F13
Figure 13. An RC Network at IN+ and IN–
80
+FS ERROR (ppm)
CEXT > 1nF at Both IN+ and
IN–. Can Take Large Source
Resistance. Unbalanced
Resistance Results in an Offset
Which Can be Calibrated
VCC = 5V
= 5V
60 VREF
VIN+ = 3.75V
– = 1.25V
40 VIN
TA = 25°C
20
CEXT = 0pF
CEXT = 100pF
0
CEXT = 1nF, 0.1µF, 1µF
–20
–40
–60
–80
1
10
100
1k
RSOURCE (Ω)
10k
100k
2485 F14
Figure 14. +FS Error vs RSOURCE at IN+ and IN–
80
–FS ERROR (ppm)
CEXT > 1nF at Both
Constant
VIN(CM) – VREF(CM) IN+ and IN–. Can
Take Large Source
Resistance with
Negligible Error
CPAR
≅20pF
CEXT
LTC2485
Table 6. Suggested Input Configuration for LTC2485
BALANCED INPUT
RESISTANCES
IN+
VCC = 5V
= 5V
60 VREF
VIN+ = 1.25V
–
40 VIN = 3.75V
TA = 25°C
20
CEXT = 1nF, 0.1µF, 1µF
0
CEXT = 100pF
–20
CEXT = 0pF
–40
–60
–80
1
10
100
1k
RSOURCE (Ω)
10k
100k
2485 F15
Figure 15. –FS Error vs RSOURCE at IN+ and IN–
2485fd
For more information www.linear.com/LTC2485
23
LTC2485
Applications Information
Reference Current
In a similar fashion, the LTC2485 samples the differential
reference pins REF+ and REF– transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in two distinct situations.
For relatively small values of the external reference capacitors (CREF < 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 1nF) may be
required as reference filters in certain configurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential reference
resistance is 1MΩ which generates a full-scale (VREF/2) gain
error of 0.51ppm for each ohm of source resistance driving
the REF+ or REF– pins. For 50Hz/60Hz mode, the related
difference resistance is 1.1MΩ and the resulting full-scale
error is 0.46ppm for each ohm of source resistance driving
the REF+ and REF– pins. For 50Hz mode, the related difference resistance is 1.2MΩ and the resulting full-scale error
is 0.42ppm for each ohm of source resistance driving the
REF+ and REF– pins. When CA0/f0 is driven by an external
oscillator with a frequency fEOSC (external conversion clock
operation), the typical differential reference resistance is
0.30 • 1012/fEOSC Ω and each ohm of source resistance
driving the REF+ or REF– pins will result in 1.67 • 10–6 •
fEOSCppm gain error. The typical +FS and –FS errors for
various combinations of source resistance seen by the
REF+ or REF– pins and external capacitance connected to
that pin are shown in Figures 16-19.
In addition to this gain error, the converter INL performance is degraded by the reference source imped-
24
ance. The INL is caused by the input dependent terms
–VIN2/(VREF • REQ) – (0.5 • VREF • DT­)/REQ in the reference
pin current as expressed in Figure 12. When using internal
oscillator and 60Hz mode, every 100Ω of reference source
resistance translates into about 0.67ppm additional INL
error. When using internal oscillator and 50Hz/60Hz mode,
every 100Ω of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillator and 50Hz mode, every 100Ω of reference source
resistance translates into about 0.56ppm additional INL
error. When CA0/f0 is driven by an external oscillator
with a frequency fEOSC, every 100Ω of source resistance
driving REF+ or REF– translates into about 2.18 • 10–6 •
fEOSCppm additional INL error. Figure 20 shows the typical
INL error due to the source resistance driving the REF+
or REF– pins when large CREF values are used. The user
is advised to minimize the source impedance driving the
REF+ and REF– pins.
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (VREFCM – VINCM) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error,
which is 0.074ppm when using internal oscillator and 60Hz
mode. When using internal oscillator and 50Hz/60Hz mode,
the extra full-scale gain error is 0.067ppm. When using
internal oscillator and 50Hz mode, the extra gain error is
0.061ppm. If an external clock is used, the corresponding
extra gain error is 0.24 • 10–6 • fEOSCppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by VREF+
and VREF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
Output Data Rate
When using its internal oscillator, the LTC2485 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz, 6.25sps with a notch frequency of 50Hz and
6.82sps with the 50Hz/60Hz rejection mode. The actual
output data rate will depend upon the length of the sleep
and data output phases which are controlled by the user
and which can be made insignificantly short. When oper-
90
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
TA = 25°C
80
70
+FS ERROR (ppm)
In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 0.5µV
maximum full-scale error.
60
50
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
40
30
20
10
0
–10
500
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
TA = 25°C
0
–20
–30
+FS ERROR (ppm)
–FS ERROR (ppm)
400
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
–40
–50
–60 VCC = 5V
VREF = 5V
–70 V + = 1.25V
IN
–
–80 VIN = 3.75V
TA = 25°C
–90
10
0
1k
100
RSOURCE (Ω)
10k
100k
2485 F16
CREF = 1µF, 10µF
CREF = 0.1µF
300
200
CREF = 0.01µF
0
100k
0
200
2485 F17
600
400
RSOURCE (Ω)
800
1000
2485 F18
Figure 18. +FS Error vs RSOURCE at REF+ or REF– (Large CREF)
0
10
CREF = 0.01µF
–200
CREF = 1µF, 10µF
–300
CREF = 0.1µF
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
TA = 25°C
–400
0
200
INL (ppm OF VREF)
–100
–FS ERROR (ppm)
10k
100
Figure 17. –FS Error vs RSOURCE at REF+ or REF– (Small CREF)
–500
1k
100
RSOURCE (Ω)
Figure 16. +FS Error vs RSOURCE at REF+ or REF– (Small CREF)
10
–10
10
0
VCC = 5V
8 VREF = 5V
VIN(CM) = 2.5V
6 T = 25°C
A
4 CREF = 10µF
R = 1k
2
R = 500Ω
0
R = 100Ω
–2
–4
–6
–8
600
400
RSOURCE (Ω)
800
1000
–10
–0.5
2485 F19
Figure 19. –FS Error vs RSOURCE at REF+ or REF– (Large CREF)
–0.3
0.1
–0.1
VIN/VREF (V)
0.3
0.5
2485 F20
Figure 20. INL vs DIFFERENTIAL Input Voltage
and Reference Source Resistance for CREF > 1µF
2485fd
For more information www.linear.com/LTC2485
25
LTC2485
Applications Information
ated with an external conversion clock (CA0/f0 connected
to an external oscillator), the LTC2485 output data rate can
be increased as desired. The duration of the conversion
phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
An increase in fEOSC over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is nevertheless accompanied by two potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line frequency. In many applications, the subsequent performance
degradation can be substantially reduced by relying upon
the LTC2485’s exceptional common mode rejection and by
carefully eliminating common mode to differential mode
conversion sources in the input circuit. The user should
avoid single-ended input filters and should maintain a
very high degree of matching and symmetry in the circuits
driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used,
20
10
0
–10
The combined effect of the internal SINC4 digital filter and
of the analog and digital auto-calibration circuits determines
the LTC2485 input bandwidth. When the internal oscillator
is used with the notch set at 60Hz, the 3dB input bandwidth
is 3.63Hz. When the internal oscillator is used with the
notch set at 50Hz, the 3dB input bandwidth is 3.02Hz. If
an external conversion clock generator of frequency fEOSC
is connected to the CA0/f0 pin, the 3dB input bandwidth
is 11.8 • 10–6 • fEOSC.
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
TA = 25°C
TA = 85°C
3000
TA = 25°C
TA = 85°C
30
Input Bandwidth
3500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
40
Typical measured performance curves for output data rates
up to 25 readings per second are shown in Figures 21 to
28. In order to obtain the highest possible level of accuracy
from this converter at output data rates above 20 readings
per second, the user is advised to maximize the power
supply voltage used and to limit the maximum ambient
operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial.
+FS ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
50
the previous section provides formulae for evaluating the
effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2485 typical
performance can be inferred from Figures 14, 15, 16 and
17 in which the horizontal axis is scaled by 307200/fEOSC.
2500
2000
1500
1000
500
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
30
0
0
2485 F21
Figure 21. Offset Error vs Output Data Rate and Temperature
26
20
10
OUTPUT DATA RATE (READINGS/SEC)
30
2485 F22
Figure 22. +FS Error vs Output Data Rate and Temperature
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
–500
22
–1000
20
RESOLUTION (BITS)
24
–FS ERROR (ppm OF VREF)
0
–1500
–2000
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
TA = 25°C
TA = 85°C
–2500
–3000
–3500
0
18
TA = 25°C
TA = 85°C
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
16
14
12
20
10
OUTPUT DATA RATE (READINGS/SEC)
10
30
0
20
10
OUTPUT DATA RATE (READINGS/SEC)
2485 F24
2485 F23
Figure 23. –FS Error vs Output Data Rate and Temperature
Figure 24. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
20
22
OFFSET ERROR (ppm OF VREF)
RESOLUTION (BITS)
20
18
16
TA = 25°C
TA = 85°C
VIN(CM) = VREF(CM)
12 VCC = VREF = 5V
fO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
10
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
14
VIN(CM) = VREF(CM)
VIN = 0V
15 fO = EXT CLOCK
TA = 25°C
5
0
–5
–10
30
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
10
0
Figure 25. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
30
Figure 26. Offset Error vs Output
Data Rate and Reference Voltage
24
22
22
20
20
RESOLUTION (BITS)
RESOLUTION (BITS)
20
10
OUTPUT DATA RATE (READINGS/SEC)
2485 F26
2485 F25
18
16 VIN(CM) = VREF(CM)
VIN = 0V
f = EXT CLOCK
14 TO = 25°C
A
RES = LOG 2 (VREF/NOISERMS)
12
V = 5V, V
= 2.5V
CC
10
30
REF
VCC = VREF = 5V
0
20
10
OUTPUT DATA RATE (READINGS/SEC)
30
18
16 VIN(CM) = VREF(CM)
VIN = 0V
REF– = GND
14 fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
12
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
10
0
10
20
OUTPUT DATA RATE (READINGS/SEC)
2485 F28
2485 F27
Figure 27. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
30
Figure 28. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
2485fd
For more information www.linear.com/LTC2485
27
LTC2485
Applications Information
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2485 input bandwidth is shown in
Figure 29. When an external oscillator of frequency fEOSC
is used, the shape of the LTC2485 input bandwidth can
be derived from Figure 29, 60Hz mode curve in which
the horizontal axis is scaled by fEOSC/307200.
If the CA0/f0 pin is driven by an external oscillator of
frequency fEOSC, Figure 30 can still be used for noise
calculation if the x-axis is scaled by fEOSC/307200. For
large values of the ratio fEOSC/307200, the Figure 30 plot
accuracy begins to decrease, but at the same time the
LTC2485 noise floor rises and the noise contribution of
the driving amplifiers lose significance.
The conversion noise (600nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nV√Hz
for an infinite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2485 significantly
simplifies anti-aliasing filter requirements. Additionally,
the input current cancellation feature of the LTC2485 allows external lowpass filtering without degrading the DC
performance of the device.
When external amplifiers are driving the LTC2485, the
ADC input referred system noise calculation can be
simplified by Figure 30. The noise of an amplifier driving
the LTC2485 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass filter with a
corner frequency fi. The amplifier noise spectral density
is ni. From Figure 30, using fi as the x-axis selector, we
can find on the y-axis the noise equivalent bandwidth freqi
of the input driving amplifier. This bandwidth includes
the band limiting effects of the ADC internal calibration
and filtering. The noise of the driving amplifier referred
to the converter input and including all these effects can
be calculated as N = ni • √freqi. The total system noise
(referred to the LTC2485 input) can now be obtained by
summing as square root of sum of squares the three
ADC input referred noise sources: the LTC2485 internal
noise, the noise of the IN+ driving amplifier and the noise
of the IN– driving amplifier.
28
Normal Mode Rejection and Anti-Aliasing
The SINC4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2485’s auto-calibration circuits further simplify the
anti-aliasing requirements by additional normal mode
signal filtering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN is the notch frequency and fOUTMAX
is the maximum output data rate. In the internal oscillator mode with a 50Hz notch setting, fS = 12800Hz, with
50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch
setting fS = 15360Hz. In the external oscillator mode, fS =
fEOSC/20. The performance of the normal mode rejection
is shown in Figures 31 and 32.
In 1x speed mode, the regions of low rejection occurring
at integer multiples of fS have a very narrow bandwidth.
Magnified details of the normal mode rejection curves
are shown in Figure 33 (rejection near DC) and Figure 34
(rejection at fS = 256fN) where fN represents the notch
frequency. These curves have been derived for the external oscillator mode but they can be used in all operating
modes by appropriately selecting the fN value.
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
100
–1
50Hz AND
60Hz MODE
–2
50Hz MODE
–3
60Hz MODE
–4
–5
–6
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
INPUT SIGNAL ATTENUATION (dB)
0
60Hz MODE
10
50Hz MODE
1
0.1
0.1
1
3
0
4
5
2
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2485 F29
Figure 30. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
0
0
–10
–10
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
Figure 29. Input Signal Using the Internal Oscillator
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2485 F31
Figure 31. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch Mode
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
Figure 32. Input Normal Mode Rejection at DC
0
fN = fEOSC/5120
–20
–120
2485 F32
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
0
–10
1
10 100 1k
10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz) 2485 F30
8fN
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2485 F33
Figure 33. Input Normal Mode Rejection at DC
2485 F34
Figure 34. Input Normal Mode Rejection at fs = 256fN
2485fd
For more information www.linear.com/LTC2485
29
LTC2485
Applications Information
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figures 35, 36 and 37. Typical measured values of the
normal mode rejection of the LTC2485 operating with an
internal oscillator and a 60Hz notch setting are shown in
Figure 35 superimposed over the theoretical calculated
curve. Similarly, the measured normal mode rejection of
the LTC2485 for the 50Hz rejection mode and 50Hz/60Hz
rejection mode are shown in Figures 36 and 37.
As a result of these remarkable normal mode specifications, minimal (if any) anti-alias filtering is required in front
of the LTC2485. If passive RC components are placed in
front of the LTC2485, the input dynamic current should
be considered (see Input Current section). In this case,
the differential input current cancellation feature of the
LTC2485 allows external RC networks without significant
degradation in DC performance.
Traditional high order delta-sigma modulators, while
providing very good linearity and resolution, suffer
from potential instabilities at large input signal levels.
The proprietary architecture used for the LTC2485 third
30
order modulator resolves this problem and guarantees a
predictable stable behavior at input signal levels of up to
150% of full-scale. In many industrial applications, it is
not uncommon to have to measure microvolt level signals
superimposed on volt level perturbations and the LTC2485
is eminently suited for such tasks. When the perturbation
is differential, the specification of interest is the normal
mode rejection for large input signal levels. With a reference voltage VREF = 5V, the LTC2485 has a full-scale differential input range of 5V peak-to-peak. Figures 38 and
39 show measurement results for the LTC2485 normal
mode rejection ratio with a 7.5V peak-to-peak (150%
of full scale) input signal superimposed over the more
traditional normal mode rejection ratio results obtained
with a 5V peak-to-peak (full-scale) input signal. In Figure
38, the LTC2485 uses the internal oscillator with the notch
set at 60Hz and in Figure 39 it uses the internal oscillator
with the notch set at 50Hz. It is clear that the LTC2485
rejection performance is maintained with no compromises
in this extreme situation. When operating with large input
signal levels, the user must observe that such signals do
not violate the device absolute maximum ratings.
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
MEASURED DATA
CALCULATED DATA
–20
–40
0
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
–60
–80
–100
–120
0
15
30
45
60
75
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
MEASURED DATA
CALCULATED DATA
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2485 F35
2485 F36
Figure 35. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (60Hz Notch)
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
Figure 36. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (50Hz Notch)
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VINCM = 2.5V
TA = 25°C
–40
–60
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2485 F38
2485 F37
Figure 37. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (50Hz/60Hz Mode)
Figure 38. Measured Input Normal Mode Rejection
vs Input Frequency with Input Perturbation of 150%
Full-Scale (60Hz Notch)
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
–60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2485 F39
Figure 39. Measured Input Normal Mode Rejection
vs Input Frequency with Input Perturbation of 150%
Full-Scale (50Hz Notch)
2485fd
For more information www.linear.com/LTC2485
31
LTC2485
Applications Information
Using the 2x speed mode of the LTC2485, the device
bypasses the digital offset calibration operation to double
the output data rate. The superior normal mode rejection
is maintained as shown in Figures 31 and 32. However,
the magnified details near DC and fS = 256fN are different,
see Figures 40 and 41. In 2x speed mode, the bandwidth is
11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz
rejection mode and 12.4Hz for the 50Hz/60Hz rejection
mode. Typical measured values of the normal mode rejection of the LTC2485 operating with the internal oscillator
and 2x speed mode is shown in Figure 42.
When the LTC2485 is configured in 2x speed mode, by
performing a running average, a SINC1 notch is combined
with the SINC4 digital filter, yielding the normal mode
rejection identical as that for the 1x speed mode. The
averaging operation still keeps the output rate with the
following algorithm:
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
……
Result n = average (sample n – 1, sample n)
The main advantage of the running average is that it
achieves simultaneous 50Hz/60Hz rejection at twice the
effective output rate, as shown in Figure 43. The raw output
data provides a better than 70dB rejection over 48Hz to
62.4Hz, which covers both 50Hz ±2% and 60Hz ±2%. With
running average on, the rejection is better than 87dB for
both 50Hz ±2% and 60Hz ±2%.
Complete Thermocouple Measurement System with
Cold Junction Compensation
The LTC2485 is ideal for direct digitization of thermocouples and other low voltage output sensors. The input
has a typical offset error of 500nV (2.5µV max) offset drift
of 10nV/°C and a noise level of 600nVRMS.
Figure 45 (last page of this data sheet) is a complete type
K thermocouple meter. The only signal conditioning is a
simple surge protection network. In any thermocouple
meter, the cold junction temperature sensor must be at
the same temperature as the junction between the thermocouple materials and the copper printed circuit board
traces. The tiny LTC2485 can be tucked neatly underneath
an Omega MPJ-K-F thermocouple socket ensuring close
thermal coupling.
The LTC2485’s 1.4mV/°C PTAT circuit measures the
cold junction temperature. Once the thermocouple voltage and cold junction temperature are known, there are
many ways of calculating the thermocouple temperature
including a straight-line approximation, lookup tables or
a polynomial curve fit. Calibration is performed by applying an accurate 500mV to the ADC input derived from an
LT®1236 reference and measuring the local temperature
with an accurate thermometer as shown in Figure 44. In
calibration mode, the up and down buttons are used to
adjust the local temperature reading until it matches an
accurate thermometer. Both the voltage and temperature
calibration are easily automated.
The complete microcontroller code for this application is
available on the LTC2485 product webpage at:
http://www.linear.com
It can be used as a template for may different instruments
and it illustrates how to generate calibration coefficients
for the onboard temperature sensor. Extensive comments
detail the operation of the program. The read_LTC2485()
function controls the operation of the LTC2485 and is
listed below for reference.
32
2485fd
For more information www.linear.com/LTC2485
LTC2485
0
0
–20
–20
INPUT NORMAL REJECTION (dB)
INPUT NORMAL REJECTION (dB)
Applications Information
–40
–60
–80
–100
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (fN)
–40
–60
–80
–100
–120
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (fN)
8fN
2485 F41
2485 F40
Figure 40. Input Normal Mode Rejection 2x Speed Mode
–70
MEASURED DATA
VCC = 5V
CALCULATED DATA VREF = 5V
VINCM = 2.5V
VIN(P-P) = 5V
TA = 25°C
–20
–40
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
Figure 41. Input Normal Mode Rejection 2x Speed Mode
–60
–80
–100
–120
–80
NO AVERAGE
–90
–110
–120
–130
–140
0
25
WITH
RUNNING
AVERAGE
–100
50 75 100 125 150 175 200 225
INPUT FREQUENCY (Hz)
60
62
54 56
58
48 50
52
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2485 F43
2485 F42
Figure 42. Input Normal Mode Rejection
vs Input Frequency, 2x Speed Mode and 50Hz/60Hz Mode
Figure 43. Input Normal Mode Rejection 2x Speed Mode
5V
C8
1µF
C7
0.1µF
ISOTHERMAL
2
+
G1
NC1M4V0
LT1236
IN OUT
TRIM
GND
4
6
5
R2
2k
R7
8k
R8
1k
1
4
5
IN+
IN–
1.7k
6
7
9
10
1.7k
REF– GND
3
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
2
REF+ VCC SCL
SDA
LTC2485 CA1
CA0/f0
8
2485 F44
26.3C
Figure 44. Calibration Setup
2485fd
For more information www.linear.com/LTC2485
33
LTC2485
Applications Information
/*
LTC248X.h
Processor setup and
Lots of useful defines for configuring the LTC2481, LTC2483, and LTC2485.
*/
#include <16F73.h>
// Device
#use delay(clock=6000000)
// 6MHz clock
//#fuses NOWDT,HS, PUT, NOPROTECT, NOBROWNOUT
// Configuration fuses
#rom 0x2007={0x3F3A} // Equivalent and more reliable fuse config.
#use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port
#include “PCM73A.h”
// Various defines
#include “lcd.c”
// LCD driver functions
#define READ
0x01
#define WRITE
0x00
#define LTC248XADDR 0b01001000
// bitwise OR with address for read or write
// The one and only LTC248X in this circuit,
// with both address lines floating.
// Useful defines for the LTC2481 and LTC2485 - OR them together to make the
// 8 bit config word.
// These do NOT apply to the LTC2483.
// Select gain - 1 to 256 (also depends on speed setting)
// Does NOT apply to LTC2485.
#define GAIN1 0b00000000
// G = 1
(SPD = 0), G = 1
#define GAIN2 0b00100000
// G = 4
(SPD = 0), G = 2
#define GAIN3 0b01000000
// G = 8
(SPD = 0), G = 4
#define GAIN4 0b01100000
// G = 16 (SPD = 0), G = 8
#define GAIN5 0b10000000
// G = 32 (SPD = 0), G = 16
#define GAIN6 0b10100000
// G = 64 (SPD = 0), G = 32
#define GAIN7 0b11000000
// G = 128 (SPD = 0), G = 64
#define GAIN8 0b11100000
// G = 256 (SPD = 0), G = 128
(SPD
(SPD
(SPD
(SPD
(SPD
(SPD
(SPD
(SPD
=
=
=
=
=
=
=
=
1)
1)
1)
1)
1)
1)
1)
1)
// Select ADC source - differential input or PTAT circuit
#define VIN
0b00000000
#define PTAT
0b00001000
// Select rejection frequency - 50, 55, or 60Hz
#define R50
0b00000010
#define R55
0b00000000
#define R60
0b00000100
// Select speed mode
#define SLOW
0b00000000 // slow output rate with autozero
#define FAST
0b00000001 // fast output rate with no autozero
34
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
/*
LTC2485.c
Basic voltmeter test program for LTC2485
Reads LTC2485, converts result to volts,
and prints voltage to a 2 line by 16 character LCD display.
Mark Thoren
Linear Technology Corporation
June 23, 2005
Written for CCS PCM compiler, Version 3.182
*/
#include “LTC248X.h”
/*** read_LTC2485() ************************************************************
This is the function that actually does all the work of talking to the LTC2485.
Arguments:
addr - device address
config - configuration bits for next conversion
Returns:
zero if conversion is in progress,
32 bit signed integer LTC2485 output word.
the i2c_xxxx() functions do the following:
void i2c_start(void): generate an i2c start or repeat start condition
void i2c_stop(void): generate an i2c stop condition
char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack
boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device
These functions are very compiler specific, and can use either a hardware i2c
port or software emulation of an i2c port. This example uses software emulation.
A good starting point when porting to other processors is to write your own
i2c functions. Note that each processor has its own way of configuring
the i2c port, and different compilers may or may not have built-in functions
for the i2c port.
When in doubt, you can always write a “bit bang” function for troubleshooting
purposes.
The “fourbytes” structure allows byte access to the 32 bit return value:
struct fourbytes
{
int8 te0;
int8 te1;
int8 te2;
int8 te3;
};
//
//
//
//
//
//
Define structure of four consecutive bytes
To allow byte access to a 32 bit int or float.
The make32() function in this compiler will
also work, but a union of 4 bytes and a 32 bit int
is probably more portable.
2485fd
For more information www.linear.com/LTC2485
35
LTC2485
Applications Information
*******************************************************************************/
signed int32 read_LTC2485(char addr, char config)
{
struct fourbytes // Define structure of four consecutive bytes
{
// To allow byte access to a 32 bit int or float.
int8 te0;
//
int8 te1;
// The make32() function in this compiler will
int8 te2;
// also work, but a union of 4 bytes and a 32 bit int
int8 te3;
// is probably more portable.
};
union
{
signed int32 bits32;
struct fourbytes by;
} adc_code;
//
//
//
//
//
adc_code.bits32
adc_code.by.te0
adc_code.by.te1
adc_code.by.te2
adc_code.by.te3
all 32 bits
byte 0
byte 1
byte 2
byte 3
// Start communication with LTC2485:
i2c_start();
if(i2c_write(addr | WRITE))// If no acknowledge, return zero
{
i2c_stop();
return 0;
}
i2c_write(config);
i2c_start();
i2c_write(addr | READ);
adc_code.by.te3 = i2c_read();
adc_code.by.te2 = i2c_read();
adc_code.by.te1 = i2c_read();
adc_code.by.te0 = i2c_read();
i2c_stop();
return adc_code.bits32;
} // End of read_LTC2485()
/*** initialize() **************************************************************
Basic hardware initialization of controller and LCD, send Hello message to LCD
*******************************************************************************/
void initialize(void)
{
// General initialization stuff.
setup_adc_ports(NO_ANALOGS);
setup_adc(ADC_OFF);
setup_counters(RTCC_INTERNAL,RTCC_DIV_1);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
lcd_init();
delay_ms(6);
printf(lcd_putc, “Hello!”);
delay_ms(500);
} // End of initialize()
36
// Initialize LCD
// Obligatory hello message
// for half a second
2485fd
For more information www.linear.com/LTC2485
LTC2485
Applications Information
/*** main() ********************************************************************
Main program initializes microcontroller registers, then reads the LTC2481
repeatedly
*******************************************************************************/
void main()
{
signed int32 x, y;
// Integer result from LTC2481
float voltage;
// Variable for floating point math
int16 timeout;
initialize();
while(1)
{
delay_ms(1);
//
//
//
//
//
// Hardware initialization
// Pace the main loop to something more than 1 ms
This is a basic error detection scheme. The LTC2485 will never take more than
163.5ms, 149.9ms, or 136.5ms to complete a conversion in the 50Hz, 55Hz, and 60Hz
rejection modes, respectively.
If read_LTC2485() does not return non-zero within this time period, something
is wrong, such as an incorrect i2c address or bus conflict.
if((x = read_LTC2485(LTC248XADDR, VIN | R50 | SLOW)) != 0)
{
// No timeout, everything is okay
timeout = 0;
// reset timer
x ^= 0x80000000;
// Invert MSB, result is 2’s complement
voltage = (float) x;
// convert to float
voltage = voltage * 5.0 / 2147483648.0;// Multiply by Vref, divide by 2^31
lcd_putc(‘\f’);
// Clear screen
lcd_gotoxy(1,1);
// Goto home position
printf(lcd_putc, “%01.6f”, voltage); // Display voltage
}
else
{
++timeout;
}
if(timeout > 200)
{
timeout = 200;
// Prevent rollover
lcd_gotoxy(1,1);
printf(lcd_putc, “ERROR - TIMEOUT”);
delay_ms(500);
}
} // End of main loop
} // End of main()
2485fd
For more information www.linear.com/LTC2485
37
LTC2485
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
DD Package
10-Lead
Plastic
DFN (3mm
3mm)× 3mm)
10-Lead Plastic
DFN×(3mm
(Reference
LTC DWG
# 05-08-1699
Rev C) Rev C)
(Reference
LTC
DWG # 05-08-1699
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.125
TYP
6
0.40 ± 0.10
10
1.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.75 ±0.05
0.00 – 0.05
5
1
(DD) DFN REV C 0310
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
38
2485fd
For more information www.linear.com/LTC2485
LTC2485
Revision History
REV
DATE
DESCRIPTION
B
11/09
Update Tables 2 and 3
C
7/10
D
10/14
(Revision history begins at Rev B)
PAGE NUMBER
15
Revised Typical Application drawing
1
Added text to I2C Interface section
12
Clarified performance vs fO frequency, reduced external oscillator maximum frequency to 1MHz.
5, 8, 26, 27
Clarified temperature sensor performance.
1, 2
Added underrange note to Table 3.
15
2485fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2485
39
LTC2485
Typical Application
5V
C8
1µF
PIC16F73
C7
0.1µF
ISOTHERMAL
1.7k
1.7k
3
R2
2k
4
2
REF
IN+
VCC
LTC2485
SCL
SDA
6
7
–
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
5
IN
10
CA1 GND REF– CAO/fO
9
8
3
5V
D7
D6
2 × 16 CHARACTER
D5
LCD DISPLAY
D4
(OPTREX DMC162488
EN
OR SIMILAR)
RW
CONTRAST
GND D0 D1 D2 D3 RS
VCC
5V
1
R6
5k
2
3
5V
18
17
16
15
14
13
12
11
28
27
26
25
24
23
22
21
7
6
5
4
3
2
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
VDD
OSC1
OSC2
MCLR
20
C6
0.1µF
9
5V
Y1
6MHz
10
R1
1 10k
D1
BAT54
5V
9
VSS
19
VSS
2485 F45
R3
10k
CALIBRATE
2
1
DOWN
R4
10k
R5
10k
UP
Figure 45. Complete Type K Thermocouple Meter
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LT1790
Micropower SOT-23 Low Dropout Reference Family
0.05% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency ∆∑ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error,
200µA
LTC2410
24-Bit, No Latency ∆∑ ADC with Differential Inputs
0.8µVRMS Noise, 2ppm INL
LTC2411/LTC2411-1
24-Bit, No Latency ∆∑ ADCs with Differential Inputs in MSOP
1.45µVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz
Rejection (LTC2411-1)
LTC2413
24-Bit, No Latency ∆∑ ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2415/LTC2415-1
24-Bit, No Latency ∆∑ ADCs with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2414/LTC2418
8-/16-Channel 24-Bit, No Latency ∆∑ ADCs
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200µA
LTC2440
High Speed, Low Noise 24-Bit ∆∑ ADC
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2480
16-Bit ∆∑ ADC with Easy Drive Inputs, 600nV Noise,
Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2482/LTC2484
LTC2481
16-Bit ∆∑ ADC with Easy Drive Inputs, 600nV Noise,
I2C Interface, Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2483/LTC2485
LTC2482
16-Bit ∆∑ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2484
LTC2483
16-Bit ∆∑ ADC with Easy Drive Inputs, and I2C Interface
Pin Compatible with LTC2481/LTC2485
LTC2484
24-Bit ∆∑ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2482
40 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2485
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2485
2485fd
LT 1014 REV D • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2005