Microsemi DRF1300 0912 Mosfet push-pull hybrid Datasheet

DRF1300
500V, 30A, 30MHz
MOSFET Push-Pull Hybrid
IN
The DRF1300 is a push-pull hybrid containing two high power gate
drivers and two power MOSFETs. It was designed to provide the system designer increased flexibility, higher performance, and lowered cost
over a non-integrated solution. This low parasitic approach, coupled
IN
with the Schmitt trigger input, Kelvin signal ground, Anti-Ring function
Invert and Non-invert select pin provide improved stability and control in
Kilowatt to Multi-Kilowatt, High Frequency ISM applications.
D
S
D
DRIVER 30A
MOSFETS
FEATURES
S
TYPICAL APPLICATIONS
• Switching Frequency: DC TO 30MHz
• Switching Speed 3-4ns
• Class C, D and E RF Generators
• Inverting Non-Inverting Select
• BVds = 500V
• Switch Mode Power Amplifiers
• Low Pulse Width Distortion
• Ids = 30A max. Per-section
• HV Pulse Generators
• Single Power Supply (Per Section)
• Rds(on) ≤ .24 Ohm
• 1V CMOS Schmitt Trigger Input 1V
• Ultrasound Transducer Drivers
• PD = 550W Per-section
• Acoustic Optical Modulators
Hysteresis
• RoHS Compliant
Driver Absolute Maximum Ratings
Symbol
VDD
Parameter
Ratings
Supply Voltage
Unit
15
V
IN, FN
Input Single Voltages
-.7 to +5.5
IO PK
Output Current Peak
8
A
TJMAX
Operating Temperature
175
°C
Driver Specifications
Parameter
Min
VDD
Supply Voltage
10
IN
Input Voltage
3
Typ
Max
15
5
Unit
V
IN(R)
Input Voltage Rising Edge
3
IN(F)
Input Voltage Falling Edge
3
IDDQ
Quiescent Current
2
mA
Output Current
8
A
Ciss
Input Capacitance
3
RIN
Input Parallel Resistance
IO
ns
1
MΩ
VT(ON)
Input, Low to High Out (See Truth Table)
0.8
1.1
VT(OFF)
Input, High to Low Out (See Truth Table)
1.9
2.2
TDLY
Time Delay (throughput)
38
tr
Rise Time
5
tf
Fall Time
5
Microsemi Website - http://www.microsemi.com
V
ns
ns
050-4971 Rev E 12-2009
Symbol
DRF1300
Driver Output Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Cout
Output Capacitance
Rout
Output Resistance
.8
Ω
Lout
Output Inductance
3
nH
FMAX
Operating Frequency CL = 3000nF + 50Ω
30
FMAX
Operating Frequency RL = 50Ω
50
2500
pF
MHz
Driver Thermal Characteristics
Symbol
Parameter
Min
Typ
RθJC
Thermal Resistance Junction to Case
1.5
RθJHS
Thermal Resistance Junction to Heat Sink
2.5
TJSTG
Storage Temperature
PDJHS
Maximum Power Dissipation @ TSINK = 25°C
60
PDJC
Total Power Dissipation @ TC = 25°C
100
Max
Unit
°C/W
°C
-55 to 150
W
MOSFET Absolute Maximum Rating (Per-Section)
Symbol
BVDSS
ID
RDS(on)
Tjmax
Parameter
Min
Drain Source Voltage
500
Typ
Max
V
Continuous Drain Current THS = 25°C
30
Drain-Source On State Resistance
Unit
0.24
Operating Temperature
A
Ω
175
°C
Max
Unit
MOSFET Dynamic Characteristics (Per-Section)
Symbol
Parameter
Min
Typ
CISS
Input Capacitance
1800
Coss
Output Capacitance
335
Crss
Reverse Transfer Capacitance
75
pF
MOSFET Thermal Characteristics (Total Package)
Symbol
Parameter
Min
Typ
RθJC
Junction to Case Thermal Resistance
.06
RθJHS
Junction to Heat Sink Thermal Resistance
.140
TJSTG
Storage Junction Temperature
Max
°C/W
°C
-55 to 150
PDHS
Maximum Power Dissipation @ TSINK = 25°C
1.07
PDC
Total Power Dissipation @ TC = 25°C
2.5
Unit
KW
Section A and B Output Switching Performance
Symbol
Characteristic
Typ
Max
TON
Leading Edge 10% to 90%
2
3
4
TOFF
Trailing Edge 10% to 90%
45
TBD
49
TDLY(ON)
Total Throughput Delay Time, ON
45
TBD
47
TDLY(OFF)
Total Throughput Delay Time, OFF
49
50
51
∆TDLY(ON)
Delta TON Delay between Section A and B
-0.5
0
1.5
∆TDLY(OFF)
Delta TOFF Delay between Section A and B
0
0.6
1.3
Microsemi reserves the right to change, without notice, the specifications and information contained herein.
050-4971 Rev E 12-2009
Min
Typ
ns
DRF1300
Figure 1, DRF1300 Circuit Diagram
The DRF1300 is configured as a Push Pull Hybrid incorporating two independent channels configured with a common source each consisting of a
driver, a high voltage MOSFET and by-pass capacitors. The function of the by-pass capacitors C1 and C2 is to reduce the internal parasitic loop
inductance. This coupled with the tight geometry of the hybrid allows optimal gate drive to the MOSFET. This low parasitic approach coupled
with the Schmitt trigger input (IN), Kelvin signal ground (SG) and the Anti-Ring function; provide improved stability and control in Kilowatt to MultiKilowatt high frequency applications. The IN pin should be referenced to the Kelvin Ground (SG) and is applied to a Schmitt Trigger. The SG
pin is a Kelvin return for the IN pin only. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary
circuitry designed specifically for ring abatement. To further increase the utility of the device the driver die and the MOSFET die are adjacent die
selected. This provides a very close match in the turn on and propagation delays.
The test circuit illustrated in Figure 2 was used to evaluate the DRF1300 (available as an evaluation board DRF13XX/EVALSW.) The input
control signal is applied via IN and SG pins using RG188. This provides excellent noise immunity and control of the signal ground currents.
The +VDD inputs (pins 2, 6, 8 and 12) should be heavily by-passed by 1uF capacitors as close to the pins as possible. The capacitors used
for this function must be capable of supporting the RMS currents and frequency of the gate load. RL set for IDM at VDS max this load is used to
evaluate the output performance.
Microsemi’s products are covered by one or more of U.S. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583
4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743, 7,352,045 5,283,201 5,801,417 5,648,283 7,196,634 6,664,594 7,157,886 6,939,743 7,342,262
and foreign patents. US and Foreign patents pending. All Rights Reserved.
050-4971 Rev E 12-2009
Figure 2, DRF1300 Test Circuit
DRF1300
050-4971 Rev E 12-2009
Pin Assignments
Pin 1
Ground
Pin 2
U1 +Vdd
Pin 3
U1 FN
Pin 4
U1 IN
Pin 5
U1 SG
Pin 6
U1 +Vdd
Pin 7
Ground
Pin 8
U2 +Vdd
Pin 9
U2 FN
Pin 10
U2 IN
Pin 11
U2 SG
Pin 12
U2 +Vdd
None of the inputs to U1 or U2 of the DRF1300 are isolated for direct connection to a ground referenced power
supply or control circuitry. Isolation appropriate to the application is the responsibility of the end user. It
is imperative that high output currents be restricted to the Source (14, 16, 18) and Drain (15, 17) pins by design.
See DRF100 for more information on Driver IC used in the device.
The Function (FN, pin 3 or pin 9) is the invert or non-invert select Pin, it is Internally held high.
Truth Table * Referenced to SG
FN (pin 3)
IN (pin 4)
MOSFET
HIGH
HIGH
ON
HIGH
LOW
OFF
LOW
HIGH
OFF
LOW
LOW
ON
Truth Table * Referenced to SG
FN (pin 9)
IN (pin 10)
MOSFET
Pin 13
Ground
Pin 14
Source
HIGH
HIGH
ON
Pin 15
U2 Drain
HIGH
LOW
OFF
Pin 16
Source
LOW
HIGH
OFF
Pin 17
U1 Drain
LOW
LOW
ON
Pin 18
Source
All dimensions are ± .005
Figure 4, DRF1300 Mechanical Outline
Similar pages