Freescale MMM6035 Quad-band gsm/gprs pa module with integrated power control Datasheet

Freescale Semiconductor
Advance Information
Document Number: MMM6035/D
Rev. 2.4, 10/2005
MMM6035
Package Information
Plastic Package
Case 1561
(6 x 6 mm Module)
MMM6035
Quad-Band GSM/GPRS PA
Module with Integrated Power
Control
1
Introduction
The MMM6035 is a 50 Ω Power Amplifier module for
quad-, tri-, and dual-band GSM handset applications,
functioning over the GSM850, EGSM, DCS, and PCS
frequency bands. This module is compatible with
GSM/GPRS operating modes (up to 50% duty cycle). To
simplify radio front-end design requirements, the power
control function is integrated, removing the need for
directional couplers and detector diodes. GSM burst
shaping and power control is integrated on an internal
control SmartMOS™ IC. The analog power control
signal is smoothed by a low-pass filter included in the
internal control SmartMOS chip, allowing over 45 dB
dynamic range to be achieved.
Ordering Information
Device
Device Marking or
Operating
Temperature Range
Package
MMM6035
MMM6035
Module
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Functional Block Diagram . . . . . . . . . . . . . . . 2
3 Electrical Characteristics . . . . . . . . . . . . . . . 3
4 RF Specifications . . . . . . . . . . . . . . . . . . . . . . 4
5 Input/Output ESD Specifications . . . . . . . . . 9
6 Application Information . . . . . . . . . . . . . . . . 11
7 Design Information . . . . . . . . . . . . . . . . . . . . 14
8 Package Information . . . . . . . . . . . . . . . . . . 18
9 Signal Description . . . . . . . . . . . . . . . . . . . . 20
10Product Documentation . . . . . . . . . . . . . . . 21
The MMM6035 also prevents degradation of switching
transients, regardless of battery conditions, due to an
internal anti-saturation detection feature. Transmit
Enable and Band Select functions are controlled through
0 to 2.8 V logic inputs. These functions are also
compatible with 0 to 1.8 V logic inputs.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Functional Block Diagram
2
Functional Block Diagram
Power Control IC
MATCH
TXIN_HB
MATCH
PRE
DRIVER
VD_OUT
MATCH
DRIVER
FINAL
MATCH
VREG_PA
VAPC
TXOUT_HB
VREG_PA
LB_HB_B
PRE
DRIVER
DRIVER
FINAL
MATCH
MATCH
VDD2_LB
MATCH
VDD1_LB
TXIN_LB
VBAT
VREG
VRAMP
TX_EN
LB_HB
VDD3_HB_DEC
VDD2_HB
VDD1_HB
Figure 1 is a functional block diagram of the quad-band (GSM850, EGSM, DCS, and PCS power amplifier
module.
MATCH
TXOUT_LB
Figure 1. Functional Block Diagram
MMM6035 Advance Information, Rev. 2.4
2
Freescale Semiconductor
Electrical Characteristics
3
Electrical Characteristics
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Drain Supply Voltages
VDD
5.5
V
Power Control IC Supply Voltage
VBAT
5.5
V
External Regulated DC Supply Voltage
VREG
5.5
V
RF Input Power
Pin
11
dBm
Operating Temperature Range
TA
-20 to 85
°C
Storage Temperature
Tstg
-55 to 150
°C
Junction Temperature
TJ
150
°C
MSL
3
Rth
20
Moisture Sensitivity Level
(Meets lead-free reflow profiles with peak temperature of 260 °C)
Thermal Resistance (junction to mounting base)
°C/W
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Recommended Operating
Conditions and Electrical Characteristics tables.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Min
Typ
Max
Unit
External Regulated DC Supply Voltage
VREG
2.6
2.8
3.0
V
Power Control IC Supply Voltage
VBAT
3.1
-
4.5
V
Pin
3.0
-
9.0
dBm
Mode Control Low Voltage (TX_EN, LB_HB)
0
-
0.4
V
Mode Control High Voltage (TX_EN, LB_HB)
1.4
-
VREG
V
0.1
-
2.2
V
RF Input Power
Power Control Ramp Voltage
VRAMP
Table 3. DC Characteristics
(VREG = 2.6 to 3 V, TA = -20 to 85° C)
Characteristic
External Regulate DC Supply Current
TX_EN, LB_HB high
Standby Leakage Current
Include current on all pins
TX_EN, LB_HB low
VRAMP = 0 V, Vreg = 2.8 V, VBAT = 4.5 V, TA = 85° C
Mode Control Input
Input Low
Input High
Symbol
Min
Typ
Max
Unit
Ireg
-
5
10
mA
ILKG
-
-
50
µA
Imci(L)
Imci(H)
-0.5
-
-
50
µA
MMM6035 Advance Information, Rev. 2.4
Freescale Semiconductor
3
RF Specifications
Table 3. DC Characteristics (continued)
(VREG = 2.6 to 3 V, TA = -20 to 85° C)
Characteristic
Mode Control Input Resistance (High State)
Resistance to GND
Min
Typ
Max
Unit
Rmci
-
250
-
kΩ
IRAMP(L)
IRAMP(H)
-0.5
-
-
50
µA
Vramp Input Current
VRAMP = 0 V
Vramp = 2.2 V
4
Symbol
RF Specifications
Table 4. Mode GMSK Cellular Band Specifications
(TXIN_LB = 3.0 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 0 V,
VREG = 2.8 V, TX_EN = 2.8 V, TA = 25°C ±5° C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
F0
824
-
849
MHz
PO(H)
34.2
34.9
-
dBm
PO(HX)
32.2
-
-
dBm
Power Added Efficiency @ PO(H)
PAE
46
52
-
%
Current Consumption at Low Output Power (PO set to 6.0 dBm)
IDD(L)
-
-
150
mA
Forward Isolation (VRAMP = 0 V, TX_EN = 0 V) over VRNG,
TRNG
Iso1
-
-
-20
dBm
Harmonics level over VRNG, TRNG
2 F0
3 F0
-
-
-10
-10
dBm
NRx1 FRX =
869-894 MHz
-
-
-82
dBm
Input VSWR
ΓIN
-
16
-
dB
Second Harmonic Leakage at DCS/PCS over VRNG, TRNG at
High VRAMP
Xtalk
-
-
-15
dBm
Load mismatch stability
All angles
Set Vramp where Po(H) ≤ 34.2 dBm into 50 Ω load
All spurious < -36 dBm, RBW = 3 MHz
VSWR
6:1
-
-
Load mismatch ruggedness
All angles
Set Vramp where Po(H) ≤ 34.2 dBm into 50 Ω load
No damage, no degradation
VSWR
20:1
-
-
RPC
35
-
-
Operating Frequency
Output Power at High VRAMP
Output Power over VRNG, TRNG at High VRAMP
Tx Noise in Rx Cellular Band
@ PO=PO(H) RBW = 100 kHz
Power Control Range over VRNG, TRNG
dB
MMM6035 Advance Information, Rev. 2.4
4
Freescale Semiconductor
RF Specifications
Table 5. Mode GMSK E-GSM Band Specifications
(TXIN_LB = 3.0 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 0 V,
VREG = 2.8 V, TX_EN = 2.8 V, TA = 25° C ±5° C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
F0
880
-
915
MHz
PO(H)
34.2
34.9
-
dBm
PO(Hx)
32.2
-
-
dBm
PAE
50
56
-
%
IDD(L)
-
-
150
mA
Forward Isolation (VRAMP = 0 V, TX_EN = 0 V) over VRNG,
TRNG
Iso1
-
-
-20
dBm
Harmonics level over VRNG, TRNG
2 F0
3 F0
-
-
-10
-10
dBm
Operating Frequency
Output Power at High VRAMP
Output Power over VRNG, TRNG at High VRAMP
Power Added Efficiency @ PO(H)
Current Consumption at Low Output Power (PO set to 6.0 dBm)
Tx Noise in Rx E-GSM Band @ PO = PO(H) RBW =
100 kHz
NRx1 FRX = 925-935 MHz
NRx2 FRX = 935-960 MHz
dBm
-
-
-77
-82
Input VSWR
ΓIN
-
12
-
dB
Second Harmonic Leakage at DCS/PCS over VRNG, TRNG at
High VRAMP
Xtalk
-
-
-15
dBm
Load mismatch stability
All angles
Set Vramp where Po(H) ≤ 34.2 dBm into 50 Ω load
All spurious < -36 dBm, RBW = 3 MHz
VSWR
6:1
-
-
Load mismatch ruggedness
All angles
Set Vramp where Po(H) ≤ 34.2 dBm into 50 Ω load
No damage, no degradation
VSWR
20:1
-
-
RPC
35
-
-
Power Control Range over VRNG, TRNG
dB
Table 6. Mode GMSK DCS Band Specifications
(TXIN_HB = 3 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 2.8 V,
VREG = 2.8 V, TX_EN = 2.8 V, TA = 25° C ±5° C unless otherwise noted)
Characteristic
Operating Frequency
Output Power at High VRAMP
Output Power over VRNG, TRNG at High VRAMP
Power Added Efficiency @ PO(H)
Current Consumption at Low Output Power (PO set to 1.5 dBm)
Forward Isolation (VRAMP = 0 V, TX_EN = 0 V) over VRNG,
TRNG
Symbol
Min
Typ
Max
Unit
F0
1710
-
1785
MHz
PO(H)
31.5
33.0
-
dBm
PO(Hx)
29.5
-
-
dBm
PAE
40
46
-
%
IDD(L)
-
-
150
mA
Iso1
-
-
-28
dBm
MMM6035 Advance Information, Rev. 2.4
Freescale Semiconductor
5
RF Specifications
Table 6. Mode GMSK DCS Band Specifications (continued)
(TXIN_HB = 3 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 2.8 V,
VREG = 2.8 V, TX_EN = 2.8 V, TA = 25° C ±5° C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
2F0
3F0
-
-
-10
-10
dBm
NRx1 FRX =
1805-1880
MHz
-
-
-75
dBm
ΓIN
-
16
-
dB
Load mismatch stability
All angles
Set Vramp where Po(H) ≤ 31.5 dBm into 50 Ω load
All spurious < -30 dBm, RBW = 3 MHz
VSWR
6:1
-
-
Load mismatch ruggedness
All angles
Set Vramp where Po(H) ≤ 34.2 dBm into 50 Ω load
No damage, no degradation
VSWR
20:1
-
-
RPC
35
-
-
Harmonics level over VRNG, TRNG
Tx Noise in Rx DCS Band @ PO = PO(H)
RBW = 100 kHz
Input VSWR
Power Control Range over VRNG, TRNG
dB
Table 7. Mode GMSK PCS Band Specifications
(TXIN_HB = 3 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 2.8 V,
VREG = 2.8 V, TX_EN = 2.8 V, TA = 25° C ±5° C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
F0
1850
-
1910
MHz
PO(H)
31.5
32.8
-
dBm
PO(Hx)
29.5
-
-
dBm
PAE
40
46
-
%
IDD(L)
-
-
150
mA
Forward Isolation (VRAMP = 0 V, TX_EN = 0 V) over VRNG,
TRNG
Iso1
-
-
-28
dBm
Harmonics level over VRNG, TRNG
2F0
3F0
-
-
-10
-10
dBm
NRx1 FRX =
1930 -1990
MHz
-
-
-75
dBm
ΓIN
-
15
-
dB
VSWR
6:1
-
-
Operating Frequency
Output Power at High VRAMP
Output Power over VRNG, TRNG at High VRAMP
Power Added Efficiency @ PO(H)
Current Consumption at Low Output Power (PO set to 1.5 dBm)
Tx Noise in Rx PCS Band @ PO = PO(H)
RBW = 100 kHz
Input VSWR
Load mismatch stability
All angles
Set Vramp where Po(H) ≤ 31.5 dBm into 50 Ω load
All spurious < -30 dBm, RBW = 3 MHz
MMM6035 Advance Information, Rev. 2.4
6
Freescale Semiconductor
RF Specifications
Table 7. Mode GMSK PCS Band Specifications (continued)
(TXIN_HB = 3 dBm, VBAT = 3.6 V, VRAMP = 0.1 to 2.2 V pulsed, Period = 4.6 ms, Duty Cycle = 25%, LB_HB = 2.8 V,
VREG = 2.8 V, TX_EN = 2.8 V, TA = 25° C ±5° C unless otherwise noted)
Characteristic
Load mismatch ruggedness
All angles
Set Vramp where Po(H) ≤ 34.2 dBm into 50 Ω load
No damage, no degradation
Power Control Range over VRNG, TRNG
Symbol
Min
Typ
Max
VSWR
20:1
-
-
RPC
35
-
-
Unit
dB
Table 8. Power Control Specifications
(VREG = 2.8 V, Vrng = 3.0 to 4.5 V, -20 to 85° C)
Characteristic
Conditions
Symbol
Min
Typ
Max
Unit
VBAT = 3.6 V
TA = 25° C, Time to
reach stable VD_OUT
after 0.3 V VRAMP step
twu
-
12
-
µs
Vramp Input Voltage Offset
Voltage at which
VD_OUT rises above
0V
Voffset1
0.18
0.2
-
V
VD_OUT vs. VRAMP Slope
VBAT = 3.6 V
TA = 25° C, VRAMP >
VOffset
Vslope1
-
2.0
-
V/V
VBAT = 3.6 V
TA = 25° C, Po>5 dBm
for TX CEL and EGSM,
Po>0 dBm for TX DCS
and PCS
Po_slope1
-
-
240
dB/V
VRAMP Controller Enable Threshold
VBAT = 3.6 V
TA = 25° C, Rising
VRAMP
Vctrl(R)
-
160
-
mV
VRAMP Controller Disable Threshold
VBAT = 3.6 V
TA = 25° C, Falling
VRAMP
Vctrl(F)
-
140
-
mV
Smoothing Filter Bandwidth (3 dB cutoff
frequency)
VBAT = 3.6 V
TA = 25° C
BW
vramp
-
200
-
kHz
Smoothing Filter Attenuation (Atten at 1
MHz)
VBAT = 3.6 V
αvramp
-
30
-
dB
Smoothing Filter Rise Time (Vdout rise
time between 10% and 90% with VRAMP
step of Voffset 50 mV)
VBAT = 3.6 V
TA = 25° C
tr
-
2.5
-
µs
Wake-up Time
Po versus VRAMP Slope
MMM6035 Advance Information, Rev. 2.4
Freescale Semiconductor
7
RF Specifications
Table 8. Power Control Specifications (continued)
(VREG = 2.8 V, Vrng = 3.0 to 4.5 V, -20 to 85° C)
Characteristic
Conditions
Symbol
Min
Typ
Max
Unit
Pout variation versus Temp
Vramp adj for Pout(H)-10 dB
< Pout < Pout(H)
Vramp adj for Pout(H)-20 dB
< Pout < Pout(H)-10 dB
Vramp adj for Pout(H)-30 dB
< Pout < Pout(H)-20 dB
VBAT = 3.6 V
TA = 25° C
∆Po(H)_T
-1.5
-
1.5
dB
∆Po(M)_T
-2.0
-
2.0
dB
∆Po(L)_T
-4.0
-
4.0
dB
Pout variation versus Freq
Vramp set for Power(H) at 836.5 MHz
VBAT = 3.6 V
TA = 25° C
∆Po_CELL_f
-0.5
-
0.5
dB
∆Po_EGSM_f
-0.5
-
0.5
dB
∆Po_DCS_f
-0.5
-
0.5
dB
-0.5
-
0.5
dB
Vramp set for Power(H) at 897.5 MHz
Vramp set for Power(H)
at 1747.5 MHz
∆Po_PCS_f
Vramp set for Power(H) at 1880 MHz
1
See Figure 4.
MMM6035 Advance Information, Rev. 2.4
8
Freescale Semiconductor
Input/Output ESD Specifications
5
Input/Output ESD Specifications
The MMM6035 meets Class 1B and Class 1C for the Human Body Model (HBM) Electrostatic Discharge
(ESD) classification and it meets Class M2 for the Machine Model (MM) ESD classification. Table 9 and
Table 10 show the ESD immunity level for each MMM6035 pin. The numbers shown in Table 9 and
Table 10 specify the ESD threshold level for each pin where the I-V curve between the pin and ground
begins to show degradation.
Table 9. ESD Human Body Model: EOS/ESD-S5.1 (Pin to Ground Stress)
Pin Number-Name
1 - GND
450 Volts
500 Volts
750 Volts
1000 Volts
1250 Volts
2000 Volts
NA
NA
NA
NA
NA
NA
2 - VDD2_HB
X
3 - VDD1_HB
X
4 - Vapc
X
5 - TXIn_HB
X
6 - TXIn_LB
X
7 - VDD1_LB
X
8 - VDD2_LB
X
9 - GND
NA
NA
NA
NA
NA
NA
10 - GND
NA
NA
NA
NA
NA
NA
11 - TXOut_LB
X
12 - Vreg_PA
X
13 - VD_OUT
X
14 - Vramp
X
15 - TXEn
X
16 - LB_HB
X
17 - Vreg
X
18 - Vbat
X
19 - VD3_HB_DEC
X
20 - TXOut_HB
X
21 - GND
NA
NA
NA
NA
NA
NA
22 - GND
NA
NA
NA
NA
NA
NA
MMM6035 Advance Information, Rev. 2.4
Freescale Semiconductor
9
Input/Output ESD Specifications
Table 10. ESD Machine Model: EOS/ESD-S5.1, From 50 V up to 150 V (Destruction Voltage)
Pin Number/Name
1 - GND
50 Volts
75 Volts
100 Volts
150 Volts
200 Volts
NA
NA
NA
NA
NA
2 - VDD2_HB
X
3 - VDD1_HB
X
4 - Vapc
X
5 - TXIn_HB
X
6 - TXIn_LB
X
7 - VDD1_LB
X
8 - VDD2_LB
X
9 - GND
NA
NA
NA
NA
NA
10 - GND
NA
NA
NA
NA
NA
11 - TXOut_LB
X
12 - Vreg_PA
X
13 - VD_OUT
X
14 - Vramp
X
15 - TXEn
X
16 - LB_HB
X
17 - Vreg
X
18 - Vbat
X
19 - VD3_HB_DEC
X
20 - TXOut_HB
X
21 - GND
NA
NA
NA
NA
NA
22 - GND
NA
NA
NA
NA
NA
MMM6035 Advance Information, Rev. 2.4
10
Freescale Semiconductor
Application Information
6
Application Information
Figure 2 shows the typical application schematic and Figure 3 shows the printed circuit board for the
MMM6035. The bill of materials are listed in Table 11 and the power up/down sequences are listed in
Table 12.
Figure 2. Typical Application Schematic
MMM6035 Advance Information, Rev. 2.4
Freescale Semiconductor
11
Application Information
Table 11. Bill of Materials
Reference
Value
Size and Manufacturer
C1
68 uF 6 V
Sprague
C2
1000 nF
0402 Murata
C3
100 nF
0402 Murata
C4
22 pF
0402 Murata
C5
22 pF
0402 Murata
C6
2.7 pF
0402 Murata
C7
22 pF
0402 Murata
C9
33 pF
0402 Murata
C10
8.2 pF
0201 Johanson
C11
10 nF
0402 Murata
C12
10 nF
0402 Murata
C13
220 pF
0402 Murata
C14
10 nF
0402 Murata
C15
1 nF
0402 Murata
L1
3.9 nH
0402 Murata
R1
10 k
0402 NEOHM
R2
10k
0402 NEOHM
R3
1.8 k
0402 NEOHM
R4
1k
0402 NEOHM
MMM6035 Advance Information, Rev. 2.4
12
Freescale Semiconductor
Application Information
60 mm
50 mm
Figure 3. Printed Circuit Board
Table 12. Power Up/Down Sequences
SEQ
DESCRIPTION
Power Up Sequence for TX
1
Set TX_EN, LB_HB low
2
Set VRAMP to 0 V
3
Apply VBAT
4
Apply RF drive to appropriate TXIN
5
Apply VREG
6
Set LB_HB for desired band
7
Set TX_EN high
8
Apply appropriate pulses to VRAMP
Power Down Sequence for TX
1
Set VRAMP to 0 V
2
Set TX_EN low
3
Set LB_HB low
4
Remove VREG
MMM6035 Advance Information, Rev. 2.4
Freescale Semiconductor
13
Design Information
Table 12. Power Up/Down Sequences (continued)
SEQ
7
7.1
DESCRIPTION
5
Remove RF drive
6
Remove VBAT
Design Information
Power Control
Open loop power control of the power amplifier is enabled when TX_EN is set high. The PA drain voltage
will then be proportional to the VRAMP input voltage over the range 200 mV to 2.2 V of VRAMP as
shown in Figure 4.
enabled
disabled
VBAT
section
Vslope
Controller
section
Controller
VD_OUT
Vsat
Voffset
0
Vctrl
Vramp
Figure 4. VD_OUT vs. VRAMP Characteristics
MMM6035 Advance Information, Rev. 2.4
14
Freescale Semiconductor
Design Information
To meet the GSM power versus time mask and switching transient requirement, the MMM6035 must be
provided with a DAC ramp profile on the VRAMP input, as well as proper timing on digital controls for
the control loop circuitry as shown in Figure 5.
twu
tr_ramp
tf_ramp
TX_EN
Vramp(H)
Vramp
Vpedestal
Voffset
Vramp(L)
VD_OUT
+4dBc
-6dBc*
Pout (dB)
-30dBc*
Iso2
Iso1
10µs
8µs
10µs
542.8µs
10µs
8µs
10µs
* Derated at low Pout
Figure 5. Recommended Power Control Timing
The ramp profile consists of a pedestal voltage, 12 to 16 discrete voltage steps on the rising edge of the
burst, a constant region, 12 to 16 steps on the falling edge of the burst, and a final voltage. Generally, the
same profile, scaled in amplitude, us used for all frequencies and power control levels.
A feature unique to the MMM6035 is the internal offset generator which functions to cancel any external
offset associated with the DAC driving the VRAMP pin. In addition, the MMM6035 has a 200 kHz
MMM6035 Advance Information, Rev. 2.4
Freescale Semiconductor
15
Design Information
two-pole Sallenkey filter included in the VRAMP path to remove DAC noise and to provide VRAMP
signal smoothing.
7.2
Anti-Saturation Detection Feature
The MMM6035 prevents degradation of switching transients, regardless of battery conditions, due to an
internal anti-saturation detection feature. The goal of this block is to maintain the RF output power ramp
within the power versus time mask and to maintain acceptable spectral limits at specified offset
frequencies.
The anti-saturation detection feature is implemented by a feedback loop inside the power control loop
which detects when the power controller PMOS goes into the linear region. The feedback loop reduces
VRAMP to maintain the pass device in its saturation region, even under low battery voltage conditions.
40
VBATT = 3.5V
Antisat on
35
Time Mask
30
VBATT = 3.0V
Antisat on
25
VBATT = 3.0V
Ant isat off
Pout (dBm)
20
15
10
5
0
-5
-10
-15
0
2
4
6
8
10
12
14
16
18
20
Time (us)
Figure 6. Anti-Saturation Detection
7.3
Recommended Power Control Calibration Procedure
Power control calibration is carried out at two points. The procedure first requires the measurement of
output power (Po) calibration points at two values of Vramp (Vramp(1) and Vramp(2)). Figure 5 shows
these points, after conversion (*), plotted on the RMS RF output voltage (Vrf) against the control voltage
(Vramp) characteristic. Using these points, the Vramp voltage (Vramp(E)) can be estimated for any desired
output power level. In order to meet the transmitted power level versus time requirement of GSM05.05
Specification, at the lowest power level, it is also necessary to determine the Vramp pedestal voltage (see
Figure 4 and Figure 5) required to reach an acceptable power level when the controller section feedback
loop has stabilized after wake-up.
As a reminder:
Vrf = 10
( Po – 13 ) ⁄ 20
Eqn. 1
where Po is in dBm into 50 Ω and Vrf is in Vrms.
MMM6035 Advance Information, Rev. 2.4
16
Freescale Semiconductor
Design Information
Vrf Vrms
Calibration point(2)
Vrf(2)
Estimated point
Vrf(E)
Vrf(1)
Vrf(P)
Calibration point(1)
0
Vpedestal Vramp(1)
Vramp(2)
Vramp(E)
Vramp (V)
Figure 7. Vrf vs. Vramp characteristic
The calibration points Vrf(1) and Vrf(2) are each measured by forcing Vramp levels of Vramp(1) and
Vramp(2) respectively. The estimated Vramp level for the required RF output voltage Vrf(E) is then
calculated from the following:
Vramp ( 2 )x [ Vrf ( E ) – Vrf ( 1 ) ] + Vramp ( 1 )x [ Vrf ( 2 ) – Vrf ( E ) ]
Vramp ( E ) = ---------------------------------------------------------------------------------------------------------------------------------------------------------------Vrf ( 2 ) – Vrf ( 1 )
Eqn. 1
In a similar way Vpedestal can be calculated:
Vramp ( 2 )x [ Vrf ( P ) – Vrf ( 1 ) ] + Vramp ( 1 )x [ Vrf ( 2 ) – Vrf ( P ) ]
V pedestal = -------------------------------------------------------------------------------------------------------------------------------------------------------------Vrf ( 2 ) – Vrf ( 1 )
Eqn. 2
Table 13. Recommended Calibration Values
Description
Symbol
Value
Unit
Vramp at calibration point (1)
Vramp(1)
0.3
V
Vramp at calibration point (2)
Vramp(2)
1.5
V
Output power with Vramp=Vpedestal (Low band)
Po(P)_LB
1
dBm
Output power with Vramp=Vpedestal (High band)
Po(P)_HB
-3.5
dBm
Active Vramp rise time
Tr_ramp
14
µs
Active Vramp fall time
Tf_ramp
14
µs
-
12
µs
Pedestal Width
MMM6035 Advance Information, Rev. 2.4
Freescale Semiconductor
17
Package Information
VBAT
VREG
LB_HB
TX_EN
VDD3_HB_DEC
Package Information
TXOUT_HB
8
18
17
16
15
19
GND
20
1
GND
VDD2_ HB
VDD1_HB
14
VRAMP
13
VD_OUT
12
VREG_PA
11
TXOUT_LB
10
GND
2
3
TXIN_HB
5
TXIN_LB
6
7
8
9
GND
4
VDD2_LB
VAPC
VDD1_LB
GND
Figure 8. Package Footprint - Top View
MMM6035 Advance Information, Rev. 2.4
18
Freescale Semiconductor
Package Information
Figure 9. Outline Dimensions for 6x6 mm Module
(Case 1561-01, Issue O)
MMM6035 Advance Information, Rev. 2.4
Freescale Semiconductor
19
Signal Description
9
Signal Description
Table 14. Pin Connections
Number
Name
1
GND
2
Description
Type
Impedance
Ground
Ground
VDD2_HB
Drain Supply for Driver Stage, High-Band
Supply
3
VDD1_HB
Drain Supply for Pre-Driver Stage,
High-Band
Supply
4
VAPC
Bias Control Voltage
5
TX_IN_HB
TX Input High-Band
RF Input
50 Ω – DC Blocked
6
TX_IN_LB
TX Input Low-Band
RF Input
50 Ω – DC Blocked
7
VDD1_LB
Drain Supply for Pre-Driver Stage,
Low-Band
Supply
8
VDD2_LB
Drain Supply for Driver Stage, Low-Band
Supply
9
GND
Ground
Ground
Ground
10
GND
Ground
Ground
Ground
11
TXOUT_LB
TX Output Low-Band
12
VREG_PA
Regulated DC supply output active only
when TX_EN is high. Used for external
biasing of the power amplifier section.
Supply
13
VD_OUT
Power Control IC Output
Supply
14
VRAMP
DAC power control ramp
Control
15
TX_EN
Enable Power Control when set High
Control
16
LB_HB
Low-Band/High-Band Select. Logic High for
High-Band, Logic Low for Low-Band.
Control
17
VREG
External Regulated Voltage
Supply
18
VBAT
Drain supply for power control chip
Supply
19
20
50 Ω – NOT DC Blocked
VDD3_HB_DEC High-Band Final Stage RF Decoupling
TXOUT_HB
TX Output High-Band
Ground
RF
RF Output
50 Ω – NOT DC Blocked
MMM6035 Advance Information, Rev. 2.4
20
Freescale Semiconductor
Product Documentation
10 Product Documentation
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MMM6035 Advance Information, Rev. 2.4
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