TI1 LF351-N Lf351 wide bandwidth jfet input operational amplifier Datasheet

LF351
LF351 Wide Bandwidth JFET Input Operational Amplifier
Literature Number: SNOSBH2
General Description
are critical, the LF356 is recommended. If maximum supply
current is important, however, the LF351 is the better choice.
The LF351 is a low cost high speed JFET input operational
amplifier with an internally trimmed input offset voltage
(BI-FET II™ technology). The device requires a low supply
current and yet maintains a large gain bandwidth product
and a fast slew rate. In addition, well matched high voltage
JFET input devices provide very low input bias and offset
currents. The LF351 is pin compatible with the standard
LM741 and uses the same offset voltage adjustment circuitry. This feature allows designers to immediately upgrade
the overall performance of existing LM741 designs.
The LF351 may be used in applications such as high speed
integrators, fast D/A converters, sample-and-hold circuits
and many other circuits requiring low input offset voltage,
low input bias current, high input impedance, high slew rate
and wide bandwidth. The device has low noise and offset
voltage drift, but for applications where these requirements
n
n
n
n
n
n
n
n
n
Typical Connection
Simplified Schematic
Features
Internally trimmed offset voltage: 10 mV
Low input bias current: 50 pA
Low input noise voltage:
Low input noise current:
Wide gain bandwidth: 4 MHz
High slew rate: 13 V/µs
Low supply current: 1.8 mA
High input impedance: 1012Ω
Low total harmonic distortion AV = 10,: < 0.02%
RL = 10k, VO = 20 Vp-p, BW = 20 Hz–20 kHz
n Low 1/f noise corner: 50 Hz
n Fast settling time to 0.01%: 2 µs
LF351
LF351
Wide Bandwidth JFET Input Operational Amplifier
LF351 Wide Bandwidth JFET Input Operational Amplifier
April 1998
DS005648-11
DS005648-12
BI-FET II™ is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
www.national.com
DS005648
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1
Connection Diagram
Dual-In-Line Package
DS005648-13
Order Number LF351M or LF351N
See NS Package Number M08A or N08E
www.national.com
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Absolute Maximum Ratings (Note 1)
θjA
N Package
M Package
Soldering Information
Dual-In-Line Package
Soldering (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Power Dissipation (Notes 2, 7)
Operating Temperature Range
Tj(MAX)
Differential Input Voltage
Input Voltage Range (Note 3)
Output Short Circuit Duration
Storage Temperature Range
Lead Temp. (Soldering, 10 sec.)
Metal Can
DIP
± 18V
670 mW
0˚C to +70˚C
115˚C
± 30V
± 15V
Continuous
−65˚C to +150˚C
DC Electrical Characteristics
Symbol
120˚C/W
TBD
260˚C
215˚C
220˚C
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
ESD rating to be determined
300˚C
260˚C
(Note 4)
Parameter
Conditions
LF351
Min
Max
5
10
Input Offset Voltage
RS = 10 kΩ, TA = 25˚C
Average TC of Input Offset
Over Temperature
RS = 10 kΩ
10
Input Offset Current
Tj = 25˚C, (Notes 4, 5)
25
Input Bias Current
Tj ≤ 70˚C
Tj = 25˚C, (Notes 4, 5)
RIN
Input Resistance
Tj ≤ ± 70˚C
Tj = 25˚C
AVOL
Large Signal Voltage Gain
VO
Output Voltage Swing
VCM
Input Common-Mode Voltage
VOS
∆VOS/∆T
Units
Typ
13
mV
mV
µV/˚C
Voltage
IOS
IB
50
VS = ± 15V, TA = 25˚C
VO = ± 10V, RL = 2 kΩ
25
Over Temperature
VS = ± 15V, RL = 10 kΩ
100
pA
4
nA
200
pA
8
nA
1012
Ω
100
V/mV
15
± 12
V/mV
± 13.5
V
+15
V
Range
VS = ± 15V
± 11
−12
V
CMRR
Common-Mode Rejection Ratio
RS≤10 kΩ
70
100
dB
PSRR
Supply Voltage Rejection Ratio
(Note 6)
70
100
IS
Supply Current
1.8
dB
3.4
mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.
Note 2: For operating at elevated temperature, the device must be derated based on the thermal resistance, θJA.
Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: These specifications apply for VS = ± 15V and 0˚C≤TA≤+70˚C. VOS, IB and IOS are measured at VCM = 0.
Note 5: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, Tj. Due to the limited
production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation, PD. Tj = TA+θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum.
Note 6: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. From
± 15V to ± 5V.
Note 7: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate outside
guaranteed limits.
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AC Electrical Characteristics
Symbol
(Note 4)
Parameter
Conditions
LF351
Min
Typ
Units
Max
SR
Slew Rate
VS = ± 15V, TA = 25˚C
13
V/µs
GBW
Gain Bandwidth Product
4
MHz
en
Equivalent Input Noise Voltage
VS = ± 15V, TA = 25˚C
TA = 25˚C, RS = 100Ω,
25
Equivalent Input Noise Current
f = 1000 Hz
Tj = 25˚C, f = 1000 Hz
0.01
in
Typical Performance Characteristics
Input Bias Current
Input Bias Current
Supply Current
DS005648-15
DS005648-14
Positive Common-Mode
Input Voltage Limit
DS005648-16
Negative Common-Mode
Input Voltage Limit
Positive Current Limit
DS005648-19
DS005648-17
Negative Current Limit
DS005648-18
Output Voltage Swing
Voltage Swing
DS005648-21
DS005648-20
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DS005648-22
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Typical Performance Characteristics
Gain Bandwidth
(Continued)
Slew Rate
Bode Plot
DS005648-23
Distortion vs Frequency
DS005648-25
DS005648-24
Undistorted Output
Voltage Swing
Open Loop Frequency
Response
DS005648-26
DS005648-28
DS005648-27
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Equivalent Input
Noise Voltage
DS005648-29
DS005648-30
DS005648-31
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Typical Performance Characteristics
Open Loop Voltage
Gain (V/V)
(Continued)
Output Impedance
Inverter Settling Time
DS005648-34
DS005648-33
DS005648-32
Pulse Response
Small Signal Inverting
Small Signal Non-Inverting
DS005648-4
DS005648-5
Large Signal Inverting
Large Signal Non-Inverting
DS005648-6
DS005648-7
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Pulse Response
(Continued)
Current Limit (RL = 100Ω)
DS005648-8
The LF351 will drive a 2 kΩ load resistance to ± 10V over the
full temperature range of 0˚C to +70˚C. If the amplifier is
forced to drive heavier load currents, however, an increase
in input offset voltage may occur on the negative voltage
swing and finally reach an active current limit on both positive and negative swings.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3
dB frequency of the closed loop gain and consequently there
is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3
dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal
to the original feedback pole time constant.
Application Hints
The LF351 is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET II™). These
JFETs have large reverse breakdown voltages from gate to
source and drain eliminating the need for clamps across the
inputs. Therefore, large differential input voltages can easily
be accommodated without a large increase in input current.
The maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a reversal of phase to the output.
Exceeding the negative common-mode limit on both inputs
will force the amplifier output to a high state. In neither case
does a latch occur since raising the input back within the
common-mode range again puts the input stage and thus
the amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced
to a high state.
The amplifier will operate with a common-mode input voltage
equal to the positive supply; however, the gain bandwidth
and slew rate may be decreased in this condition. When the
negative common-mode voltage swings to within 3V of the
negative supply, an increase in input offset voltage may occur.
The LF351 is biased by a zener reference which allows normal circuit operation on ± 4V power supplies. Supply voltages less than these may result in lower gain bandwidth and
slew rate.
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Detailed Schematic
DS005648-9
Typical Applications
Supply Current Indicator/Limiter
Hi-ZIN Inverting Amplifier
DS005648-40
• VOUT switches high when RSIS > VD
www.national.com
DS005648-41
Parasitic input capacitance C1 ≅ (3 pF for LF351 plus any additional layout
capacitance) interacts with feedback elements and creates undesirable
high frequency pole. To compensate, add C2 such that: R2C2 ≅ R1C1.
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Typical Applications
(Continued)
Ultra-Low (or High) Duty Cycle Pulse Generator
DS005648-42
where VS = V+ + |V−|
*low leakage capacitor
Book
Extract
End
Long Time Integrator
DS005648-43
*Low leakage capacitor
• 50k pot used for less sensitive VOS adjust
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THIS PAGE IS IGNORED IN THE DATABOOK
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Physical Dimensions
inches (millimeters) unless otherwise noted
SO Package (M)
Order Number LF351M
NS Package Number M08A
Molded Dual-In-Line Package (N)
Order Number LF351N
NS Package Number N08E
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LF351 Wide Bandwidth JFET Input Operational Amplifier
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PrintDate=1998/04/07 PrintTime=13:52:35 38265 ds005648 Rev. No. 3
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