ESD11L5.0DT5G Transient Voltage Suppressors ESD Protection Diodes with Ultra−Low Capacitance The ESD11L5.0DT5G is designed to protect voltage sensitive components from damage due to ESD in applications that require ultra low capacitance to preserve signal integrity. Excellent clamping capability, low leakage and fast response time are combined with an ultra low diode capacitance of 0.5 pF to provide best in class protection from IC damage due to ESD. The ultra small SOT−1123 package is ideal for designs where board space is at a premium. The ESD11L5.0DT5G can be used to protect two uni−directional lines or one bi−directional line. When used to protect one bi−directional line, the effective capacitance is 0.25 pF. Because of its low capacitance, it is well suited for protecting high frequency signal lines such as USB2.0 high speed and antenna line applications. http://onsemi.com PIN 1. CATHODE 2. CATHODE 3. ANODE 3 2 SOT−1123 CASE 524AA Specification Features: • Low Capacitance 0.5 pF Typical • Low Clamping Voltage • Small Body Outline Dimensions: • • • • • • 1 MARKING DIAGRAM 0.039” x 0.024” (1.0 mm x 0.6 mm) Low Body Height: 0.015″ (0.37 mm) Stand−off Voltage: 5 V Low Leakage Response Time is Typically < 1.0 ns IEC61000−4−2 Level 4 ESD Protection This is a Pb−Free Device 6M 6 = Specific Device Code M = Date Code Mechanical Characteristics: CASE: Void-free, transfer-molded, thermosetting plastic Epoxy Meets UL 94 V−0 LEAD FINISH: 100% Matte Sn (Tin) MOUNTING POSITION: Any ORDERING INFORMATION QUALIFIED MAX REFLOW TEMPERATURE: 260°C Device Package Shipping† ESD11L5.0DT5G SOT−1123 (Pb−Free) 8000/Tape & Reel Device Meets MSL 1 Requirements MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Contact Value Unit ±10 kV Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C °PD° 150 mW Storage Temperature Range Tstg −55 to +150 °C Junction Temperature Range TJ −55 to +125 °C Lead Solder Temperature − Maximum (10 Second Duration) TL 260 °C †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. DEVICE MARKING INFORMATION See specific marking information in the device marking column of the Electrical Characteristics tables starting on page 2 of this data sheet. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2009 August, 2009 − Rev. 1 1 Publication Order Number: ESD11L5.0D/D ESD11L5.0DT5G ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol I Parameter IF IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR Working Peak Reverse Voltage VBR Test Current IF Forward Current VF Forward Voltage @ IF Ppk Peak Power Dissipation V IR VF IT Breakdown Voltage @ IT IT C VC VBR VRWM Maximum Reverse Leakage Current @ VRWM IPP Uni−Directional TVS Capacitance @ VR = 0 V and f = 1.0 MHz *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 1.1 V Max. @ IF = 10 mA for all types) Device ESD11L5.0DT5G 2. 3. 4. 5. 6. VRWM (V) IR (mA) @ VRWM VBR (V) @ IT (Note 2) C (pF), uni−directional (Note 3) C (pF), bi−directional (Note 4) IT Device Marking Max Max Min mA Typ Max Typ Max Per IEC61000−4−2 (Note 6) 6 5.0 1.0 5.4 1.0 0.5 0.9 0.25 0.45 Figures 1 and 2 VC VBR is measured with a pulse test current IT at an ambient temperature of 25°C. Uni−directional capacitance at f = 1 MHz, VR = 0 V, TA = 25°C (pin1 to pin 3; pin 2 to pin 3). Bi−directional capacitance at f = 1 MHz, VR = 0 V, TA = 25°C (pin1 to pin 2). Surge current waveform per Figure 5. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D. Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV contact per IEC 61000−4−2 Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV contact per IEC 61000−4−2 http://onsemi.com 2 ESD11L5.0DT5G IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 3. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 5. 8 X 20 ms Pulse Waveform http://onsemi.com 3 80 ESD11L5.0DT5G PACKAGE DIMENSIONS SOT−1123 CASE 524AA−01 ISSUE B −X− D b1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. −Y− 1 E 3 2 b e 0.08 (0.0032) X Y DIM A b b1 c D E e HE L A c L HE MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 0.15 0.22 0.28 0.10 0.15 0.20 0.07 0.12 0.17 0.75 0.80 0.85 0.55 0.60 0.65 0.35 0.40 −−− 0.95 1.00 1.05 0.05 0.10 0.15 MIN 0.013 0.006 0.004 0.003 0.030 0.022 0.014 0.037 0.002 INCHES NOM 0.015 0.009 0.006 0.005 0.031 0.024 −−−− 0.039 0.004 MAX 0.016 0.011 0.008 0.007 0.033 0.026 0.016 0.041 0.006 SOLDERING FOOTPRINT* 0.35 0.30 0.25 0.40 0.90 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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