AKM AK7755EN Dsp with mono adc stereo codec mic/lineout amp Datasheet

[AK7755]
AK7755
DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp
1. General Description
The AK7755 is a highly integrated digital signal processor, including a mono ADC, a stereo audio CODEC, a
MIC pre-amplifier, a line-out amplifier and digital audio I/F. The audio DSP has 2560step at fs = 48kHz
parallel processing power. As the AK7755 is a RAM based DSP, it is programmable for user requirements
such as high performance hands free function and acoustic effects. The AK7755 is available in a space saving
small 36-pin QFN package.
2. Features
 DSP
- Word length: 24-bit (Data RAM 24-bit floating point)
- Instruction cycle: 8.1ns (2560fs at fs=48kHz)
- Multiplier 24 x 24 → 48-bit (double precision available)
- Divider 20 / 20 → 20-bit (with floating point normalization function)
- ALU: 52-bit arithmetic operation (with overflow margin 4-bit)
- Program RAM: 4096 × 36-bit
- Coefficient RAM: 2048 × 24-bit
- Data RAM: 2048 × 24-bit (24-bit floating point)
- Offset Register: 32 × 13-bit
- Delay RAM: 8192 × 24-bit
- Accelerator Coefficient RAM: 2048 × 20-bit
- Accelerator Data RAM: 2048 × 16-bit
- JX pins (Interrupt)
- Master/Slave Operation
- Master Clock: 2560fs
(Internally Generated by PLL from 32, 48, 64, 128, 256 and 384fs clock)
 Two Digital Interfaces (I/F1, I/F2)
- Digital Signal Input Port (4ch): MSB justified 24-bit, LSB justified 24/20/16-bit, I2S
- Digital Signal Input Port (6ch): MSB justified 24-bit, LSB justified 24/20/16-bit, I2S
- Short / Long Frame
- 24-bit linear, 8-bit A-law, 8-bit μ-law
- TDM 256fs (8ch) MSB justified and I2S formats
 Stereo 24-bit ADC:
- Sampling Frequency: fs=8kHz ~ 96kHz
- ADC Characteristics S/(N+D): 91dB, DR, S/N: 102dB
- Two-Channel Analog Input Selector (Differential, Single-ended Input)
- Channel Independent Mic Analog Gain Amplifier
(0~18dB (2dB Step), 18~36dB (3dB Step))
- Analog DRC (Dynamic Range Control)
- Channel Independent Digital Volume (24~-103dB, 0.5dB Step Mute)
- Digital HPF for DC Offset Cancelling
 Mono 24-bit ADC
- Sampling Frequency: 8kHz ~ 96kHz
- ADC Characteristics S/(N+D): 90dB; DR, S/N: 100dB
- Line Amplifier: 21dB ~ -21dB, 3dB Step
- Digital Volume (24dB ~ -103dB, 0.5dB step, Mute)
- Digital HPF for DC Offset Cancelling
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 Stereo 24-bit DAC
- Sampling Frequency: fs=8kHz ~ 96kHz
- Digital Volume (12dB ~ -115dB, 0.5step, Mute)
- Digital De-emphasis Filter (tc=50/15us, fs=32kHz, 44.1kHz, 48kHz)
 Line Output
- Single-ended Output
- S/(N+D): 91dB, DR, S/N: 106dB
- Stereo Analog Volume (+0dB ~ -28dB, 2.0dB step, Mute)
 Analog Mixer
 Digital Mixer
 4ch Digital Microphone Interface
 I2C Bootloader
- EEPROM Mat Selectable
 μP Interface: SPI, I2C-bus (400kHz Fast Mode)
 Power supply
Analog (AVDD): 3.0V ~ 3.6V (typ. 3.3V)
Digital1 (DVDD): 1.14V ~ 1.3V (typ. 1.2V)
(External Power Supply or Internal Regulator is selectable)
I/F (TVDD): 1.7V ~ 3.6V (typ. 3.3V)
 Operating Temperature Range: -40C ~ 85C
 Package: 36-pin QFN (0.5mm pitch)
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3. Table of Contents
1. General Description ................................................................................................................................................. 1
2. Features.................................................................................................................................................................... 1
3. Table of Contents ..................................................................................................................................................... 3
4. Block Diagram and Functions ................................................................................................................................. 4
■ Block Diagram .......................................................................................................................................... 4
■ DSP Block Diagram .................................................................................................................................. 5
5. Pin Configurations and Functions ........................................................................................................................... 6
■ Ordering Guide .......................................................................................................................................... 6
■ Pin Layout ................................................................................................................................................. 6
■ Pin Functions ............................................................................................................................................. 9
■ Handling of Unused Pin .......................................................................................................................... 10
6. Absolute Maximum Ratings .................................................................................................................................. 11
7. Recommended Operating Conditions .................................................................................................................... 11
8. Electrical Characteristics ....................................................................................................................................... 12
■ Analog Characteristics ............................................................................................................................ 12
■ DC Characteristics ................................................................................................................................... 17
■ Power Consumptions ............................................................................................................................... 17
■ Digital Filter Characteritics ..................................................................................................................... 18
■ Switching Characteristics ........................................................................................................................ 19
9. Functional Description .......................................................................................................................................... 26
■ System Clock ........................................................................................................................................... 26
■ Control Register Settings......................................................................................................................... 30
■ Power-up Sequence ................................................................................................................................. 52
■ LDO (Internal Circuit Drive Regulator).................................................................................................. 55
■ Power-down Sequence ............................................................................................................................ 55
■ Power-down and Reset ............................................................................................................................ 56
■ RAM Clear .............................................................................................................................................. 58
■ Serial Data Interface ................................................................................................................................ 59
■ μP Interface Setting and Pin Status ......................................................................................................... 66
■ SPI Interface (I2CSEL pin = “L”) ........................................................................................................... 66
■ I2C Bus Interface (I2CSEL pin= “H”) ..................................................................................................... 79
■ Analog Input Block ................................................................................................................................. 84
■ ADC Block .............................................................................................................................................. 87
■ DAC Blocks ............................................................................................................................................ 90
■ Analog Output Block............................................................................................................................... 92
■ Simple Write Error Check ....................................................................................................................... 94
■ EEPROM Interface.................................................................................................................................. 95
■ Digital Microphone Interface .................................................................................................................. 99
■ Digital Mixer ......................................................................................................................................... 100
10. Recommended External Circuits ....................................................................................................................... 101
■ Connection Diagram.............................................................................................................................. 101
■ Peripheral Circuit .................................................................................................................................. 105
11. Package .............................................................................................................................................................. 107
■ Outline Dimensions ............................................................................................................................... 107
■ Package & Lead frame material ............................................................................................................ 107
■ Marking ................................................................................................................................................. 108
12. Revision History ................................................................................................................................................ 109
IMPORTANT NOTICE ........................................................................................................................................ 109
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4. Block Diagram and Functions
■ Block Diagram
Figure 1. Block Diagram
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■ DSP Block Diagram
CP0, CP1
Pointer
DP0, DP1
Coefficient RAM
Data RAM
2048w x 24-Bit(20.4f)
2048w×24-Bit
OFREG
32w x 13-Bit
DLP0, DLP1
Delay RAM
8192w x 24-Bit(20.4f)
CBUS(24-Bit)
DBUS(28-Bit)
MPX24
Micon I/F
MPX24
X
Serial I/F
Control
PRAM
DEC
Y
4096w×36-Bit
Multiply
24 ×24 → 48-Bit
PC
Stack : 5level(max)
28-Bit
48-Bit
TMP 12×24-Bit
PTMP(LIFO) 6×24-Bit
MUL
DBUS
2×16/20/24-Bit
DIN4
2×16/20/24-Bit
DIN3
2×16/20/24-Bit
DIN2
2×16/20/24-Bit
DIN1
ALU
2×16/20/24-Bit
DOUT4
52-Bit
2×16/20/24-Bit
DOUT3
2×16/20/24-Bit
DOUT2
2×16/20/24-Bit
DOUT1
SHIFT
52-Bit
48-Bit
A
B
Overflow Margin: 4-Bit
52-Bit
DR0  3
Accelerator
52-Bit
Coefficient RAM
(ACCRAM)
2048w x 20-Bit
Over Flow Data
Generator
Division 2020→20
Data RAM
(ACDRAM)
2048w x 16-Bit
Peak Detector
Figure 2. DSP Block Diagram
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5. Pin Configurations and Functions
■ Ordering Guide
-40  +85C
36-pin QFN (0.5mm pitch)
Evaluation Board for AK7755
AK7755EN/VN
AKD7755
OUT3
OUT2
DVSS
DVDD/AVDRV
LDOE
PDN
AVDD
CSN/CAD/MATSEL
SI/EXTEEP
27
26
25
24
23
22
21
20
19
■ Pin Layout
OUT1
28
18
SCLK/SCL
AVDD
29
17
SO/SDA
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
SDOUT2/JX3/MAT0
IN3/INP2/DMDAT2
32
14
SDOUT3/JX2/MAT1
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
1
2
3
4
5
6
7
8
9
VCOM
AVSS
I2CSEL
SDIN2/JX1
SDIN1/JX0
STO/RDY
LRCK
BICK
CLKO
(TOP VIEW)
PIN
Input
Output
I/O
Power
Figure 3. Pin Layout
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OUT3
OUT2
DVSS
DVDD/AVDRV
LDOE
PDN
AVDD
CSN
SI
27
26
25
24
23
22
21
20
19
I2CSEL pin = “L”
OUT1
28
18
SCLK
AVDD
29
17
SO
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
SDOUT2/JX3
IN3/INP2/DMDAT2
32
14
SDOUT3/JX2
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
1
2
3
4
5
6
7
8
9
VCOM
AVSS
I2CSEL=“L”
SDIN2/JX1
SDIN1/JX0
STO/RDY
LRCK
BICK
CLKO
(TOP VIEW)
PIN
Input
Output
I/O
Power
OUT3
OUT2
DVSS
DVDD/AVDRV
LDOE
PDN
AVDD
CAD
EXTEEP=“L”
27
26
25
24
23
22
21
20
19
I2CSEL pin = “H”, EXTEEP pin = “L”
OUT1
28
18
SCL
AVDD
29
17
SDA
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
SDOUT2/JX3
IN3/INP2/DMDAT2
32
14
SDOUT3/JX2
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
1
2
3
4
5
6
7
8
9
VCOM
AVSS
I2CSEL=“H”
SDIN2/JX1
SDIN1/JX0
STO/RDY
LRCK
BICK
CLKO
(TOP VIEW)
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PIN
Input
Output
I/O
Power
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OUT3
OUT2
DVSS
DVDD/AVDRV
LDOE
PDN
AVDD
MATSEL=“L”
EXTEEP=“H”
27
26
25
24
23
22
21
20
19
I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “L”
OUT1
28
18
SCL
AVDD
29
17
SDA
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
SDOUT2/JX3
IN3/INP2/DMDAT2
32
14
SDOUT3/JX2
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
1
2
3
4
5
6
7
8
9
VCOM
AVSS
I2CSEL=“H”
SDIN2/JX1
SDIN1/JX0
STO/RDY
LRCK
BICK
CLKO
(TOP VIEW)
PIN
Input
Output
I/O
Power
OUT3
OUT2
DVSS
DVDD/AVDRV
LDOE
PDN
AVDD
MATSEL=“H”
EXTEEP=“H”
27
26
25
24
23
22
21
20
19
I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “H”
OUT1
28
18
SCL
AVDD
29
17
SDA
AVSS
30
16
SDOUT1/EEST
IN4/INN2/DMCLK2
31
15
MAT0
IN3/INP2/DMDAT2
32
14
MAT1
IN2/INN1/DMCLK1
33
13
DVSS
IN1/INP1/DMDAT1
34
12
TVDD
LIN
35
11
XTI
AVDD
36
10
XTO
36pin QFN
1
2
3
4
5
6
7
8
9
VCOM
AVSS
I2CSEL=“H”
SDIN2/JX1
SDIN1/JX0
STO/RDY
LRCK
BICK
CLKO
(TOP VIEW)
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PIN
Input
Output
I/O
Power
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■ Pin Functions
No.
Pin Name
I/O
1
VCOM
O
2
AVSS
-
3
I2CSEL
I
SDIN2
JX1
SDIN1
JX0
STO
RDY
LRCK
BICK
CLKO
I
I
I
I
O
O
I/O
I/O
O
4
5
6
7
8
9
10 XTO
O
11 XTI
I
12 TVDD
13 DVSS
SDOUT3
JX2
14
MAT1
I
O
I
SDOUT2
JX3
O
I
MAT0
I
15
SDOUT1
EEST
SO
17
SDA
16
SCLK
I
O
O
O
I/O
I
18
SCL
19
I/O
SI
I
EXTEEP
I
Function
Common Voltage Output Pin of Analog Block
▪ Connect a 2.2μF capacitor between AVSS.
▪ Do not connect to an external circuit.
Analog Ground Pin 0V
I2C-BUS Select Pin
▪ I2CSEL pin = “L”: SPI Interface
▪ I2CSEL pin = “H”: I2C-bus Interface
The I2CSEL pin must be fixed to “L” (DVSS) or “H” (TVDD).
Serial Data Input2 Pin
External Conditional Jump1 Pin (JX1E bit = “1”)
Serial Data Input1 Pin
External Conditional Jump0 Pin (JX0E bit = “1”)
Status Output Pin
RDY Pin
LR Channel Select Pin (Internal pull-down)
Serial Bit Clock Output Pin (Internal pull-down)
Clock Output Pin
Crystal oscillator output pin
▪ When a crystal oscillator is used, connect it between XTI and XTO.
▪ When a crystal oscillator is not used, leave this pin as open.
Crystal oscillator input pin
▪ When a crystal oscillator is used, connect it between XTI and XTO.
▪ When a crystal oscillator is not used, connect this pin to the external clock
or leave open.
Digital IO Power Supply Pin: 1.7~3.6V (typ. 3.3V)
Ground Pin 0V
Serial Data Output3 Pin
External Conditional Jump2 Pin (JX2E bit = “1”)
I2CSEL pin = EXTEEP pin = MATSEL pin = “H”
EEPROM Download Mat Select Address1
Serial Data Output2 Pin
External Conditional Jump3 Pin (JX3E bit = “1”)
I2CSEL pin = EXTEEP pin = MATSEL pin = “H”
EEPROM Download Mat Select Address0
Serial Data Output1 Pin
EEPROM Interface Status
SO Pin (I2CSEL pin = “L”)
I2CBUS Interface (I2CSEL pin = “H”)
Serial Data Clock Pin for SPI Interface (I2CSEL pin = “L”)
▪ Set this pin to “H” when there is no clock input.
I2CBUS Interface Pin (I2CSEL pin = “H”)
EEPROM Download This becomes an output pin when EXTEEP pin = “H”.
Serial Data Input Pin for SPI Interface (I2CSEL pin = “L”)
▪ Set this pin to “L” when not used.
EEPROM Download Control Pin (I2CSEL pin = “H”)
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ChipSelectN Pin for SPI Interface (I2CSEL pin = “L”)
▪ Set this pin to “H” when the AK7755 is in power-down mode or when the
microprocessor I/F is not used.
20
CAD
I I2CBUS Address Pin (I2CSEL pin = “H”)
MATSEL
I EEPROM Mat Select Pin (I2CSEL pin = EXTEEP pin = “H”)
21 AVDD
- Analog Power Supply Pin: (typ. 3.3V)
Power-down N Pin
22 PDN
I
▪ The AK7755 can be powered-down by this pin.
▪ Set this pin to “L” upon power-up the AK7755.
LDO Select Pin
LDOE pin = “L”: 24 pin External 1.2V Power Supply
23 LDOE
I
LDOE pin = “H”: 24 pin LDO Output (LDO Drive)
The LDOE pin must be fixed to “L(DVSS)” or “H(TVDD)”.
DVDD
I Power Supply Pin for Digital Core: (typ. 1.2V)
LDO Output (LDOE pin = “H”)
24
AVDRV
O
Connect a 1uF capacitor between this pin and DVSS. This pin must not be
connected to an external circuit.
25 DVSS
- Ground Pin 0V
26 OUT2
O Line Output 2 Pin
27 OUT3
O Line Output 3 Pin
28 OUT1
O Line Output 1 Pin
29 AVDD
- Analog Power Supply Pin: 3.3V (typ)
30 AVSS
- Analog Ground Pin 0V
IN4/INN2
I ADC Input Pin (AINE bit = “1”)
31
DMCLK2
O Digital MIC Clock Output 2 Pin (DMIC2 bit = “1”)
IN3/INP2
I ADC Input Pin (AINE bit = “1”)
32
DMDAT2
I Digital MIC Clock Input 2 Pin (DMIC2 bit = “1”)
IN2/INN1
I ADC Input Pin (AINE bit = “1”)
33
DMCLK1
O Digital MIC Clock Output 1 Pin (DMIC1 bit = “1”)
IN1/INP1
I ADC Input Pin (AINE bit = “1”)
34
DMDAT1
I Digital MIC Clock Input 1 Pin (DMIC1 bit = “1”)
35 LIN
I Mono ADC Input Pin
36 AVDD
- Analog Power Supply Pin: 3.3V (typ)
Note 1. All digital input pins must not be allowed to float. If analog input pins are not used, leave them open.
The I2CSEL pin, LDOE pin and CAD/MATSEL pin should be fixed to “L” (DVSS) or “H”
(TVDD).
CSN
I
■ Handling of Unused Pin
The unused I/O pins must be processed appropriately as below.
Classification Pin Name
LIN, IN1/INP1/DMDAT1, IN2/INN1/DMCLK1,
Analog
IN3/INP2/DMDAT2, IN4/INN2/DMCLK2, OUT1, OUT2,
OUT3
STO/RDY, CLKO, XTI, XTO, SDOUT3/ JX2/MAT1,
SDOUT2/JX3/MAT0, SDOUT1/EEST, SO/SDA, LRCK,
BICK
Digital
I2CSEL, SDIN2/JX1, SDIN1/JX0,
SCLK/SCL, SI/EXTEEP, CSN/CAD/MATSEL, LDOE
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Setting
These pins must be open.
These pins must be open.
These pins must be
connected to DVSS.
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6. Absolute Maximum Ratings
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
min
max
Power Supplies
Analog
AVDD
-0.3
4.3
Digital1(I/F)
TVDD
-0.3
4.3
Digital2(Core)
DVDD
-0.3
1.6
DVSS-AVSS
(Note 2)
ΔGND
-0.3
0.3
Input Current, Any Pin Except Supplies
IIN
±10
－
Analog Input Voltage (Note 3)
VINA
-0.3
(AVDD+0.3)≤4.3
Digital Input Voltage (Note 4)
VIND
-0.3
(TVDD+0.3)≤4.3
Ambient Temperature
Ta
-40
85
Storage Temperature
Tstg
-65
150
Note 2. All voltages with respect to ground. AVSS and DVSS must be the same voltage.
Note 3. The maximum analog input voltage is smaller value between (AVDD+0.3)V and 4.3V.
Note 4. The maximum digital input voltage is smaller value between (DVDD+0.3)V and 4.3V.
Unit
V
V
V
V
mA
V
V
℃
℃
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS=0V; Note 2)
Parameter
Symbol
min
typ
max
Unit
Power Supplies
Analog
AVDD
3.0
3.3
3.6
V
Digital1(I/F)
TVDD
1.7
3.3
3.6
V
Digital2(Core)
DVDD
1.14
1.2
1.3
V
Note 5. AVDD and TVDD must be powered up first before DVDD when DVDD is supplied externally
(LDOE pin = “L”). In this case, the power-up sequence between AVDD and TVDD is not critical.
When using the internal regulator (LDOE pin = “H”), the power-up sequence between AVDD and
TVDD is not critical. But all power supplies must be ON before starting operation of the AK7755
by PDN pin = “H”.
Note 6. Do not turn off the power supply of the AK7755 with the power supply of the surrounding device
turned on. Pull-up of SDA and SCL pins must not exceed TVDD.
* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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8. Electrical Characteristics
■ Analog Characteristics
1. MIC Amplifier Gain
(Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V)
Parameter
min
MIC
Input Impedance
14
AMP
MGNL[3:0]bits=0h, MGNR[3:0]bits=0h
MGNL[3:0]bits=1h, MGNR[3:0]bits=1h
MGNL[3:0]bits=2h, MGNR[3:0]bits=2h
MGNL[3:0]bits=3h, MGNR[3:0]bits=3h
MGNL[3:0]bits=4h, MGNR[3:0]bits=4h
MGNL[3:0]bits=5h, MGNR[3:0]bits=5h
MGNL[3:0]bits=6h, MGNR[3:0]bits=6h
MGNL[3:0]bits=7h, MGNR[3:0]bits=7h
Gain
MGNL[3:0]bits=8h, MGNR[3:0]bits=8h
MGNL[3:0]bits=9h, MGNR[3:0]bits=9h
MGNL[3:0]bits=Ah, MGNR[3:0]bits=Ah
MGNL[3:0]bits=Bh, MGNR[3:0]bits=Bh
MGNL[3:0]bits=Ch, MGNR[3:0]bits=Ch
MGNL[3:0]bits=Dh, MGNR[3:0]bits=Dh
MGNL[3:0]bits=Eh, MGNR[3:0]bits=Eh
MGNL[3:0]bits=Fh, MGNR[3:0]bits=Fh
typ
20
0
2
4
6
8
10
12
14
16
18
21
24
27
30
33
36
max
Unit
kΩ
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
2. Line-in Amplifier Gain
(Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V)
Parameter
min
typ
max
Unit
Line-in Input Impedance
14
20
kΩ
AMP
LIGN[3:0]bits=0h
0
dB
LIGN[3:0]bits=1h
-3
dB
LIGN[3:0]bits=2h
-6
dB
LIGN[3:0]bits=3h
-9
dB
LIGN[3:0]bits=4h
-12
dB
LIGN[3:0]bits=5h
-15
dB
LIGN[3:0]bits=6h
-18
dB
LIGN[3:0]bits=7h
-21
dB
Gain
(Note 7) LIGN[3:0]bits=8h
N/A
dB
LIGN[3:0]bits=9h
+3
dB
LIGN[3:0]bits=Ah
+6
dB
LIGN[3:0]bits=Bh
+9
dB
LIGN[3:0]bits=Ch
+12
dB
LIGN[3:0]bits=Dh
+15
dB
LIGN[3:0]bits=Eh
+18
dB
LIGN[3:0]bits=Fh
+21
dB
Note 7. If the output signal of line-in amplifier is input to the analog mixer, +18dB gain is added to the
signal at the mixer.
014006643-E-00
2014/10
- 12 -
[AK7755]
3. MIC Amp + ADC
Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V;
Signal Frequency 1kHz; Sampling Rate fs=48kHz; Measurement Frequency =20Hz to 20kHz
Sampling Rate fs=96kHz; Measurement Frequency =20Hz to 40kHz
CKM mode0(CKM[2:0]= “000”); BITFS[1:0]= “00” (64fs); Differential Input Mode
Parameter
min
typ
max
MIC Amp Resolution
24
+ ADC
Dynamic Characteristics (Differential Input mode)
Fs=48kHz (Note 12)
80
91
Fs=48kHz (Note 13)
88
S/(N+D)
(-1dBFS)
Fs=96kHz (Note 12)
89
Fs=96kHz (Note 13)
85
Fs=48kHz (A-weighted) (Note 12)
94
102
Dynamic
Fs=48kHz (A-weighted) (Note 13)
93
Range
Fs=96kHz (Note 12)
95
(Note 8)
Fs=96kHz (Note 13)
89
Fs=48kHz (A-weighted) (Note 12)
94
102
Fs=48kHz (A-weighted) (Note 13)
93
S/N
Fs=96kHz (Note 12)
95
Fs=96kHz (Note 13)
89
Inter-Channel Isolation (Note 9)
90
105
DC accuracy (Differential Input)
Channel Gain Mismatch
0.0
0.3
Analog Input
(Note 12)
±2.0
±2.2
±2.4
Input Voltage
(Differential Input) (Note 10)
(Note 13)
±0.277
(Note 12)
2.0
2.2
2.4
Input Voltage
(Single-ended Input) (Note 11)
(Note 13)
0.277
Note 8. S/(N+D) when -60dB FS signal is applied.
Note 9. Indicates inter-channel isolation between Lch and Rch when –1dBFS signal is input.
Note 10. INP1/INN1 and INP2/INN2 pins.
Note 11. IN1, IN2, IN3 and IN4 pins.
Note 12. MGNL/R[3:0] bits = 0h (0dB)
Note 13. MGNL/R[3:0] bits = 9h (18dB)
014006643-E-00
Unit
Bit
dB
dB
dB
dB
dB
Vp-p
Vp-p
2014/10
- 13 -
[AK7755]
4. Line-in Amp + ADC
Ta=25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V;
Signal Frequency 1kHz; Sampling Rate fs=48kHz; Measurement Frequency =20Hz to 20kHz
Sampling Rate fs=96kHz; Measurement Frequency =20Hz to 40kHz
CKM mode0(CKM[2:0]= “000”); BITFS[1:0]= “00” (64fs);
Parameter
Line-in Amp Resolution
+ ADC
Dynamic Characteristics
Fs=48kHz (Note 16)
Fs=48kHz (Note 17)
S/(N+D)
(-1dBFS) Fs=96kHz (Note 16)
Fs=96kHz (Note 17)
Fs=48kHz (A-weighted) (Note 16)
Dynamic
Fs=48kHz (A-weighted) (Note 17)
Range
Fs=96kHz (Note 16)
(Note 14)
Fs=96kHz (Note 17)
Fs=48kHz (A-weighted) (Note 16)
Fs=48kHz (A-weighted) (Note 17)
S/N
Fs=96kHz (Note 16)
Fs=96kHz (Note 17)
Analog Input
Input Voltage (Note 15)
(Note 16)
(Note 17)
Note 14. S/(N+D) when -60dB FS signal is applied.
Note 15. The Lin pin.
Note 16. LIGN[3:0] bits = 0h (0dB)
Note 17. LIGN[3:0] bits = Eh (+18 dB)
014006643-E-00
min
typ
77
90
86
88
85
100
90
95
86
100
90
95
86
92
92
2.00
2.20
0.277
max
24
Unit
Bit
dB
dB
dB
2.40
Vp-p
2014/10
- 14 -
[AK7755]
5. Line-out AMP Gain
Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V
Parameter
LOVOL1[3:0]bits=0h, LOVOL2[3:0]bits=0h,
LOVOL3[3:0]bits=0h
LOVOL1[3:0]bits=1h, LOVOL2[3:0]bits=1h,
LOVOL3[3:0]bits=1h
LOVOL1[3:0]bits=2h, LOVOL2[3:0]bits=2h,
LOVOL3[3:0]bits=2h
LOVOL1[3:0]bits=3h, LOVOL2[3:0]bits=3h,
LOVOL3[3:0]bits=3h
LOVOL1[3:0]bits=4h, LOVOL2[3:0]bits=4h,
LOVOL3[3:0]bits=4h
LOVOL1[3:0]bits=5h, LOVOL2[3:0]bits=5h,
LOVOL3[3:0]bits=5h
LOVOL1[3:0]bits=6h, LOVOL2[3:0]bits=6h,
LOVOL3[3:0]bits=6h
LOVOL1[3:0]bits=7h, LOVOL2[3:0]bits=7h,
Line
LOVOL3[3:0]bits=7h
-out
Gain
LOVOL1[3:0]bits=8h, LOVOL2[3:0]bits=8h,
AMP
LOVOL3[3:0]bits=8h
LOVOL1[3:0]bits=9h, LOVOL2[3:0]bits=9h,
LOVOL3[3:0]bits=9h
LOVOL1[3:0]bits=Ah, LOVOL2[3:0]bits=Ah,
LOVOL3[3:0]bits=Ah
LOVOL1[3:0]bits=Bh, LOVOL2[3:0]bits=Bh,
LOVOL3[3:0]bits=Bh
LOVOL1[3:0]bits=Ch, LOVOL2[3:0]bits=Ch,
LOVOL3[3:0]bits=Ch
LOVOL1[3:0]bits=Dh, LOVOL2[3:0]bits=Dh,
LOVOL3[3:0]bits=Dh
LOVOL1[3:0]bits=Eh, LOVOL2[3:0]bits=Eh,
LOVOL3[3:0]bits=Eh
LOVOL1[3:0]bits=Fh, LOVOL2[3:0]bits=Fh,
LOVOL3[3:0]bits=Fh
014006643-E-00
min
typ
max
Unit
mute
dB
-28
dB
-26
dB
-24
dB
-22
dB
-20
dB
-18
dB
-16
dB
-14
dB
-12
dB
-10
dB
-8
dB
-6
dB
-4
dB
-2
dB
0
dB
2014/10
- 15 -
[AK7755]
6. DAC+Line-out Amp
Ta= 25C; AVDD=TVDD=3.3V; DVDD=1.2V; AVSS=DVSS=0V;
Signal Frequency 1kHz; Sampling Rate fs=48kHz; Measurement Frequency =20Hz to 20kHz
Sampling Rate fs=96kHz; Measurement Frequency =20Hz to 40kHz
CKM mode0(CKM[2:0]=000); BITFS[1:0] bits = “00”; LOVOL1/2/3[3:0] bits = Fh(0dB);
Parameter
min
typ
max
Resolution
24
DAC
Dynamic Characteristics 1 (OUT1, OUT2, OUT3)
fs=48kHz
80
91
S/(N+D) (0 dBFS)
fs=96kHz
89
fs=48kHz (A-weighted)
100
106
Dynamic Range (Note 18)
fs=96kHz
101
fs=48kHz (A-weighted)
100
106
S/N
fs=96kHz
101
Inter-Channel Isolation (f=1kHz) (Note 19)
90
110
DC accuracy
Channel Gain Mismatch
0.0
0.5
Analog Output
Output Voltage
(Note 20)
2.28
2.51
2.74
Load Resistance
10
Load Capacitance
30
Note 18. S/(N+D) when -60dB FS signal is applied.
Note 19. Indicates inter-channel isolation between Lch and Rch of DAC when –1dBFS signal is input.
Note 20. Full-scale output voltage. The output voltage is proportional to AVDD (AVDD x 0.76).
014006643-E-00
Unit
Bit
dB
dB
dB
dB
dB
Vp-p
kΩ
pF
2014/10
- 16 -
[AK7755]
■ DC Characteristics
(Ta= -40 to 85C, AVDD=3.3V, DVDD=1.2V, TVDD=1.7 to 3.6V, AVSS=DVSS=0V)
Parameter
Symbol
min
typ
max
High Level Input Voltage
VIH
80%TVDD
Low Level Input Voltage
VIL
20%TVDD
SCL, SDA High Level Input Voltage
VIH
70%TVDD
SCL, SDA Low Level Input Voltage
VIL
30%TVDD
DMDAT1, DMDAT2 High Level Input Voltage
VIH2 65%AVDD
(DMIC1, DMIC2 bit = “1”)
DMDAT1, DMDAT2 Low Level Input Voltage
VIL2
35%AVDD
(DMIC1, DMIC2 bit = “1”)
TVDD-0.3
VOH
High Level Output Voltage Iout= -100A (Note 21)
0.3
VOL
Low Level Output Voltage Iout=100A (Note 22)
TVDD≥2.0V
VOL
0.4
SDA Low Level Output Voltage
Iout=3mA
TVDD<2.0V
VOL
20%TVDD
DMCLK1, DMCLK2 High Level Output Voltage
VOH2 AVDD-0.4
Iout = -80A
(DMIC1, DMIC2 bit = “1”)
DMCLK1, DMCLK2 Low Level Output Voltage
VOL2
0.4
Iout = 80A
(DMIC1, DMIC2 bit = “1”)
Input Leak Current (Note 23)
Iin
±10
77
Input Leak Current at Pulled-down Pins (Note 24)
Iid
17
Input Leak Current at XTI pin
lix
Note 21. Except XTO pin
Note 22. Except SDA and XTO pins.
Note 23. Internal Pulled-down pins, except the XTI pin
Note 24. The LRCK, BICK, SDOUT2/JX3/MAT0 and SDOUT3/JX2/MAT1 pins are internal
pulled-down pins (typ. 43 kΩ@3.3V).
■
Unit
V
V
V
V
V
V
V
V
V
V
V
A
A
A
Power Consumptions
(Ta=25C, AVDD=3.0 to 3.6V (typ=3.3V, max=3.6V), TVDD=1.7 to 3.6V (typ=3.3V, max=3.6V),
DVDD=1.14 to 1.3V (typ=1.2V, max=1.3V), AVSS=DVSS=0V)
Parameter
min
typ
max
AVDD
16
24
Power consumptions in operation 1 (Note 25)
TVDD
3
4.5
(LDOE pin = “L”)
DVDD
25
40
AVDD
48
72
Power consumptions in operation 2 (Note 25)
(LDOE pin = “H”)
TVDD
3
4.5
AVDD
10
Power consumptions in power-down
TVDD
10
(PDN pin= “L”, LDOE pin = “L”)
DVDD
200
Power consumptions in power-down
AVDD
1
(PDN pin= “L”, LDOE pin = “H”)
TVDD
1
Note 25. DVDD power consumption will be changed depending on DSP programs.
(e.g. It will be 6mA when using AKM’s Hands Free program.)
014006643-E-00
Unit
mA
mA
mA
mA
mA
uA
uA
uA
uA
uA
2014/10
- 17 -
[AK7755]
■ Digital Filter Characteritics
1. ADC
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
fs=48kHz (Note 26))
Parameter
Symbol
min
typ
max
Unit
Passband
PB
0
20.7
kHz
+0.14dB ~ 0.12dB
(Note 27)
-0.87dB
21.6
kHz
-3.0dB
22.8
kHz
Stoppband
SB
28.4
kHz
Passband Ripple
(Note 27)
PR
±0.14
dB
Stopband Ripple (Note 28, Note 29)
SA
65
dB
Group Delay Distorsion
0
μs
△GD
Group Daley
(Ts=1/fs)
GD
12.5
Ts
Note 26. The passband and stopband frequencies scale with “fs” (system sampling rate). The characteristic
of the high pass filter is not included.
Note 27. The passband is from DC to 18.9kHz when fs=48kHz.
Note 28. The stopband is 28kHz to 3.044MHz when fs=48kHz.
Note 29. When fs = 48kHz, the analog modulator samples the input signal at 3.072MHz. There is no
attenuation of an input signal in band (n x 3.072MHz ±21.99kHz; n=0, 1, 2, 3…) of integer times
of the sampling frequency by the digital filter.
2. DAC
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
fs=48kHz)
Parameter
Symbol
min
Typ
max
Unit
PB
Passband (Note 30) (±0.05dB)
0
21.7
kHz
(-6.0dB)
24
kHz
Stopband (Note 30)
SB
26.2
kHz
Passband Ripple
PR
±0.05
dB
Stopband Attenuation
SA
64
dB
Group Delay (Ts=1/fs) (Note 31)
GD
24
Ts
Digital Filter + Analog Filter
Amplitude Characteristics
20Hz to 20.0kHz
±0.5
dB
Note 30. The passband and stopband frequencies are proportional to “fs” (system sampling rate), and
represents PB=0.4535 × fs(@0.05dB) and SB=0.5465 × fs, respectively.
Note 31. The digital filter delay is calculated as the time from setting data into the input register until an
analog signal is output.
014006643-E-00
2014/10
- 18 -
[AK7755]
■ Switching Characteristics
1. System Clock
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol
min
typ
max
Unit
a) with a Crystal Oscillator:
11.2896
MHz
CKM[2:0]bits=0h
fXTI
12.288
16.9344
CKM[2:0]bits=1h
fXTI
MHz
18.432
b) with an External Clock
Duty Cycle
40
50
60
%
11.2896
CKM[2:0]bits=0h,2h
fXTI
11.0
12.4
MHz
12.288
16.9344
CKM[2:0]bits=1h
fXTI
16.5
18.6
MHz
18.432
LRCK Frequency
(Note 32)
fs
8
48
96
kHz
BICK Frequency
(Note 33)
TDM256 bit = “0”
High Level Width
tBCLKH
64
ns
(Normal Interface)
Low Level Width
tBCLKL
64
ns
Frequency
6.2
fBCLK
0.23
3.072
MHz
TDM256 bit = “1”
High Level Width
tBCLKH
32
ns
(TDM Interface)
Low Level Width
tBCLKL
32
ns
Frequency
12.3
fBCLK
1.8
12.288
MHz
Note 32. RCK frequency and sampling rate (fs) should be the same.
Note 33. When BICK is the source of the master clock, it should be synchronized to LRCK and have stable
frequency.
1/fXTI
1/fXTI
tXTI=1/fXTI
XTI
VIH
VIL
1/fs
ts=1/fs
1/fs
VIH
LRCK
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
BICK
VIL
tBCLKH
tBCLKL
Figure 4. System Clock Timing
014006643-E-00
2014/10
- 19 -
[AK7755]
2. Power Down
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V)
Parameter
Symbol
min
typ
max
Unit
PDN Pulse Width (Note 34)
tRST
600
ns
Note 34. The PDN pin must be set “L” when power up the AK7755.
PDN
tRST
VIL
Figure 5. Reset Timing
3. Serial Data Interface
SDIN1, SDIN2, SDOUT1, SDOUT2, SDOUT3
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol min
typ
max Unit
Slave Mode
Delay Time from BICK “↑” to LRCK (Note 35)
tBLRD 20
ns
Delay Time from LRCK to BICK “↑” (Note 35)
tLRBD 20
ns
Serial Data Input Latch Setup Time
tBSIDS 20
ns
Serial Data Input Latch Hold Time
tBSIDH 20
ns
Delay Time from LRCK to Serial Data Output (Note 36)
tLRD
20
ns
Delay Time from BICK “↓” to LRCK Output (Note 37)
tBSOD
20
ns
Master Mode
32, 48
BICK Frequency
fBCLK
fs
64, 256
BICK Duty Cycle
50
%
12
Delay Time from BICK “↓” to LRCK (Note 37)
tMBL
-12
ns
Serial Data Input Latch Setup Time
tBSIDS 20
ns
Serial Data Input Latch Hold Time
tBSIDH 20
ns
Delay Time from LRCK to Serial Data Output (Note 36)
tLRD
20
ns
Delay Time from BICK “↓” or “↑”to LRCK Output (Note 37)
tBSOD
20
ns
SDINn → SDOUTn (n=1, 2)
Delay Time from SDINn to SDOUTn Output
tIOD
60
ns
Note 35. BICK edge must not occur at the same time as LRCK edge.
If BICK polarity was inverted, the counting edge of BICK will be “↓”.
Note 36. Except I2S.
Note 37. When the polarity of BICK1 is inverted, delay time is from BICK1 “↑”.
SDOUT
n=1,2,3
Nn
50%TVDD
tIOD
SDINn
n=1,2
VIH
D
Figure 6. Serial Interface Delay Time from SDINn to SDOUTn Output
014006643-E-00
VIH
VIL
D
D
2014/10
- 20 -
[AK7755]
3-1. Slave Mode
VIH
VIL
D
LRCK
tBLRD
D
tLRBD
D
BICK
VIH
VIL
D
tBSIDS
D
tBSIDH
VIH
VIL
D
SDINn
n=1,2
D
Figure 7. Serial Interface Input Timing in Slave Mode
VIH
VIL
D
LRCK
D
tLRD
D
BICK
VIH
VIL
D
tBSOD
tLRD
tBSOD D
D
SDOUTn D
n=1,2,3
D
50%TVDD
D
Figure 8. Serial Interface Output Timing in Slave Mode
3-2. Master Mode
LRCK
50%TVDD
D
tMBL
tMBL
D
BICK
50%TVDD
tBSIDS
D
tBSIDH
VIH
VIL
D
SDINn
n=1,2
D
Figure 9. Serial Interface Input Timing in Master Mode
LRCK
50%TVDD
tLRD
D
BICK
tLRD
SDOUTn D
n=1,2,3
tBSOD
D
D
50%TVDD
tBSOD
D
D
50%TVDD
D
Figure 10. Serial Interface Output Timing in Master Mode
014006643-E-00
2014/10
- 21 -
[AK7755]
4. SPI Interface
4-1. Clock Reset (CKRESTN bit = “0”)
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol
min
typ
max
Unit
Microcontroller Interface Signal
SCLK Frequency
fSCLK
3.5
MHz
SCLK Low Level Width
tSCLKL
120
ns
SCLK High Level Width
tSCLKH
120
ns
Microcontroller → AK7755
CSN High Level Width
tWRQH
300
ns
Time from CSN “↑” to PDN “↑”
tRST
360
ns
Time from PDN“↑” to CSN “↓”
tIRRQ
1
ms
Time from RQN“↓” to SCLK“↓”
tWSC
360
ns
Time from SCLK“↑” to CSN“↑”
tSCW
480
ns
SI Latch Setup Time
tSIS
120
ns
SI Latch Hold Time
tSIH
120
ns
AK7755 → Microcontroller
SO Output Delay Time from SCLK “↓”
tSOS
120
ns
SO Output Hold Time from SCLK “↑”
tSOH
120
ns
(Note 38)
Note 38. Except when input the eighth bit of the command code.
4-2. PLL Clock (CKRESTN bit = “1”)
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol
min
typ
max
Unit
Microcontroller Interface Signal
SCLK Frequency
fSCLK
7
MHz
SCLK Low Level Width
tSCLKL
60
ns
SCLK High Level Width
tSCLKH
60
ns
Microcontroller → AK7755
CSN High Level Width
tWRQH
150
ns
Time from CSN “↑” to PDN “↑”
tRST
180
ns
Time from PDN“↑” to CSN “↓”
tIRRQ
1
ms
Time from RQN“↓” to SCLK“↓”
tWSC
150
ns
Time from SCLK“↑” to CSN“↑”
tSCW
240
ns
SI Latch Setup Time
tSIS
60
ns
SI Latch Hold Time
tSIH
60
ns
AK7755 → Microcontroller
SO Output Delay Time from SCLK “↓”
tSOS
60
ns
SO Output Hold Time from SCLK “↑”
tSOH
60
ns
(Note 38)
Note 39. It takes 10ms at maximum until PLL is locked, after setting CKRESTN bit to “1” from “0”.
014006643-E-00
2014/10
- 22 -
[AK7755]
VIH
VIL
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
VIH
PDN
VIL
VIH
CSN
VIL
tRST
tIRRQ
Figure 11. SPI Interface Timing 1
VIH
VIL
tWRQH
CSN
VIH
SI
VIL
tSIS
tSIH
VIH
VIL
SCLK
tWSC
tSCW
tWSC
tSCW
Figure 12. SPI Interface Timing 2 (Microcontroller → AK7755)
VIH
VIL
SCLK
VIH
SO
VIL
tSOS
tSOH
Figure 13. SPI Interface Timing 3 (AK7755 → Microcontroller)
014006643-E-00
2014/10
- 23 -
[AK7755]
5. I2C-BUS Interface
(Ta= -40 to 85C; AVDD=3.0 to 3.6V, TVDD=1.7 to 3.6V, DVDD=1.14 to 1.3V, AVSS=DVSS=0V,
CL=20pF)
Parameter
Symbol
min
typ
max
Unit
I2C Timing
SCL clock frequency
fSCL
400
kHz
Bus Free Time Between Transmissions
tBUF
1.3
s
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA
0.6
s
Clock Low Time
tLOW
1.3
s
Clock High Time
tHIGH
0.6
s
Setup Time for Repeated Start Condition
tSU:STA
0.6
s
SDA Hold Time from SCL Falling
tHD:DAT
0
0.9
s
SDA Setup Time from SCL Rising
tSU:DAT
0.1
s
Rise Time of Both SDA and SCL Lines
tR
0.3
s
Fall Time of Both SDA and SCL Lines
tF
0.3
s
Setup Time for Stop Condition
tSU:STO
0.6
s
Pulse Width of Spike Noise Suppressed By Input Filter
tSP
0
50
ns
Capacitive load on bus
Cb
400
pF
VIH
SDA
VIL
tBUF
tLOW tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
Figure 14. I2C BUS Interface Timing
6. Digital Microphone Interface
(AVDD=3.0~3.6V, TVDD=1.7~3.6V, DVDD=1.14~1.3V, AVSS=DVSS=0V, Ta= -40C~85C;
CL=100pF)
Parameter
Symbol
min
typ
max
DMDAT1, DMDAT2
Serial Data Input Latch Setup Time
tDMDS
50
Serial Data Input Latch Hold Time
tDMDH
0
Unit
ns
ns
DMCLK1, DMCLK2
Clock Frequency (Note 40)
fDMCK
0.5
64fs
6.2
Duty Cycle
dDMCK
40
50
60
Rise Time
tDMCKR
10
Fall Time
tDMCKF
10
Note 40. Clock frequency is determined by the sampling rate (fs) selected by DFS[2:0] bits.
014006643-E-00
MHz
%
ns
ns
2014/10
- 24 -
[AK7755]
tDMCK
65%AVDD
50%AVDD
35%AVDD
DMCLK1/2
tDMCKL
tDMCKF
tDMCKR
fDMCK = 1 / tDMCK
dDMCK = 100 x tDMKL / tDMCK
50%AVDD
DMCLK1/2
tDMDS
tDMDH
VIH2
DMDAT1/2
VIL2
DCLKP1, DCLKP2 bit = “1”
50%AVDD
DMCLK1/2
tDMDS
tDMDH
VIH2
DMDAT1/2
VIL2
DCLKP1, DCLKP2 bit = “0”
Figure 15. Digital Microphone Interface Timing Wave Form
014006643-E-00
2014/10
- 25 -
[AK7755]
9. Functional Description
■ System Clock
Master/Slave mode switching, clock source pin select for internal master clock (MCLK) generating clock
(ICLK), and ICLK frequency change are controlled by CKM [2:0] clock mode select bits. CKM[2:0] bits
can only be set during clock reset.
Use of
crystal
oscillator
XTI(12.288MHz)
0
000
Master
XTI
DFS[2:0]bits
Available
1
001
Master
XTI
DFS[2:0]bits
XTI(18.432MHz)
Available
XTI(12.288MHz), BICK,
Not
2
010
Slave
XTI
DFS[2:0]bits
LRCK
Available
Not
3
011
Slave
BICK
DFS[2:0]bits
BICK, LRCK
Available
Not
5
101
Slave
BICK
Fs=16kHz Fixed
BICK, LRCK(fs=8kHz)
Available
Note 41. The sampling frequency is set by DFS[2:0] bits (CONT00). The BICK frequency is set by
BITFS[1:0] bits.
Note 42. In CKM mode 2, XTI, BICK and LRCK must be synchronized but the phase is not critical.
Note 43. CKM mode5 is the mode that operates DSP, ADC and DAC by 16kHz sampling frequency when
LRCK sampling frequency is 8kHz. The BICK sampling frequency for LRCK is set by
BITFS[1:0] bits.
CKM
mode
CKM
[2:0]
Master
Slave
ICLK
Source
Sampling Frequency
fs (Note 41)
Input pin(s) required for
system clock
1. Relationship between MCLK Generating Clock (ICLK) and MCLK
CKM mode 0/1/2
XTI Pin
ICLK
Divider
REFCLK
PLL
MCLK
(MCLK Source)
CKM mode 3/5
BICK Pin
ICLK
Divider
REFCLK
PLL
MCLK
(MCLK Source)
Figure 16. Relation Ship between ICLK and MCLK
2. Sampling Frequency Select
FS mode
0
1
2
3
4
5
6
7
DFS[2:0]
000
001
010
011
100
101
110
111
fs: Sampling Frequency
8kHz
12kHz (11.025kHz)
16kHz
24kHz (22.05kHz)
32kHz
48kHz (44.1kHz)
96kHz (88.2kHz)
N/A
014006643-E-00
2014/10
- 26 -
[AK7755]
2-1. Master Mode (CKM mode 0, 1: Using XTI Input Clock)
CKM
mode
0
1
CKM
[2:0]
000
001
XTI
fs:48kHz series
12.288MHz
18.432MHz
fs:44.1kHz series
11.2896MHz
16.9344MHz
fs: Sampling Frequency
Input Frequency Range
Use of Chrystal
(MHz)
Oscillator
11.0 to 12.4
Available
16.7 to 18.6
Available
Input system clock to the XTI pin by setting BITFS[1:0] bits. The internal counter which is synchronized to
XTI generates LRCK(1fs) and BICK(64fs, 48fs, 32fs, 256fs). BICK frequency can be selected by
BITFS[1:0] bits. The BICK output will be in two different frequencies if setting BITFS[1:0] bits = 1h
(48kHz) when the sampling frequency is 12kHz, 24kHz, 48kHz or 96kHz (DFS[2:0]). LRCK and BICK are
not output during system reset.
XTI
XTI
External Clock
XTO
AK7755
XTO
Figure 17. Using Crystal Oscillator (CKM mode 0/1)
AK7755
Using External Clock (CKM mode 0/1)
2-2. Slave Mode1 (CKM mode 2: XTI Input Clock）
CKM
mode
2
CKM
[2:0]
010
XTI
fs:48kHz
12.288MHz
fs:44.1kHz
11.2896MHz
fs: sampling frequency
Input Frequency Range Use of Chrystal
Oscillator
(MHz)
11.0 to 12.4
Not Available
Required System Clocks are XTI, LRCK and BICK. XTI and LRCK must be synchronized, but the phase
between these clocks is not important. The system sampling rate is controlled by DFS[2:0] bits. The
sampling frequency of BICK is set by BITFS[1:0] bits.
2-3. Slave Mode 2 (CKM mode 3: BICK Input Clock)
In CKM mode 3, required system clocks are BICK and LRCK. In this mode, BICK is used for clock source
instead of XTI. This clock is multiplied directly by a PLL to generate the master clock (MCLK). Therefore
BICK with two different frequencies cannot be used. BICK and LRCK must be synchronized. Set BICK
frequency for LRCK by BITFS[1:0] bits. The sampling rate is determined by DFS[2:0] bits setting. In
applications which do not need the XTI pin of the AK7755, leave this pin open.
014006643-E-00
2014/10
- 27 -
[AK7755]
2-4. Slave Mode 3 (CKM mode 5: BICK Input Clock)
CKM mode5 is the mode that operates DSP, ADC and DAC by 16kHz sampling frequency when LRCK
sampling frequency is 8kHz. Set BICK frequency against LRCK by BITFS[1:0] bits. Each sampling
frequency is fixed (LRCK = 8kHz, DSP/ADC/DAC = 16kHz).
AK7755
LRCK
BICK
SDIN1
SDOUT1
(fs=8kHz)
16k/8k
Converter
DSP/ADC/DAC
(fs=16kHz)
SDIN2
SDOUT2
SDOUT3
(fs=16kHz)
Figure 18. Slave Mode3 (CKM mode5) Sampling Frequency Setting
DFS
[2:0]
0h
0h
0h
0h
1h
1h
1h
1h
2h
2h
2h
2h
3h
3h
3h
3h
4h
4h
4h
4h
5h
5h
5h
5h
6h
6h
6h
6h
7h
fs
8kHz
8kHz
8kHz
8kHz
12kHz
12kHz
12kHz
12kHz
16kHz
16kHz
16kHz
16kHz
24kHz
24kHz
24kHz
24kHz
32kHz
32kHz
32kHz
32kHz
48kHz
48kHz
48kHz
48kHz
96kHz
96kHz
96kHz
96kHz
N/A
fs: Sampling Frequency
BITFS
BICK Frequency
[1:0]
BICK
44.1kHz series 48kHz series
0h
64fs
470.4kHz
512kHz
1h
48fs
352.8kHz
384kHz
2h
32fs
235.2kHz
256kHz
3h
256fs
1881.6kHz
2048kHz
0h
64fs
705.6kHz
768kHz
1h
48fs
N/A
N/A
2h
32fs
352.8kHz
384kHz
3h
256fs
2822.4kHz
3072kHz
0h
64fs
940.8kHz
1024kHz
1h
48fs
705.6kHz
768kHz
2h
32fs
470.4kHz
512kHz
3h
256fs
3763.2kHz
4096kHz
0h
64fs
1.4112MHz
1.536MHz
1h
48fs
1058.4MHz
1.152MHz
2h
32fs
705.6kHz
768kHz
3h
256fs
5.6448MHz
6.144MHz
0h
64fs
1.8816MHz
2.048MHz
1h
48fs
1.4112MHz
1.536MHz
2h
32fs
0.9408MHz
1.024MHz
3h
256fs
7.5264MHz
8.192MHz
0h
64fs
2.8224MHz
3.072MHz
1h
48fs
2.1168MHz
2.304MHz
2h
32fs
1.4112MHz
1.536MHz
3h
256fs
11.2896MHz
12.288MHz
0h
64fs
5.6448MHz
6.144MHz
1h
48fs
4.2336MHz
4.608MHz
2h
32fs
2.8224MHz
3.072MHz
3h
256fs
22.5792MHz
24.576MHz
－
－
－
－
(N/A: Not available)
Table 1. Clock Select
014006643-E-00
2014/10
- 28 -
[AK7755]
BITFS[1:0] bits = 0h @(LRIF[1:0] bits = 0h)
LRCK
Right ch
Left ch
BICK
32×BICK
32×BICK
Figure 19. BITFS[1:0] bits = 0h(64fs) (LRIF[1:0]bits = 0h)
BITFS[1:0] bits = 1h @(LRIF[1:0] bits = 0h)
LRCK
Right ch
Left ch
BICK
24×BICK
24×BICK
Figure 20. BITFS[1:0] bit s= 1h(48fs) (LRIF[1:0]bits = 0h)
BITFS[1:0] bits = 2h @(LRIF[1:0] bits = 0h)
LRCK
Right ch
Left ch
BICK
16×BICK
16×BICK
Figure 21. BITFS[1:0] bits = 2h(32fs) (LRIF[1:0]bits = 0h)
Refer to Figure 40 and Figure 42 when BITFS[1:0] bits = 3h (256fs).
014006643-E-00
2014/10
- 29 -
[AK7755]
■ Control Register Settings
Control registers are reset by a power down release (PDN pin = “L” → “H”). Since control registers
CONT00-CONT01 are related to clock generation, they must be changed during clock reset (CKRSTN bit
(CONT01: D0) = “0”). CONT12-CONT19 can be written during operation. The other control registers must
be changed during clock reset or system reset (CRESETN bit (CONT0F: D3) and DSPRESETN bit
(CONT0F: D2) = “0”) to avoid errors and noises.
CONT0D: D6, CONT1A: D4, CONT26: D0 and CONT2A: D7 bits must be set to “1” during system reset.
Once these bits are set to “1”, the value will be kept until power down the AK7755 (PDN pin = “L”). Do
not write to the CONT1F-CONT25, CONT27-CONT29 and CONT2B-CONT3F registers.
CONT00-CONT1E, CONT26, CONT2A
Name
CONT00
CONT01
CONT02
CONT03
CONT04
CONT05
CONT06
CONT07
CONT08
CONT09
CONT0A
CONT0B
CONT0C
CONT0D
CONT0E
CONT0F
CONT10
CONT11
CONT12
CONT13
CONT14
CONT15
CONT16
CONT17
CONT18
CONT19
CONT1A
CONT1B
CONT1C
CONT1D
CONT1E
CONT26
CONT2A
D7
D6
D5
D4
D3
D2
0
CKM[2]
CKM[1]
CKM[0]
AINE
DFS[2]
JX2E
LRDOWN
BITFS[1]
BITFS[0]
CLKS[2]
CLKS[1]
TDM256
BCKP
LRIF[1]
LRIF[0]
TDMMODE[1] TDMMODE[0]
DIF2[1]
DIF2[0]
DOF2[1]
DOF2[0]
BANK[3]
BANK[2]
DRMS[1]
DRMS[0]
DRAM[1]
DRAM[0]
POMODE
0
ACCRAM
JX3E
FIRMODE1
FIRMODE2
SUBMODE1 SUBMODE2
CLRN
DEM[1]
DEM[0]
DIFDA[1]
DIFDA[0]
0
DIF1[2]
DOF4[1]
DOF4[0]
DOF3[1]
DOF3[0]
0
DOF1[2]
SELDAI[1]
SELDAI[0]
SELDO3[1]
SELDO3[0]
SELDO2[1]
SELDO2[0]
DIFR
INR
DIFL
INL
LO3SW3
LO3SW2
CLKOE
BICKE
LRCKE
0
0
OUT3E
0
0
0
0
0
0
DSM
0
ATSPAD
ATSPDA
0
SELDO1[2]
STO
1
0
0
0
0
PMADR
PMADL
PMAD2L
PMLO3
PMLO2
PMLO1
0
0
PML1
LRDETN
CRESETN
DSPRESETN
WDTEN
CRCE
PLLLOCKE
SOCFG
SELSTO
0
CKADJ[7]
CKADJ[6]
CKADJ[5]
CKADJ[4]
CKADJ[3]
CKADJ[2]
MGNR[3]
MGNR[2]
MGNR[1]
MGNR[0]
MGNL[3]
MGNL[2]
LIGN[3]
LIGN[2]
LIGN[1]
LIGN[0]
LOVOL3[3]
LOVOL3[2]
LOVOL2[3]
LOVOL2[2]
LOVOL2[1]
LOVOL2[0]
LOVOL1[3]
LOVOL1[2]
VOLADL[7]
VOLADL[6]
VOLADL[5]
VOLADL[4]
VOLADL[3]
VOLADL[2]
VOLADR[7] VOLADR[6] VOLADR[5] VOLADR[4] VOLADR[3] VOLADR[2]
VOLAD2L[7] VOLAD2L[6] VOLAD2L[5] VOLAD2L[4] VOLAD2L[3] VOLAD2L[2]
VOLDAL[7]
VOLDAL[6]
VOLDAL[5]
VOLDAL[4]
VOLDAL[3]
VOLDAL[2]
VOLDAR[7] VOLDAR[6] VOLDAR[5] VOLDAR[4] VOLDAR[3] VOLDAR[2]
ADMUTE
AD2MUTE
DAMUTE
1
ADRCRE
ADRCLE
AMGNR[3]
AMGNR[2]
AMGNR[1]
AMGNR[0]
AMGNL[3]
AMGNL[2]
0
0
0
0
0
0
VOLAD2R[7] VOLAD2R[6] VOLAD2R[5] VOLAD2R[4] VOLAD2R[3] VOLAD2R[2]
DMIC1
DMCLKP1
DMCLKE1
DMIC2
DMCLKP2
DMCLKE2
0
0
0
0
0
0
1
0
0
0
0
0
014006643-E-00
D1
DFS[1]
CLKS[0]
JX1E
BANK[1]
WAVP[1]
D0
DFS[0]
CKRESETN
JX0E
BANK[0]
WAVP[0]
Default
00h
00h
00h
00h
00h
MEMDIV[1]
MEMDIV[0]
00h
DIF1[1]
DIF1[0]
DOF1[1]
DOF1[0]
SELMIX[1]
SELMIX[0]
LO3SW1
SELMIX[2]
OUT2E
OUT1E
0
0
SELDO1[1]
SELDO1[0]
0
DLS
PMDAR
PMDAL
PMAD2R
DLRDY
0
CKADJEN
CKADJ[1]
CKADJ[0]
MGNL[1]
MGNL[0]
LOVOL3[1]
LOVOL3[0]
LOVOL1[1]
LOVOL1[0]
VOLADL[1]
VOLADL[0]
VOLADR[1] VOLADR[0]
VOLAD2L[1] VOLAD2L[0]
VOLDAL[1]
VOLDAL[0]
VOLDAR[1] VOLDAR[0]
MICRZCE
MICLZCE
AMGNL[1]
AMGNL[0]
0
0
VOLAD2R[1] VOLAD2R[0]
0
0
0
1
0
0
00h
00h
00h
00h
00h
00h
00h
80h
00h
00h
00h
00h
00h
00h
00h
30h
30h
30h
18h
18h
00h
00h
00h
30h
00h
00h
00h
2014/10
- 30 -
[AK7755]
CONT00: Clock Setting 1, Analog Input Setting
Write during clock reset.
W
C0h
R
40h
Name
CONT00
D7
0
D6
CKM[2]
D5
CKM[1]
D4
CKM[0]
D6, D5, D4: CKM[2:0] Clock Mode Setting
CKM
CKM Master
Main Clock
mode
[2:0] Slave
0
000
Master XTI=12.288MHz fixed
1
001
Master XTI=18.432MHz fixed
2
010
Slave
XTI=12.288MHz fixed
3
011
Slave
BICK
5
101
Slave
BICK
D3
AINE
D2
DFS[2]
D1
DFS[1]
D0
DFS[0]
fs
System Clock
fs=8~96kHz
fs=8~96kHz
fs=8~96kHz
fs=8~96kHz
XTI
XTI
XTI, BICK, LRCK
BICK, LRCK
BICK,
LRCK(fs=8kHz)
fs=16kHz
Default
00h
(default)
TDM256 bit (CONT02: D7) = “1” cannot be used in CKM mode5.
D3: AINE Analog Input Setting (IN1/INP1, IN2/INN1, IN3/INP2, IN4/INN2 pin)
0: Not Using Analog Input (default)
1: Using Analog Input
Set AINE bit to “1” first before other control register settings when using the IN1/INP1, IN2/INN1,
IN3/INP2 and IN4/INN2 pins as analog inputs. The AK7755 starts charging to a capacitor connected
to each pin by this setting.
Set AINE bit to “0” when using digital microphones (DMIC1 or DMIC2 bit (CONT1E: D7, D4)=
“1”).
D2, D1, D0: DFS[2:0] Sampling Frequency
fs
DFS mode
DFS[2:0]
0
000
8kHz
(default)
1
001
12kHz
2
010
16kHz
3
011
24kHz
4
100
32kHz
5
101
48kHz
6
110
96kHz
7
111
N/A
Multiply 44.1/48 to calculate the values for multiple sampling frequencies of 44.1kHz.
Write “0” into the “0” registers.
014006643-E-00
2014/10
- 31 -
[AK7755]
CONT01: Clock Setting 2 and JX2 Setting
Write during clock reset.
W
R
Name
D7
C1h
41h
CONT01 JX2E
D6
LR
DOWN
D5
BITFS
[1]
D4
BITFS
[0]
D3
CLKS
[2]
D2
CLKS
[1]
D1
CLKS
[0]
D0
CK
RESETN
Default
00h
D7: JX2E External Conditional Jump 2 Enable
0: JX2 is Disabled (default), No. 14-pin output (SDOUT3) when OUT3E bit (CONT0A:D2) = “1”
1: JX2 is Enabled, No. 14-pin Input
D6: LRDOWN LRCK Sampling Frequency Select
0: LRCK Sampling frequency set by DFS[2:0] bits (CONT00: D2-D0). (default)
1: LRCK Half frequency of the setting value by DFS[2:0] bits
The AK7755 can output the LRCK which is half frequency of the setting value by DFS[2:0] bits
in master mode (CKM mode 0, 1(CONT00: D6-D4)). This mode is used when
LRCK/BICK/SDIN1/SDOUT1 is driven by fs= 8kHz while the AK7755 is driven by fs= 16kHz
in master mode. LRDOWN bit = “1” cannot be set when TDM256 bit (CONT02: D7) = “1”.
D5, D4: BITFS[1:0] BICK fs Select
BITFS
BITFS
BICK Note
mode
[1:0]
0
00
64fs
512kHz(@fs=8kHz),3.072MHz(@fs=48kHz)
(default)
1
01
48fs
384kHz(@fs=8kHz),2.304MHz(@fs=48kHz)
2
10
32fs
256kHz(@fs=8kHz),1.536MHz(@fs=48kHz)
3
11
256fs
2.048MHz(@fs=8kHz),12.288MHz(@fs=48kHz)
This setting is valid in both slave and master modes.
Set the BICK input sampling frequency against LRCK, in Slave mode (CKM2, 3 and 5).
Set the BICK output sampling frequency against LRCK in Master mode (CKM0 and 1).
The BICK output will be in two different frequencies if setting BITFS[1:0] bits = 1h (48kHz) when
the sampling frequency is 12kHz, 24kHz, 48kHz or 96kHz (DFS[2:0]).
D3, D2, D1: CLKS[2:0] CLKO Output Clock Select
CLKS mode CLKS[2:0]
fs=48kHz
fs=44.1kHz
0
000
12.288MHz
11.2896MHz
1
001
6.144MHz
5.6448MHz
2
010
3.072MHz
2.8224MHz
3
011
8.192MHz
7.5264MHz
4
100
4.096MHz
3.7632MHz
5
101
2.048MHz
1.8816MHz
6
110
256fs
256fs
7
111
XTI or BICK
XTI or BICK
(default)
D0: CKRESETN Clock Reset
0: Clock Reset (default)
1: Clock Reset Release
014006643-E-00
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[AK7755]
CONT02: Serial Data Format, JX1, 0 Setting
W
R
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
C2h 42h CONT02 TDM256 BCKP LRIF[1] LRIF[0] TDM
TDM
JX1E JX0E 00h
MODE[1] MODE[0]
D7: TDM256, TDM Select
0: Normal Interface (default)
1: TDM Interface
BICK is fixed to 256fs. Set BITFS[1:0] bits = 3h (CONT01: D5, D4). Format is selected by
LRIF[1:0] bits setting (CONT02: D5, D4). In this mode, CKM mode 5(CONT00: D6-D4) is not
available. TDM256 bit cannot be set to “1” when LRDOWN bit (CONT00: D6) = “1”. In TDM
mode, a 96kHz sampling frequency is not available. DFS[2:0] bits (CONT00: D2-D0) setting
must be lower than 5h (48kHz).
D6: BCKP BICK Edge Select
BCKP bit BICK edge referenced to LRCK edge
0
falling (FE)
1
rising (RE)
(default)
D5, D4: LRIF[1:0] LRCK I/F Format
Mode LRIF[1:0]bit
Digital I/F Format
0
00
Standard (MSB justified/ LSB justified) (default)
1
01
I2S Compatible
2
10
PCM Short Frame
3
11
PCM Long Frame
In standard format mode, MSB justified and 24/20/16 bit LSB justified formats are selectable by DIF1
bits (CONT06: D2-D0), DIF2 bits (CONT03: D7, D6), DIFDA bits (CONT06: D5, D4), DOF1 bits
(CONT07: D2-D0), DOF2 bits (CONT03: D5, D4), DOF3 bits (CONT07: D5, D4), and DOF4 bits
(CONT07: D7, D6). In other modes, MSB justified format should be selected by DIF1-2 bits, DAF bit
and DOF1-4 bits.
D3, D2: TDMMODE[1:0] DSPDIN3, DSPDIN4 Input Source Select (Valid when TDM256bit = “1”)
Mode
0
1
2
3
TDMMODE
[1:0]
00
01
10
11
DSPDIN4 Lch
DSPDIN4 Rch
DSPDIN3 Lch
DSPDIN3 Rch
SDIN1 SLOT7
SDOUTAD Lch
SDOUTAD Lch
N/A
SDIN1 SLOT8
SDOUTAD Rch
SDOUTAD Rch
N/A
SDIN1 SLOT5
SDIN1 SLOT5
SDOUTAD2 Lch
N/A
SDIN1 SLOT6
SDIN1 SLOT6
SDOUTAD2 Rch
N/A
(default)
D1: JX1E External Conditional Jump1 Enable
0: JX1 is invalid (default)
1: JX1 is valid
D0: JX0E External Conditional jump0 Enable
0: JX0 is invalid (default)
1: JX0 is valid
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[AK7755]
CONT03: Delay RAM, DSP Input / Output Setting
W
C3h
R
43h
Name
D7
CONT03 0
D6
0
D5
0
D4
0
D3
BANK[3]
D2
BANK[2]
D1
BANK[1]
D0
BANK[0]
Default
00h
D7, D6: DIF2[1:0] DSP DIN2 Input Format Select
DIF2 Mode DIF2[1:0] Input Data Format
0
00
MSB (24-bit)
(default)
1
01
LSB 24-bit
2
10
LSB 20-bit
3
11
LSB 16-bit
Set “00” for I2S compatible, PCM Short and PCM Long formats.
Set “11” when BITFS[1:0] bits (CONT01: D5, D4) = 2h (32fs).
D5, D4: DOF2[1:0] DSP DOUT2 Output Format Select
DOF2 Mode DOF2[1:0] Output Data Format
0
00
MSB (24-bit)
(default)
1
01
LSB 24-bit
2
10
LSB 20-bit
3
11
LSB 16-bit
2
Set “00” for I S compatible, PCM Short and PCM Long formats.
Set “11” when BITFS[1:0] bits = 2h (32fs).
D3, D2, D1, D0: BANK[3:0]
DLRAM
BANK
Partition
[3:0]
mode
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
1001
9-15
1111
DLRAM mode Setting
Delay RAM
Bank1
Bank0
Linear 20.4f
Ring 20.4f
0
8192 words
1024 words
7168 words
2048 words
6144 words
3072 words
5120 words
4096 words
4096 words
5120 words
3072 words
6144 words
2048 words
7168 words
1024 words
8192 words
0
(default)
N/A
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[AK7755]
CONT04: Data RAM, CRAM Setting
W R
Name
D7
D6
D5
D4
D3
D2 D1
C4h 44h CONT04 DRMS[1] DRMS[0] DRAM[1] DRAM[0] POMODE 0
Default
WAVP[1] WAVP[0] 00h
D7, D6: DRMS[1:0]
DRAM
mode
0
1
2
3
Data RAM Size Setting
DSP Data RAM
DRMS
Bank1
Bank0
[1:0]
Memory
Memory
size[words]
size[words]
00
512
1536
01
1024
1024
10
1536
512
11
N/A
D0
D5, D4: DRAM[1:0] Data RAM Addressing mode Setting
DSP Data RAM
Addressing DRAM
mode
[1:0]
Bank1 DP1
Bnak0 DP0
0
00
Ring
Ring
1
01
Ring
Linear
2
10
Linear
Ring
3
11
Linear
Linear
(default)
(default)
D3: POMODE DLRAM Pointer 0 Select
0: DBUS Immediate (default)
1: OFREG
D1, D0: WAVP[1:0] CRAM Memory Assignment
WAVP mode WAVP[1:0]
FFT Point Number
0
00
33word
128
1
01
65word
256
2
10
129word
512
3
11
257word
1024
(default)
Write “0” into the “0” registers.
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[AK7755]
CONT05: Accelerator Setting, JX3 Setting
W
R
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
ACCRAM
FIR
FIR
SUB
SUB
MEM MEM
C5h 45h CONT05
JX3E
00h
CLRN
MODE1 MODE2 MODE1 MODE2 DIV[1] DIV[0]
D7: ACCRAMCLRN Accelerator CRAM Clear Setting
0: Accelerator CRAM is cleared by 0 data after releasing reset. (default)
1: Accelerator CRAM is not cleared after releasing reset.
D6: JX3E External Conditional Jump3 Enable
0: JX3 Disable (default), No. 15 pin output (SDOUT2) when OUT2E bit (CONT0A:D1) = “1”
1: JX3 Enable, No. 15 pin Input
D5: FIRMODE1 Accelerator Ch1 Operation Select
0: Adaptive Filter (default)
1: FIR Filter
D4: FIRMODE2 Accelerator Ch2 Operation Select
0: Adaptive Filter (default)
1: FIR Filter
D3: SUBMODE1 Accelerator Ch1 Mode Select
0: Fullband (default)
1: Subband
D2: SUBMODE2 Accelerator Ch2 Mode Select
0: Fullband (default)
1: Subband
D1, D0: MEMDIV[1:0] Accelerator Memory Select
MODE
MEMDIV[1:0]
ch1
ch2
0
00
2048
(default)
1
01
1792
256
2
10
1536
512
3
11
1024
1024
Write “0” into the “0” registers.
014006643-E-00
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[AK7755]
CONT06: DAC De-emphasis, DAC and DSP Input Format Settings
W R Name
D7
D6
D5
D4
D3 D2
D1
D0
Default
C6h 46h CONT06 DEM[1] DEM[0] DIFDA[1] DIFDA[0] 0
DIF1[2] DIF1[1] DIF1[0] 00h
D7, D6: DEM[1:0]
DAC De-emphasis Setting (50/15μs)
DEM mode
DEM[1:0]
Sampling Frequency fs
0
00
OFF
(default)
1
01
48kHz
2
10
44.1kHz
3
11
32kHz
D5, D4: DIFDA[1:0] DAC Input Format Select
DIFDA mode DIFDA[1:0]
Input Data Format
0
00
MSB justified (24-bit)
(default)
1
01
LSB justified 24-bit
2
10
LSB justified 20-bit
3
11
LSB justified 16-bit
Set “00” for I2S Compatible, PCM Short and PCM Long formats.
Set “11” when BITFS[1:0] bits (CONT01: D5, D4) =2h (32fs).
Set “00” when connecting MIXOUT or DSP-DOUT4 to DAC input.
D2, D1, D0: DIF1[2:0] DSP DIN1 Input Format Select
DIF1 Mode DIF1[2:0] Input Data Format
0
000
MSB (24-bit)
(default)
1
001
LSB 24-bit
2
010
LSB 20-bit
3
011
LSB 16-bit
4
100
MSB 8-bit μ-Law
5
101
MSB 8-bit A-Law
6
110
N/A
7
111
N/A
2
Set “000” for I S Compatible, PCM Short and PCM Long formats.
Set “011” when BITFS[1:0]=2h (32fs).
Write “0” into the “0” registers.
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[AK7755]
CONT07: DSP Output Format Setting
W R Name
D7
D6
D5
D4
D3 D2
D1
D0
Default
C7h 47h CONT07 DOF4[1] DOF4[0] DOF3[1] DOF3[0] 0 DOF1[2] DOF1[1] DOF1[0] 00h
D7, D6: DOF4[1:0] DSP DOUT4 Output Format Select
DOF4 mode
DOF4[1:0]
Output Data Format
0
00
MSB justified (24-bit)
(default)
1
01
LSB justified 24-bit
2
10
LSB justified 20-bit
3
11
LSB justified 16-bit
Set “00” for I2S Compatible, PCM Short and PCM Long formats.
Set “11” when BITFS[1:0] bits (CONT01: D5, D4) =2h (32fs).
Set “00” when connecting to the DAC.
D5, D4: DOF3[1:0] DSP DOUT3 Output Format Select
DOF3 mode
DOF3[1:0]
Output Data Format
0
00
MSB justified (24-bit)
(default)
1
01
LSB justified 24-bit
2
10
LSB justified 20-bit
3
11
LSB justified 16-bit
Set “00” for I2S Compatible, PCM Short and PCM Long formats.
Set “11” when BITFS[1:0] bits=2h (32fs).
D2, D1, D0: DOF1[2:0] DSP DOUT1 Output Format Select
DOF1 mode
DOF1[2:0] Output Data Format
0
000
MSB (24-bit)
(default)
1
001
LSB 24-bit
2
010
LSB 20-bit
3
011
LSB 16-bit
4
100
MSB 8-bit μ-Law
5
101
MSB 8-bit A-Law
6
110
N/A
7
111
N/A
Set “000” for I2S Compatible, PCM Short and PCM Long formats.
Set “011” when BITFS[1:0] bits=2h (32fs).
Write “0” into the “0” registers.
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[AK7755]
CONT08: DAC Input, SDOUT2/3 Output, Digital Mixer Input Setting
W
R
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
SELDAI SELDAI SELDO3 SELDO3 SELDO2 SELDO2 SELMIX SELMIX
C8h 48h CONT08
00h
[1]
[0]
[1]
[0]
[1]
[0]
[1]
[0]
D7, D6: SELDAI[1:0] DAC Input Select
SELDAI mode
SELDAI[1:0]
Input Data
0
00
DSP DOUT4 (default)
1
01
MIXOUT
2
10
SDIN2
3
11
SDIN1
Set DIFDA[1:0] bits (CONT06: D5, D4) = 0h when selecting DSP DOUT4 or MIXOUT.
D5, D4: SELDO3[1:0] SDOUT3 pin Output Select
SELDO3 mode SELDO3[1:0]
Output Data
0
00
DSP DOUT3
(default)
1
01
MIXOUT
2
10
DSP DOUT4
3
11
SDOUTAD2
The output format is fixed to MSB 24-bit when selecting SDOUTAD2 or MIXOUT.
D3, D2: SELDO2[1:0] SDOUT2 pin Output Select
SELDO2 mode SELDO2[1:0]
Output Data
0
00
DSP DOUT2 (default)
1
01
GP1
2
10
SDIN2
3
11
SDOUTAD2
The output format is fixed to MSB 24-bit when selecting SDOUTAD2.
(CONT09 D0), D1, D0: SELMIX[2:0] Digital Mixer Input Select
SELMIX mode SELMIX[2:0] MIXOUT Lch
MIXOUT Rch
1
000
SDOUTAD Lch
SDOUTAD Rch
SDOUTAD Lch/2
1
001
SDOUTAD Rch
+ SDOUTAD2 Lch/2
SDOUTAD Rch /2
2
010
SDOUTAD Lch
+ SDOUTAD2 Rch/2
SDOUTAD2 Lch
3
011
SDOUTAD2 Rch
4
100
DSP-DOUT4 Lch
SDOUTAD2 Rch
5
101
SDOUTAD2 Lch
DSP-DOUT4 Rch
6
110
DSP-DOUT4 Lch
SDOUTAD Rch
7
111
SDOUTAD Lch
DSP-DOUT4 Rch
014006643-E-00
(default)
2014/10
- 39 -
[AK7755]
CONT09: Analog Input / Output Setting
W
R
Name
D7
D6 D5
D4 D3
D2
D1
D0
Default
C9h 49h CONT09 DIFR INR DIFL INL LO3SW3 LO3SW2 LO3SW1 SELMIX[2] 00h
D7, D6: DIFR, INR ADC Rch Analog Input
DIFR bit INR bit
ADC Rch
0
0
IN3
(default)
0
1
IN4
1
X
INP2/INN2
ADC
Lch
DIFL bit
MIC-Amp
Lch
INR bit
IN3/INP2 pin
IN4/INN2 pin
D5, D4: DIFL, INL ADC Lch Analog Input
DIFL bit INL bit
ADC Lch
0
0
IN1
(default)
0
1
IN2
1
X
INP1/INN1
AK7755
INL bit
IN1/INP1 pin
IN2/INN1 pin
ADC
Rch
DIFR bit
MIC-Amp
Rch
Figure 22. Analog Input Select
D3: LO3SW3 OUT3 Mixing Select 3
0: LIN off (default)
1: LIN on
D2: LO3SW2 OUT3 Mixing Select 2
0: DAC Rch off (default)
1: DAC Rch on
D1: LO3SW1 OUT3 Mixing Select 1
0: DAC Lch off (default)
1: DAC Lch on
AK7755
Mono
ADC
LIN pin
Stereo
DAC Lch
OUT1 pin
LOVOL1[3:0]
LIGN[3:0]
Stereo
DAC Rch
OUT2 pin
LO3SW1
LO3SW2
LO3SW3
LOVOL2[3:0]
M
I
X
OUT3 pin
LOVOL3[3:0]
Figure 23. OUT3 Output Select
D0: SELMIX[2] Digital Mixer Input Select
Refer to CONT08: D1, D0, SELMIX[2:0] bits
014006643-E-00
2014/10
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[AK7755]
CONT0A: CLK and SDOUT Output Setting
W
CAh
R
4Ah
Name
D7
CONT0A CLKOE
D6
BICKOE
D5
LRCKOE
D4
0
D3 D2
D1
D0
Default
0
OUT3E OUT2E OUT1E 00h
D7: CLKOE CLKO pin Setting
0: CLKO= “L” (default)
1: CLKO Output Enable
D6: BICKOE BICK pin Output Setting
0: BICKO= “L” (default)
1: BICKO Output Enable
This setting is invalid in Slave mode (CKM mode 2, 3, and 5 (CONT00: D6-D4)).
D5: LRCKOE LRCK pin Output Setting (Master Mode)
0: LRCKO= “L” (default)
1: LRCKO Output Enable
This setting is invalid in Slave mode (CKM mode2, 3 and 5).
D2: OUT3E
0: SDOUT3= “L” (default)
1: SDOUT3 Output Enable Valid when JX2E bit (CONT01: D7) = “0”
D1: OUT2E
0: SDOUT2= “L” (default)
1: SDOUT2 Output Enable Valid when JX3E bit (CONT05: D6) = “0”
D0: OUT1E
0: SDOUT1= “L” (default)
1: SDOUT1 Output Enable
Write “0” into the “0” registers.
CONT0B: TEST Setting
W
R
Name
D7
CBh 4Bh CONT0B 0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Default
00h
Write “0” into the “0” registers.
014006643-E-00
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[AK7755]
CONT0C: ADC, DAC Volume Transition Time and SDOUT1 Output Settings
W
R
Name
CCh 4Ch CONT0C
D7
D6 D5
DSM 0
D4
D3 D2
ATSPAD ATSPDA 0
D1
D0
Default
SELDO1[2] SELDO1[1] SELDO1[0] 00h
D7: DSM Delta Sigma Module Sampling CLK Setting
0: DSMCLK 256fs (default)
1: DSMCLK 12.288MHz
D5: ATSPAD ADC Volume Transition Time Setting
0: 1/fs (default)
1: 4/fs
D4: ATSPDA DAC Volume Transition Time Setting
0: 1/fs (default)
1: 4/fs
D2, D1, D0: SELDO1[2:0] SDOUT1 Pin Output Select
SELDO1 mode SELDO1[2:0] Output Data
0
000
DSP DOUT1
(default)
1
001
GP0
2
010
SDIN1
3
011
SDOUTAD
4
100
EEST
5
101
SDOUTAD2
6
110
N/A
7
111
N/A
The output format is fixed to MSB 24-bit when selecting SDOUTAD or SDOUTAD2.
Write “0” into the “0” registers.
CONT0D: STO Status Read and EEPROM Download Setting
W
CDh
R
4Dh
Name
D7
CONT0D STO
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
DLS
Default
80h
D7: STO Status Output
0: Internal Error Status
1: Normal Operation (default)
This is a read only register.
D6: 1
Thise bit should be set to “1” during system reset (CRESETN bit (CONT0F:D3) = “0” and
DSPRESETN bit (CONT0F: D2) = “0”).
D0: DLS Start EEPROM Downloading
0: Normal Operation (default)
1: Start EEPROM Downloading
This setting is valid when the I2CSEL pin= “H”. Register settings and DSP programs can be
downloaded from an external EEPROM by setting the EXTEEP pin = “H” or DLS bit = “1”.
However, when selecting memory mat (I2CSEL pin = MATSEL pin = “H”), downloading cannnot be
executed by DLS bit.
Write “0” into the “0” registers.
014006643-E-00
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[AK7755]
CONT0E: ADC, DAC, Lineout Power Management
W
R
Name
D7
D6
D5
CEh 4Eh CONT0E PMADR PMADL PMAD2L
D4
D3
D2
D1
D0
PMLO3 PMLO2 PMLO1 PMDAR PMDAL
Default
00h
D7: PMADR Power Management (MIC-Amp Rch + ADC Rch)
0: Power-down (default)
1: Start Normal Operation after releasing CODEC Reset (CRESETN bit (CONT0F: D3) = “1”).
D6: PMADL Power Management (MIC-Amp Lch + ADC Lch)
0: Power- down (default)
1: Start Normal Operation after releasing CODEC Reset (CRESETN bit = “1”).
D5: PMAD2L Power Management (ADC2 Lch)
0: Power- down (default)
1: Start Normal Operation after releasing CODEC Reset (CRESETN bit = “1”).
D4: PMLO3 Lineout 3 Power Management
0: Power- down (default)
1: Normal Operation
D3: PMLO2 Lineout 2 Power Management
0: Power- down (default)
1: Normal Operation
D2: PMLO1 Lineout 1 Power Management
0: Power- down (default)
1: Normal Operation
D1: PMDAR Power Management (DAC Rch)
0: Power- down (default)
1: Start Normal Operation after releasing CODEC Reset (CRESETN bit = “1”).
D0: PMDAL Power Management (DAC Lch)
0: Power- down (default)
1: Start Normal Operation after releasing CODEC Reset (CRESETN bit = “1”).
014006643-E-00
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[AK7755]
CONT0F: Reset Settings, Lineout and Digital MIC2 Rch Power Managements
W
CFh
R
4Fh
Name
D7 D6 D5
CONT0F 0
0
PML1
D4
LRDETN
D3
CRESETN
D2
D1
D0
Default
DSPRESETN PMAD2R DLRDY 00h
D5: PMLI Line-in Power Management
0: Power-down (default)
1: Normal Operation
D4: LRDETN Slave Mode Automatic System Reset Setting
0: LRCK Detect ON (default)
1: LRCK Detect OFF
When this bit is “0”, if the LRCK is stopped or the LRCK phase is shifted more than 1/4fs, the
AK7755 enters system reset state automatically.
D3: CRESETN CODEC Reset N
0: CODEC Reset (default)
1: CODEC Reset Release
CODEC means the ADC and the DAC.
D2: DSPRESETN DSP Reset N
0: DSP Reset (default)
1: DSP Reset Release
The AK7755 is in system reset state when CRESETN bit = “0” and DSPRESETN bit = “0”.
D1: PMAD2R Power Managements of ADC2 Rch (only when using digital microphone)
0: Power-down (default)
1: The AK7755 enters normal operation after releasing CODEC Reset (CRESETN bit = “1”).
D0: DLRDY DSP Download Ready
0: Normal Operation (default)
1: Program Downloading
DSP programs and coefficient data can be downloaded by setting this bit to “1” during clock reset
(CKRESETN bit = “0”) or when the main clock is stopped. This bit must be set to “0” after finishing
the downloading.
Write “0” into the “0” registers.
014006643-E-00
2014/10
- 44 -
[AK7755]
CONT10: Function Settings
W
R Name
D7
D6
D0h 50h CONT10 WDTEN CRCE
D5
D4
D3
D2 D1 D0
Default
PLLLOCKE SOCFG SELSTO 0
0
CKADJEN 00h
D7: WDTEN WDT (watchdog timer) Setting
0: WDTE Enable (default)
1: WDTE Disable
D6: CRCE CRC (cyclic redundancy check) Setting
0: CRC Disable (default)
1: CRC Enable
D5: PLLLOCKE PLL LOCK Detection
0: PLL LOCK Disable (default)
1: PLL LOCK Enable
D4: SOCFG SO pin Hi-Z Select
0: Hi-Z (default)
1: CMOSL
D3: SELSTO STO/RDY Pin Selecting Status Out
0: STO (default)
1: RDY
D0: CKADJEN Clock Adjustment Enable
0: CKADJ DISABLE (default)
1: CKADJ ENABLE
Write this bit to “1” when setting CONT11 CKADJ[7:0] bits.
Write “0” into the “0” registers.
CONT11: DSPMCLK Availability Ratio Setting
W
R
Name D7
D6
D5
D4
D3
D2
D1
D0
Default
CK
CK
CK
CK
CK
CK
CK
CK
D1h 51h CONT11
00h
ADJ[7]) ADJ[6]) ADJ[5]) ADJ[4]) ADJ[3]) ADJ[2]) ADJ[1]) ADJ[0])
D7-D0: CKADJ [7:0] DSPMCLK Availability Ratio Setting
Availability = (256-CKADJ) / 256
0000_0000: 100% driving (Normal) (default)
0000_0001: 99.6% driving
• • •
1000_0000: 50% driving
• • •
1111_1110: 0.8% driving
1111_1111: 0.4% driving
Set CONT10 CKADJEN bit to “1” when using this register.
DSPMCLK must always be more than 10 times of SCLK.
For example, when SCLK is 2MHz, the setting should be lower than 0hD6 (214) since CKADJ[7:0] <
256 – (2 x 10 x 256) / 122.88 = 214.33.
014006643-E-00
2014/10
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[AK7755]
CONT12: Microphone Gain Setting
W
R
D2h 52h
Name
D7
MGNR
CONT12
[3]
D6
MGNR
[2]
D5
MGNR
[1]
D4
MGNR
[0]
D3
MGNL
[3]
D2
MGNL
[2]
D1
MGNL
[1]
D0
MGNL
[0]
Default
00h
D7, D6, D5, D4: MGNR[3:0] Microphone Input Rch Gain Setting
MGNR mode
MGNR[3:0]
Microphone Input Rch
Gain
(default)
0
0000
0dB
1
0001
2dB
2
0010
4dB
3
0011
6dB
4
0100
8dB
5
0101
10dB
6
0110
12dB
7
0111
14dB
8
1000
16dB
9
1001
18dB
A
1010
21dB
B
1011
24dB
C
1100
27dB
D
1101
30dB
E
1110
33dB
F
1111
36dB
D3, D2, D1, D0: MGNL[3:0] Microphone Input Lch Gain
MGNL mode
MGNL[3:0]
Microphone Input Lch
Gain
0dB
0
0000
1
0001
2dB
2
0010
4dB
3
0011
6dB
4
0100
8dB
5
0101
10dB
6
0110
12dB
7
0111
14dB
8
1000
16dB
9
1001
18dB
A
1010
21dB
B
1011
24dB
C
1100
27dB
D
1101
30dB
E
1110
33dB
F
1111
36dB
014006643-E-00
(default)
2014/10
- 46 -
[AK7755]
CONT13: Line-in/Lineout 3 Volume Setting
W
R
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
LOVOL3 LOVOL3 LOVOL3 LOVOL3
D3h 53h CONT13 LIGN[3] LIGN[2] LIGN[1] LIGN[0]
00h
[3]
[2]
[1]
[0]
・D7, D6, D5, D4: LIGN[3:0] Line-in Volume Setting
LIGN mode
LIGN[3:0]
Line-in Volume Setting
0
0000
0dB
1
0001
-3dB
2
0010
-6dB
3
0011
-9dB
4
0100
-12dB
5
0101
-15dB
6
0110
-18dB
7
0111
-21dB
8
1000
N/A
9
1001
+3dB
A
1010
+6dB
B
1011
+9dB
C
1100
+12dB
D
1101
+15dB
E
1110
+18dB
F
1111
+21dB
・D3, D2, D1, D0: LOVOL3[3:0] Line-out 3 Volume Setting
LOVOL3 mode LOVOL3[3:0]
Line-out 3 Volume Setting
0
0000
Mute
1
0001
-28dB
2
0010
-26dB
3
0011
-24dB
4
0100
-22dB
5
0101
-20dB
6
0110
-18dB
7
0111
-16dB
8
1000
-14dB
9
1001
-12dB
A
1010
-10dB
B
1011
-8dB
C
1100
-6dB
D
1101
-4dB
E
1110
-2dB
F
1111
0dB
014006643-E-00
(default)
(default)
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[AK7755]
CONT14: Line-out 1, Line-out 2 Volume Setting
W R Name D7
D6
D5
D4
D3
D2
D1
D0
Default
LOVOL2 LOVOL2 LOVOL2 LOVOL2 LOVOL1 LOVOL1 LOVOL1 LOVOL1
D4h 54h CONT14
00h
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
D7, D6, D5, D4: LOVOL2[3:0] Line-out 2 Volume Setting
LOVOL2 mode
LOVOL2[3:0]
Lineout 2 Volume Setting
0
0h
Mute
1
1h
-28dB
2
2h
-26dB
3
3h
-24dB
4
4h
-22dB
5
5h
-20dB
6
6h
-18dB
7
7h
-16dB
8
8h
-14dB
9
9h
-12dB
A
Ah
-10dB
B
Bh
-8dB
C
Ch
-6dB
D
Dh
-4dB
E
Eh
-2dB
F
Fh
0dB
(default)
D3, D2, D1, D0: LOVOL1[3:0] Line-out 1 Volume Setting
LOVOL1 mode
LOVOL1[3:0]
Lineout 1 Volume Setting
0
0h
Mute
1
1h
-28dB
2
2h
-26dB
3
3h
-24dB
4
4h
-22dB
5
5h
-20dB
6
6h
-18dB
7
7h
-16dB
8
8h
-14dB
9
9h
-12dB
A
Ah
-10dB
B
Bh
-8dB
C
Ch
-6dB
D
Dh
-4dB
E
Eh
-2dB
F
Fh
0dB
(default)
CONT15-16-17: ADC, ADC2 Lch Digital Volume Setting
W
R
Name
D7
D6
D5
VOL
VOL
VOL
D5h 55h CONT15
ADL[7] ADL[6] ADL[5]
VOL
VOL
VOL
D6h 56h CONT16
ADR[7] ADR[6] ADR[5]
VOL
VOL
VOL
D7h 57h CONT17
AD2L[7] AD2L[6] AD2L[5]
Refer to “2-3. ADC, ADC2 digital volume”.
D4
VOL
ADL[4]
VOL
ADR[4]
VOL
AD2L[4]
014006643-E-00
D3
VOL
ADL[3]
VOL
ADR[3]
VOL
AD2L[3]
D2
VOL
ADL[2]
VOL
ADR[2]
VOL
AD2L[2]
D1
VOL
ADL[1]
VOL
ADR[1]
VOL
AD2L[1]
D0
VOL
ADL[0]
VOL
ADR[0]
VOL
AD2L[0]
Default
30h
30h
30h
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[AK7755]
CONT18-19: DAC Digital Volume Setting
W
R
D8h
58h
D9h
59h
Name
D7
VOL
CONT18
DAL[7]
VOL
CONT19
DAR[7]
D6
VOL
DAL[6]
VOL
DAR[6]
D5
VOL
DAL[5]
VOL
DAR[5]
D4
VOL
DAL[4]
VOL
DAR[4]
D3
VOL
DAL[3]
VOL
DAR[3]
D2
VOL
DAL[2]
VOL
DAR[2]
D1
VOL
DAL[1]
VOL
DAR[1]
D0
Default
VOL
18h
DAL[0]
VOL
18h
DAR[0]
Refer to “2. DAC digital volume”.
CONT1A: ADC/DAC MUTE, ADRC and Zero-cross Settings
W
R
DAh 5Ah
Name
D7
AD
CONT1A
MUTE
D6
AD2
MUTE
D5
DA
MUTE
D4
1
D3
D2
D1
D0
Default
ADRCRE ADRCLE MICRZCE MICLZCE 00h
D7: ADMUTE ADC MUTE Setting
0: Stereo ADC MUTE Release (default)
1: Stereo ADC MUTE
D6: ADMMUTE ADC2 MUTE Setting
0: ADC2 MUTE Release (default)
1: ADC2 MUTE
D5: DAMUTE DAC MUTE Setting
0: DAC MUTE Release (default)
1: DAC MUTE
D4: 1
Thise bit should be set to “1” during system reset (CRESETN bit (CONT0F: D3) = “0” and
DSPRESETN bit (CONT0F: D2) = “0”).
D3: ADRCRE Analog Dynamic Range Controller Rch Enable Setting
0: ADRC Rch DISABLE (default)
1: ADRC Rch ENABLE
D2: ADRCLE Analog Dynamic Range Controller Lch Enable Setting
0: ADRC Lch DISABLE (default)
1: ADRC Lch ENABLE
D1: MICRZCE MICGAIN Rch Zero-corss Enable
0: Rch Zero-cross Detection ON (default)
1: Rch Zero-cross Detection OFF
D0: MICLZCE MICGAIN Lch Zero-cross Enable
0: Lch Zero-cross Detection ON (default)
1: Lch Zero-cross Detection OFF
Write “0” into the “0” registers.
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[AK7755]
CONT1B: Microphone Gain Read Register when using ADRC
W R
-
Name
5Bh CONT1B
D7
D6
D5
D4
D3
D2
D1
D0
Default
AMGNR AMGNR AMGNR AMGNR AMGNL AMGNL AMGNL AMGNL
00h
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
This register is a read only register.
AMGNR[3:0] bits will be valid when ADRCRE bit (CONT1A: D3) = “1”, and AMGNL[3:0] will be valid
when ADRCLE bit (CONT1A: D2) = “1”. The microphone gain value set by DSP can be readout.
CONT1C: TEST Setting
W
R
Name
D7
D6
DCh 5Ch CONT1C 0
0
Write “0” into the “0” registers.
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Default
00h
CONT1D: ADC2 Rch Digital Volume Setting
W
R
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
VOL
VOL
VOL
VOL
VOL
VOL
VOL
VOL
DDh 5Dh CONT1D
30h
AD2R[7] AD2R[6] AD2R[5] AD2R[4] AD2R[3] AD2R[2] AD2R[1] AD2R[0]
Refer to “2-3. ADC2 Digital Volume”.
CONT1E: Digital Microphone Interface Setting
W R Name
D7
DDh 5Dh CONT1D DMIC1
D6
D5
D4
D3
D2
D1 D0 Default
DMCLKP1 DMCLKE1 DMIC2 DMCLKP2 DMCLKE2 0
0 00h
D7: DMIC1 Digital Microphone 1 Select
0: Not Using DMIC1 (default)
1: Using DMIC1
When DMIC1 bit = “1” or DMIC2 bit = “1”, pin number 31~ 34 become digital microphone interfaces,
and analog inputs are not available.
D6: DMCLKP1 Digital Microphone 1 Channel Setting
DMCLKP1
DMCLK1 pin = “H”
DMCLK1 pin = “L”
0
Rch
Lch
1
Lch
Rch
(default)
D5: DMCLKE1 Digital Microphone 1 Clock Setting
0: DMCLK1 pin = “L” (default)
1: DMCLK1 64fs (Output Enable)
・D4: DMIC2 Digital Microphone 2 Select
0: Not Using DMIC2 (default)
1: Using DMIC2
When DMIC1 bit = “1” or DMIC2 bit = “1”, pin number 31 ~ 34 become digital microphone
interfaces, and analog inputs are not available.
・D3: DMCLKP2 Digital Microphone 2 Channel Setting
DMCLKP2
DMCLK2 pin = “H”
DMCLK2 pin = “L”
0
Rch
Lch
1
Lch
Rch
(default)
・D2: DMCLKE2 Digital Microphone 2 Clock Setting
0: DMCLK2 pin = “L” (default)
1: DMCLK1 64fs (Output Enable)
014006643-E-00
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[AK7755]
Do not write data into CONT21 - CONT25.
CONT26
W R
Name
D7 D6 D5 D4 D3 D2 D1 D0 Default
E6 66h CONT26 0
0
0
0
0
0
0
1
00h
D0: 1
Thise bit should be set to “1” during system reset (CRESETN bit (CONT0F: D3) = “0” and
DSPRESETN bit (CONT0F: D2) = “0”).
Write “0” into the “0” registers.
Do not write data into CONT27 - CONT29.
CONT2A
W R
Name
D7 D6 D5 D4 D3 D2 D1 D0 Default
EA 6Ah CONT2A 1
0
0
0
0
0
0
0
00h
D7: 1
Thise bit should be set to “1” during system reset (CRESETN bit (CONT0F: D3) = “0” and
DSPRESETN bit (CONT0F: D2) = “0”).
Write “0” into the “0” registers.
Do not write data into CONT2B – CONT2F.
014006643-E-00
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[AK7755]
■ Power-up Sequence
1. When not downloading settings and programs from EEPROM
The AK7755 should be powered up when the PDN pin = “L”. AVDD and TVDD must be powered up first
before DVDD when DVDD is supplied externally (LDOE pin = “L”). In this case, the power-up sequence
between AVDD and TVDD is not critical. Control register settings are initialized by the PDN pin = “L”.
Set the PDN pin to “H” to start the power supply circuits for REF (analog reference voltage source)
generator and digital circuits (only when LDOE pin = “H”) after all power supplies are fed. Control register
access must be made after 1ms from the PDN pin = “H”. Set AINE bit (CONT00: D3) to “1” fist when
using the IN1/INP1, IN2/INN1, IN3/INP2 and IN4/INN2 pins as analog inputs.
The PLL starts operation by a clock reset release (CKRESETN bit (CONT01: D0) = “0” → “1”) and
generates the internal master clock after setting control registers. Therefore, necessary system clock must be
input and control register settings for CONT00 ~ CONT01 are must be finished before releasing the clock
reset.
Interfacing with the AK7755 except control register settings should be made when PLL oscillation is
stabilized after clock reset release (take a 10ms interval or confirm “H” level output of PLLLOCK signal
from the STO/RDY pin) (Figure 24). However, DSP program and coefficient data can be written even
when the system clock is stopped. DSP programs and coefficient data can be written in 1ms by setting
DLRDY bit =“0” → “1” (CONT0F, D0). DLRDY bit (CONT0F: D0) must be set to “0” after the download
(Figure 25).
When using a crystal oscillator in master mode, set the CKM[2:0] bits (CONT00: D6-D4) = 0h or 1h, and
release the clock reset after crystal oscillation is stabilized. The stabilizing time of crystal oscillation is
dependent on the crystal and external circuits.
The system clock must not be stopped except during the clock reset and power-down mode.
TVDD,AVDD
DVDD
PDN (pin)
CONT Reg. Setting
SI(SPI),SDA(I2C)
DSP Program
CKRESETN bit (Reg.)
DSPRESETN bit(Reg.)
CRESETN bit(Reg.)
XTI,BICK (pin)
Clock Stabilizataion
Internal PLLCLK
(Internal Master Clock)
600ns(min)
Power OFF
1ms(min)
Before PLL stable oscillation
access is not permitted
(10ms)
Command code and DSP
Program download
（No time limitation）
Figure 24. Power-up Sequence 1 (When not downloading from EEPROM)
(With External Power Supply (LDOE pin = “L”), No downloading from EEPROM)
014006643-E-00
2014/10
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[AK7755]
TVDD, AVDD
DVDD
PDN(Pin)
SI(spi), SDA(i2c)
DLRDY=1
DSP Program
DLRDY=0
CONT Reg.Setting
CKRESETN bit (Reg.)
DSPRESETN bit(Reg)
CRESETN bit(Reg)
XTI,BICK(Pin)
Clock Stabilization
Internal PLLCLK
(Internal Master Clock)
Power OFF
600ns(min) 1ms(min)
Before PLL stable oscillation
access is not permitted
(10ms)
1ms(min)
Figure 25. Power-up Sequence 2
(With External Power Supply (LDOE pin = “L”), DLRDY Setting, No downloading from EEPROM)
2. When downloading settings and programs from EEPROM
When downloading programs from an EEPROM, I2C interface (I2CSEL pin = “H”) and a 12.288MHz
clock input to the XTI pin are necessary, or a 12.288MHz crystal oscillator must be connected to the XTI
and XTO pins. In this case, only CKM mode 0 and 2 (CONT00: D6-D4) are available. The AK7755 should
be powered up when the PDN pin = “L”. AVDD and TVDD must be powered up first before DVDD when
DVDD is supplied externally (LDOE pin = “L”). In this case, the power-up sequence between AVDD and
TVDD is not critical. Set the PDN pin to “H” to start the power supply circuits for REF (analog reference
voltage source) generator and internal digital circuit (only when the LDOE pin = “H”) after all power
supplies are fed. There are three ways to start downloading control register settings, DSP programs and
Coefficient RAM: by PDN pin (1) (Figure 26), by EXTEEP pin (2) (Figure 26) and by DLS bit (3) (Figure
27).
014006643-E-00
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[AK7755]
TVDD, AVDD
DVDD
PDN(pin)
(1)
XTI(pin)
Clock Stabilization(12.288MHz)
I2CSEL(pin)
EXTEEP(pin)
SDA(pin)
(2)
CONT Reg. Setting, DSP Program
(EEPROM→AK7755)
EEST(pin)
Success
STO(pin)
Error
CKRESETN bit (Reg.)
DSPRESETN bit(Reg.)
CRESETN bit(Reg.)
Power OFF
600ns(min) 1ms(min)
Figure 26. Power-up Sequence 3
(With External Power Supply (LDOE pin = “L”), Downloading from EEPROM (1)(2))
(1) Start Downloading by PDN pin
Power ON (AVDD, TVDD), I2CSEL pin=“H”, EXTEEP pin=“H”→ (DVDD→), PDN pin=“L”→“H”
(2) Start Downloading EXTEEP pin (Dotted Line)
Power ON (AVDD, TVDD), I2CSEL pin = “H” → (DVDD→), PDN pin = “L” → “H”
→ EXTEEP pin = “L” → “H”
TVDD, AVDD
DVDD
PDN(pin)
(1)
XTI(pin)
Clock Stabilization(12.288MHz)
I2CSEL(pin)
DLS bit
(3)
(uP→AK7755)
SDA(pin)
DLS=1
(EEPROM→AK7755)
CONT Reg. Setting, DSP Program
EEST(pin)
Success
STO(pin)
Error
CKRESETN bit (Reg.)
DSPRESETN bit(Reg.)
CRESETN bit(Reg.)
Power OFF
600ns(min) 1ms(min)
Figure 27. Power-up Sequence 4
(With External Power Supply (LDOE pin = “L”), Downloading from EEPROM (3))
(3) Start Downloading DLS bit
Power ON (AVDD, TVDD), I2CSEL pin=“H”→(DVDD→), PDN pin=“L”→“H” →DLS bit = “0”→“1”
014006643-E-00
2014/10
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[AK7755]
■ LDO (Internal Circuit Drive Regulator)
The AK7755 has a regulator for driving internal digital circuits (LDO). When using the LDO, the LDOE
pin must be fixed to “H” and connect a 1μF (±30%) capacitor between the AVDRV pin and the VSS pin.
The LDO starts operation by releasing power-down mode, and control register write/read can be made 1ms
after the power-down release.
The AK7755 has an overcurrent protection circuit to avoid abnormal heat of the device that is caused by a
short of the AVDRV pin to VSS and etc., and an overvoltage protection circuit to protect from exceeded
voltage when the voltage to the AVDRV pin gets too high. When these protection circuits perform, internal
circuits are powered down and the STO pin outputs “L”. The internal circuit will not return to a normal
operation until being reset by the PDN pin after removing the problems.
TVDD,AVDD
LDOE (pin)
AVDRV (pin)
PDN (pin)
STO (pin)
CONT Reg. Setting
SI(SPI),SDA(I2C)
DSP Program
CKRESETN bit (Reg.)
DSPRESETN bit(Reg.)
CRESETN bit(Reg.)
XTI,BICK (pin)
Clock Stabilization
Internal PLLCLK
(Internal Master Clock)
Power OFF
600ns(min)
1ms(min)
Before PLL stable oscillation
access is not permitted
(10ms)
Command code and DSP
Program download
（No time limitation）
Figure 28. Power-up Sequence 5
(With LDO (LDOE pin = “H”), No downloading from EEPROM)
■ Power-down Sequence
The AK7755 should be powered down when the PDN pin = “L”. Stop external clocks during this
power-down state and then OFF the power supplies. Do not input external clocks when the power supplies
are off (a current will flow through protection diodes). AVDD and TVDD must be powered down after
DVDD when DVDD is supplied externally (LDOE pin = “L”). In this case, the power-down sequence
between AVDD and TVDD is not critical.
TVDD,AVDD
DVDD
PDN(pin)
Power OFF
Figure 29. Power-down Sequence
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[AK7755]
■ Power-down and Reset
1. Power-down, Reset and Power Management of the AK7755
The AK7755 has four types of power-down and reset functions that are power-down (PDN pin), Clock
reset (CLKRESETN bit (CONT01:D0)), CODEC reset (CRESETN bit(CONT0F:D3)) and DSP reset
(DSPRESETN bit(CONT0F:D2)). Each block can be powered-down by power management registers.
2. Power-down
The AK7755 is powered down by setting the PDN pin = “L”. The PDN pin must be set to “L” when
power up the AK7755. The statuses of output pins in power-down mode are shown below.
LDOE pin = “L” (External 1.2V supply mode)
No
Pin Name
I/O Power-down Mode Status No
1
VCOM
O
L
17
6
STO/RDY
O
H
18
7
LRCK
I/O
L
26
8
BICK
I/O
L
27
9
CLKO
O
L
28
10
XTO
O
H
31
11
XTI
I
H
32
14 JX2/SDOUT3/JX2/MAT1 I/O
L
33
15 SDOUT2/JX3/MAT1 I/O
L
34
16
SDOUT1
O
L
Note 44. [I/O] indicates Input / Output attribute of each pin.
LDOE pin = “H” (LDO mode)
No
Pin Name
I/O Power-down Mode Status
1
VCOM
O
L
6
STO/RDY
O
L
7
LRCK
I/O
L
8
BICK
I/O
L
9
CLKO
O
L
10
XTO
O
H
11
XTI
I
H
14 JX2/SDOUT3/JX2/MAT1 I/O
L
SDOUT2/JX3/MAT1
15
I/O
L
16
SDOUT1
O
L
No
17
18
24
26
27
28
31
32
33
34
Pin Name
SO/SDA
SCLK/SCL
OUT3
OUT2
OUT1
IN4/INN2/DMCLK2
IN3/INP2/DMDAT2
IN2/INN1/DMCLK1
IN1/INP1/DMDAT1
Pin Name
SO/SDA
SCLK/SCL
AVDRV
OUT3
OUT2
OUT1
IN4/INN2/DMCLK2
IN3/INP2/DMDAT2
IN2/INN1/DMCLK1
IN1/INP1/DMDAT1
I/O Power-down Mode Status
I/O
Hi-Z
I/O
Hi-Z
O
Hi-Z
O
Hi-Z
O
Hi-Z
I/O
Hi-Z
I
Hi-Z
I/O
Hi-Z
I
Hi-Z
I/O Power-down Mode Status
I/O
Hi-Z
I/O
Hi-Z
O
L
O
Hi-Z
O
Hi-Z
O
Hi-Z
I/O
Hi-Z
I
Hi-Z
I/O
Hi-Z
I
Hi-Z
3. Power-down Release
3-1. LDOE = “L” (External 1.2V supply mode)
DVDD, TVDD and AVDD should be supplied when the PDN pin = “L”. By bringing the PDN pin “H”
600ns (min) after all power supplies are fed (DVDD, TVDD and AVDD), REF voltage circuit (Analog
reference voltage) starts operation. Control register write / read should be made 1ms after bringing the
PDN pin = “H” (Figure 24). AVDD and TVDD must be powered up first before DVDD. In this case,
the power-up sequence between AVDD and TVDD is not critical.
3-2. LDOE = “H” (LDO mode)
TVDD and AVDD should be supplied when the PDN pin = “L”. By bringing the PDN pin “H” 600ns
(min) after TVDD and AVDD are fed, the power supply circuits for REF generator and internal digital
circuit start operation. Control register write / read should be made 1ms after bringing the PDN pin =
“H” (Figure 28).
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[AK7755]
4. Clock Reset
Clock reset is defined as when CKRESERN bit (CONT01: D0) = “0” after power-down release (PDN
pin = “H”). The AK7755 is in the clock reset state after releasing power-down. At this time, all internal
blocks of the AK7755, except the REF circuit and the power supply circuit for digital block, are in
power-down mode. Even the PLL for internal master clock generation is not in operation.
Control register write/read should be made 1ms (min.) after power-down release. Clock generating
control registers (CONT00 ~ CONT01) must be set during clock reset. AINE bit (CONT00: D3) should
be set to “1” first when using the IN1/INP1, IN2/INN1, IN3/INP2 and IN4/INN2 pins as analog inputs.
DSP program and coefficient RAM data writing to the DSP become available in 1ms by setting
DLRDY bit (CONT0F: D0) = “0” → “1” during clock reset (CKRESETN bit = “0”). DLRDY bit must
be set to “0” when finishing downloading. Necessary system clock (XTI@CKM mode0-2 or
BICK@CKM mode 3, 5(CONT00: D6-D4)) must be input before releasing the clock reset (Figure 16).
The PLL for internal master clock starts operation and generating master clock when the clock reset
state is released (CKRESETN bit = “1”). Do not send DSP programs, coefficient data or a command
code for system reset release from a microcontroller to the AK7755 until the PLL oscillation is
stabilized (for 10ms or during Low output period of the PLLLOCK signal from the STO pin).
System clocks must be changed during a clock reset or in power-down mode (PDN pin = “L”). The
AK7755 enters clock reset state by setting CKRESETN bit to “0” after system reset. The PLL and the
internal clock are stopped by this clock reset and the clock change can be done safely. Change register
settings and system clock frequencies during the clock reset. After a system clock is stabilized, the PLL
starts operation by setting CKRESETN bit to “1”.
CKM mode3
CKM mode0
XTI
BICK
CSN
SCLK (Simplified)
SI
0xCF 0x00
0xC1 0x00
0xC0 0x3x
0xC1 0x01
0xCF 0x0C
CRESETN / DSPRESETN
CKRESETN
Input Clock Changeable Period
PLL Stable
Oscillation
Command Code &
DSP Program Transmitting Period
Figure 30. Clock Reset Sequence (e.g. CKM mode0 → CKM mode 3)
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[AK7755]
5. System Reset
System reset is defined as when CRESETN bit (CONT0F: D3) = “0” and DSPRESETN bit (CONT0F:
D2) = “0” after clock reset is released (CKRESETN bit (CONT01: D0) = “1”). PRAM and CRAM
downloading should be executed in this state. PRAM and CRAM accessing of the AK7755 should be
made when PLL oscillation is stabilized after clock reset release (take a 10ms interval or confirm “H”
level output of PLLLOCK signal from the STO pin).
System reset is released when either CODEC reset (CRESETN bit) or DSP reset (DSPRESETN bit) is
released (“0” → “1”) after DSP programs and coefficient data are transmitted. Then the AK7755 starts
generating necessary clocks for ADC, DAC and DSP operations. A system reset image is shown below.
CRESETN bit
DSPRESETN bit
SRESETN
Figure 31. System Reset Structure
In slave mode, the AK7755 starts operation in synchronization of an LRCK rising edge (falling edge in
I2S mode) when system reset is released. If the LRCK is stopped or the LRCK phase is shifted more
than 1/4fs, the AK7755 becomes the system reset state automatically. In this case, the system reset state
is released if the LRCK is input again.
■ RAM Clear
The AK7755 has a RAM clear function. After system reset release (during RUN), data RAM and delay
RAM are cleared by “0” (RAM clear). The internal PLL must have a stable oscillation before system
reset release. The required time to clear RAM is 400µs.
In the RAM clear sequence, it is possible to send commands to the DSP. (DSP is stopped during RAM
clear sequence. The sent command is accepted automatically after this sequence is completed.)
PDN (pin)
DSPRESETN bit
RAM Clear
DSP Start
RAM Clear Period
DSP Program
Operation Start
Figure 32. RAM Clear Sequence
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■ Serial Data Interface
Serial audio data pins; the SDIN1, SDIN2, SDOUT1, SDOUT2 and SDOUT3 pins are interfaced with
an external system by LRCK and BICK. Control register settings are needed to use these interfaces
(Refer to ■ Block Diagram (Figure 1) and Control register setting).
The data format is 2's compliment MSB first. I/O format supports MSB justified, LSB justified, I2S
compatible and PCM format. (In I2S compatible/PCM mode, all audio data input and output pins are in
I2S compatible/PCM format, respectively.)
The input (SDIN1 and SDIN2) format is 24-bit MSB justified at default. 24-bit/20-bit/16-bit LSB
justified, I2S and PCM formats are also selectable by control register DIF[1:0] bits. The output
(SDOUT1, ADOUT2 and SDOUT3) format is 24-bit MSB justified at default. 24-bit/20-bit/16-bit LSB
justified, I2S and PCM formats are selectable by setting DOF[1:0] bits. The SDOUT1 also supports 8-bit
MSB justified μ-Law and 8-bit MSB justifid A-Law formats. The output data of the ADC (SDOUTAD
and SDOUTAD2) is fixed to 24-bit MSB justified.
mode
LRIF[1:0]
0
1
2
3
4
5
6
7
8
000h
000h
000h
000h
0h
0h
011h
102h
113h
DIFDIF2, DIFDA[1:0]
or
DOF2, 3, 4[1:0]
000h
011h
102h
113h
N/A
N/A
000h
000h
000h
DIF1[2:0]
or
DOF1[2:0]
0h
1h
2h
3h
4h
5h
0h
0h
0h
BITFS[1:0]
0h
0h/1h
0h/1h
0h/1h/2h
0h
0h
0h
0h/3h
0h/3h
Format
MSB 24-bit 64fs
LSB 24-bit 64fs/48fs
LSB 20-bit 64fs/48fs
LSB 16-bit 64fs/48fs/32fs
MSB 8-bit μ-Law
MSB 8-bit A-Law
I2S Compatible
PCM Short Frame 64fs/256fs
PCM Long Frame 64fs/256fs
Serial Data Format Examples
1. MSB justified (mode 0)
Left ch
LRCK
Right ch
BICK
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
DIF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
SDOUT1, 2, 3
DOF Mode 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
Figure 33. MSB Justified BICK 64fs
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[AK7755]
2. LSB justified (mode1, 2, 3)
LRCK
Left ch
Right ch
BICK
31 30
23 22 21 20 19 18 17 16 15 14
1 0 31 30
23 22 21 20 19 18 17 16 15 14
1 0
SDIN1, 2
DIF Mode 1
Don’t care M 22 21 20 19 18 17 16 15 14
1 L Don’t care M 22 21 20 19 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 2
Don’t care
M 18 17 16 15 14
1 L Don’t care
M 18 17 16 15 14
1 L
SDIN1, 2
DIF Mode 3
Don’t care
M 14
1 L Don’t care
M 14
1 L
M: MSB, L: LSB
SDOUT1, 2, 3
DOF Mode 1
MSB
22 21 20 19 18 17 16 15 14
1 L
MSB
22 21 20 19 18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 2
MSB
18 17 16 15 14
1 L
MSB
18 17 16 15 14
1 L
SDOUT1, 2, 3
DOF Mode 3
MSB
14
1 L
MSB
14
1 L
Figure 34. LSB Justified BICK 64fs
LRCK
Left ch
Right ch
BICK
23 22 21 20 19 18 17 16 15 14 13 12 11 10
1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SDIN1,2
DIF mode1
M 22 21 20 19 18 17 16 15 14 13 12 11 10
1 L M 22 21 20 19 18 17 16 15 14 13 12 11 10
1 L
SDIN1,2
DIF mode2
Don’t care M 18 17 16 15 14 13 12 11 10
1 L Don’t care M 18 17 16 15 14 13 12 11 10
1 L
SDIN1,2
DIF mode3
Don’t care
1 L Don’t care
1 L
M 14 13 12 11 10
M 14 13 12 11 10
1 0
M:MSB,L:LSB
SDOUT1,2,3
DOF mode1
M 22 21 20 19 18 17 16 15 14 13 12 11 10
1 L M 22 21 20 19 18 17 16 15 14 13 12 11 10
1 L
SDOUT1,2,3
DOF mode2
MSB
18 17 16 15 14 13 12 11 10
1 L MSB
18 17 16 15 14 13 12 11 10
1 L
SDOUT1,2,3
DOF mode3
MSB
14 13 12 11 10
1 L MSB
14 13 12 11 10
1 L
Figure 35. LSB Justified BICK 48fs
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[AK7755]
LRCK
Left ch
Right ch
BICK
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIN1,2
DIF mode3
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
SDOUT1,2,3
DOF mode3
M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L
Figure 36. LSB Justified BICK 32fs
3. MSB 8-bit μ-Law、MSB 8-bit A-Law (mode 4,5)
LRCK
Left ch
Right ch
BICK
31 30 29 28 27 26 25 24
7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
7 6 5 4 3 2 1 0
SDIN1
DIF mode4/5
M 6 5 4 3 2 1 L
M 6 5 4 3 2 1 L
M:MSB,L:LSB
SDOUT1
DOF mode4/5
M 6 5 4 3 2 1 L
M 6 5 4 3 2 1 L
M:MSB,L:LSB
SDIN2
DIF mode0
M 22 21 20 19 18 17 16
1 L
M 22 21 20 19 18 17 16
1 L M:MSB,L:LSB
SDOUT2,3
DOF mode0
M 22 21 20 19 18 17 16
1 L
M 22 21 20 19 18 17 16
1 L M:MSB,L:LSB
Figure 37. MSB Justified 8-bit μ-Law, 8-bit A-Law BICK 64fs
4. I²S (mode6)
LRCK
Left ch
Right ch
BICK
31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
M: MSB, L: LSB
SDIN1, 2
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
SDOUT1, 2, 3
M 22 21 20
3 2 1 L
M 22 21 20
3 2 1 L
M: MSB, L: LSB
Figure 38. I²S BICK 64fs
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[AK7755]
5. PCM Short Frame (mode7)
LRCK
tBCLK
SF
BICK
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
10 9 8 7 6 5 4 3 2 1 0
SDIN1, 2
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
SDOUT1, 2, 3
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
M: MSB, L: LSB
Left ch
Right ch
Figure 39. 64fs PCM Short Frame
LRCK
tBCLK
SF
BICK
255 254 253 252 251
234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219
SDIN1,2
M 22 21 20 19
2 1 L
SDOUT1,2,3
M 22 21 20 19
2 1 L
M:MSB,L:LSB
Left ch
202 201 200 199 198
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
3 2 1 0
Right ch
tBCLK × 32
tBCLK × 256
Figure 40. PCM Short Frame 256fs
6. PCM Long Frame (mode8)
tBCLK ≤ t ≤ ts-tBCLK
LRCK
LF
BICK
SDIN1, 2
SDOUT1, 2, 3
63 62 61 60 59
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
tBCLK
M: MSB, L: LSB
10 9 8 7 6 5 4 3 2 1 0
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Left ch
Right ch
tBCLK × 32
tBCLK × 32
Figure 41. 64fs PCM Long Frame
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[AK7755]
LRCK
LF
BICK
255 254 253 252 251
SDIN1, 2
SDOUT1, 2, 3
234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
tBCLK
M:MSB,L:LSB
202 201 200 199 198
M 22 21 20 19
2 1 L
M 22 21 20 19
2 1 L
Left ch
4 3 2 1 0
Right ch
tBCLK × 32
tBCLK × 256
Figure 42. PCM Long Frame 256fs
7. TDM Mode
TDM interface formats shown below are available by setting TDM256 bit = “1”. BITFS[1:0] bits should
be set to 3h since BICK is fixed to 256fs.
Mode
LRIF[1:0]
TDMMODE[1:0]
0
1
2
3
4
5
6
7
8
9
10
11
0h
0h
0h
1h
1h
1h
2h
2h
2h
3h
3h
3h
0h
1h
2h
0h
1h
2h
0h
1h
2h
0h
1h
2h
Format
MSB 24-bit
MSB 24-bit
MSB 24-bit
I2S Compatible
I2S Compatible
I2S Compatible
PCM Short Frame
PCM Short Frame
PCM Short Frame
PCM Long Frame
PCM Long Frame
PCM Long Frame
014006643-E-00
Note
SLOT7 and 8 Inputs Not Available
SLOT5, 6, 7 and 8 Inputs Not Available
SLOT7 and 8 Inputs Not Available
SLOT5, 6, 7 and 8 Inputs Not Available
SLOT7 and 8 Inputs Not Available
SLOT5, 6, 7 and 8 Inputs Not Available
SLOT7 and 8 Inputs Not Available
SLOT5, 6, 7 and 8 Inputs Not Available
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[AK7755]
256BICK
LRCK(master)
LRCK(slave)
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
BICK(256fs)
SDOUT1
23 22
0
23 22
DOUT1L
SDIN1(TDM mode0)
23 22
23 22
0
0
23 22
23 22
23 22
0
0
23 22
23 22
23 22
0
0
0
23 22
0
23 22
DOUT2R
23 22
23 22
0
23 22
0
23 22
0
23 22
23 22
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
23 22
23 22
0
23 22
DIN4R
23 22
0
23 22
SDOUTAD
Rch
SDOUTAD
Lch
0
23 22
0
23 22
SDOUTAD
Rch
SDOUTAD
Lch
SDOUTAD2
Rch
0
DOUT4R
DIN4L
DIN3R
SDOUTAD2
Lch
0
DOUT4L
DIN3R
DIN3L
0
0
DOUT3R
0
23 22
DIN2R
DIN2L
23 22
DIN3L
DIN2R
0
0
DOUT3L
DIN2R
DIN2L
DIN1R
DIN1L
23 22
DIN2L
DIN1R
0
0
DOUT2L
DIN1R
DIN1L
SDIN1(TDM mode2)
23 22
DOUT1R
DIN1L
SDIN1(TDM mode1)
0
(don’t care)
SDIN2
Figure 43. TDM mode MSB Justified 24-bit (Internal signals are indicated by dotted lines)
256BICK
LRCK(master)
LRCK(slave)
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
BICK(256fs)
SDOUT1
23
0
DOUT1L
SDIN1(TDM mode3)
SDIN1(TDM mode4)
SDIN1(TDM mode5)
23
0
0
DOUT1R
23
0
23
0
DOUT2L
23
0
23
0
DOUT2R
23
0
23
0
DOUT3L
23
0
23
0
DOUT3R
23
0
DIN1L
DIN1R
DIN2L
DIN2R
DIN3L
DIN3R
23
23
23
23
23
23
0
0
0
0
0
0
DIN1L
DIN1R
DIN2L
DIN2R
DIN3L
DIN3R
23
23
23
23
23
23
0
DIN1L
SDIN2
23
0
DIN1R
0
DIN2L
0
DIN2R
0
SDOUTAD2
Lch
0
SDOUTAD2
Rch
23
0
DOUT4L
23
0
DIN4L
23
0
SDOUTAD
Lch
23
0
SDOUTAD
Lch
23
0
23
DOUT4R
23
0
23
DIN4R
23
0
23
SDOUTAD
Rch
23
0
23
SDOUTAD
Rch
(don’t care)
Figure 44. TDM mode I2S Compatible (Internal signals are indicated by dotted lines)
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[AK7755]
256BICK
LRCK
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
BICK(256fs)
SDOUT1
23
0
DOUT1L
SDIN1(TDM mode6)
SDIN1(TDM mode7)
SDIN1(TDM mode8)
23
0
0
DOUT1R
23
0
23
0
DOUT2L
23
0
23
0
23
DOUT2R
23
0
DOUT3L
0
23
0
23
0
DOUT3R
23
0
DIN1L
DIN1R
DIN2L
DIN2R
DIN3L
DIN3R
23
23
23
23
23
23
0
0
0
0
0
0
DIN1L
DIN1R
DIN2L
DIN2R
DIN3L
DIN3R
23
23
23
23
23
23
0
DIN1L
SDIN2
23
0
DIN1R
0
DIN2L
0
DIN2R
0
SDOUTAD2
Lch
0
SDOUTAD2
Rch
23
0
DOUT4L
23
0
DIN4L
23
0
SDOUTAD
Lch
23
0
SDOUTAD
Lch
23
23
0
DOUT4R
23
0
23
DIN4R
23
0
23
SDOUTAD
Rch
23
0
23
SDOUTAD
Rch
(don’t care)
Figure 45. TDM mode PCM Short Frame (Internal signals are indicated by dotted lines)
256BICK
LRCK
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
BICK(256fs)
SDOUT1
23 22
0
DOUT1L
SDIN1(TDM mode9)
23 22
0
DIN1L
SDIN1(TDM mode10)
23 22
0
DIN1L
SDIN1(TDM mode11)
23 22
0
DIN1L
SDIN2
23 22
0
DOUT1R
23 22
0
DIN1R
23 22
0
DIN1R
23 22
0
DIN1R
23 22
0
DOUT2L
23 22
0
DIN2L
23 22
0
DIN2L
23 22
0
DIN2L
23 22
0
DOUT2R
23 22
0
DIN2R
23 22
0
DIN2R
23 22
0
DIN2R
23 22
0
DOUT3L
23 22
0
DIN3L
23 22
0
DIN3L
23 22
0
SDOUTAD2
Lch
23 22
0
DOUT3R
23 22
0
DIN3R
23 22
0
DIN3R
23 22
0
SDOUTAD2
Rch
23 22
0
DOUT4L
23 22
0
DIN4L
23 22
0
SDOUTAD
Lch
23 22
0
SDOUTAD
Lch
23 22
0
23 22
DOUT4R
23 22
0
23 22
DIN4R
23 22
0
23 22
SDOUTAD
Rch
23 22
0
23 22
SDOUTAD
Rch
(don’t care)
Figure 46. TDM mode PCM Long Frame (Internal signals are indicated by dotted lines)
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■ μP Interface Setting and Pin Status
SPI or I2C bus interface mode can be selected by the I2CSEL pin. Pin statuses that are changed by I2CSEL
pin setting are shown below.
I2CSEL
L
PDN
L
SO/SDA
SCLK/SCL
Hi-Z (CSN pin = “H”)
Input
SPI Interface
Hi-Z (CSN pin = “H”)
L
H
Input
function(CSN pin = “L”)
H
L
“Hi-Z”→ pull-up
“Hi-Z”→ pull-up
I2C BUS
H
H
function
function
Note 45. The CSN pin must be set to “H” when not interfacing to a micro controller or the AK7755 is in
power-down mode in SPI interface mode.
■ SPI Interface (I2CSEL pin = “L”)
1. Configuration
The access format is: Command code (8bits) + Address + Data (MSB First).
Bit Length
Command Code 8
MSB bit is R/W flag. The following 7-bits indicate access area such
as PRAM/ CRAM/Registers.
Address
16 or 0
Valid only for those cases where accessed areas have addresses such
as PRAM /CRAM/OFREG. When no address is assigned, there is no
data.
Data
Later Section Write or Read data
SOPCFG bit selects SO output (Hi-z or Low) during CSN = “H”.
Write operation
CSN
SCLK
SI
don’tcare
(L/H)
Command Code (8bit)
Address (16bit or 0bit)
SO Hi-Z
Data (write)
Hi-Z
Low
Echo Back
Low
Read operation
X (L/H)
Figure 47. SPI Interface Write
CSN
SCLK
SI
don’tcare
(L/H)
Command Code (8bit)
SO Hi-Z
Low
X (L/H)
Address (16bit or 0bit)
Echo Back
Data (read)
Hi-Z
Low
Figure 48. SPI Interface Read
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2. Command Code
BIT7
BIT6
BIT5
R/W flag
Area to be accessed
R/W Flag: Write at “1”, Read at “0”.
BIT4
Access data and accompanying data
BIT6 BIT5 BIT4 BIT3~0
0
0
0
Number of Write
0
0
1
Number of Write
0
1
0
0100
0010
0
1
1
1000
0100
0010
1011
1
1
1
0
0
1
0
1
0
1
1
1
Register Address
Register Address
0000
0110
1010
0000
0010
0100
0110
1000
1010
1100
BIT3
BIT2
BIT1
Accompanying data to the access area
BIT0
Write preparation to CRAM during RUN
Write preparation to OFREG during RUN
Write operation to CRAM during RUN
Write operation to OFREG during RUN
Write/Read operation to PRAM during system reset
Write/Read operation to CRAM during system reset
Write/Read operation to OFREG during system reset
Write/Read operation to ACRAM (Accelerator
Coefficient RAM) during system reset
Internal control registers 00h~0Fh
Internal control registers 10h~1Fh
Device Identification (Read only)
Internal control registers 26h
Internal control registers 2Ah
Error Status Read
CRC Write/Read
Write operation of JX code
Read operation from MIR1
Read operation from MIR2
Read operation from MIR3
Read operation from MIR4
3. Address
The address description is always LSB justified. Accessing command code BIT[6:4]= “000” to “011”
requires a 16-bit address. Accessing command code BIT[6:4]= “100” to “111” requires no address.
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[AK7755]
4. Data
The length of write data depends on the write area size. When accessing RAM, data may be written to
sequential address locations by writing data continuously.
Write
Command
Description
Write preparation to CRAM during RUN.
Command code BIT3~BIT0 bits determines the amount of write
0x80~0x8F 16bit
24bit×n
operation. (0x80 # of write: 1, 0x81 # of write: 2, ----, 0x8F # of
write: 16) If the actual amount of write operations exceeds the
defined amount, that data will be ignored.
Write preparation to OFREG during RUN
Command code BIT3~BIT0 bits determines the amount of write
0x90~0x9F 16bit
24bit×n
operation. (0x90 # of write: 1, 0x91 # of write: 2, ----, 0x9F # of
write: 16) If the actual amount of write operations exceeds the
defined amount, that data will be ignored.
Write operation to OFREG during RUN. 0 address should be
0xA2
16bit
None
written.
0xA4
16bit
None
Write operation to CRAM during RUN. 0 address should be written.
0xB2
16bit
24bit×n
Write operation to OFREG during system reset
0xB4
16bit
24bit×n
Write operation to CRAM during system reset
0xB8
16bit
40bit×n
Write operation to PRAM during system reset
0xBB
16bit
24bit×n
Write operation to ACRAM during system reset
0xC0~0xDF None
8bit
Write operation to Control Registers 00~1Fh
0xE6
None
8bit
Write operation to Control Register 26h
0xEA
None
8bit
Write operation to Control Register 2Ah
0xF2
None
16bit
CRC Write
0xF4
None
8bit
Write operation of External Conditional Jump Code
Data length is defined by the command code which specifies the area to be accessed. When accessing
RAM, data may be read from sequential address locations by reading data continuously. Writing other
than this command code is prohibited.
Address
Data Length
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[AK7755]
Read
Command
0x24
0x32
0x34
0x38
0x3B
0x40~0x5F
0x60
0x66
0x6A
0x70
0x72
Address
16bit
16bit
16bit
16bit
16bit
None
None
None
None
None
None
None
Data Length
24bit×n
24bit×n
24bit×n
40bit×n
24bit×n
8bit
8bit
8bit
8bit
8bit
16bit
Description
CRAM/OFREG Preparation Data Read during RUN
Read operation form OFREG during system reset
Read operation from CRAM during system reset
Read operation from PRAM during system reset
Read operation from ACRAM during system reset
Write operation to Control Registers 00~1Fh
Device Identification
Write operation to Control Register 26h
Write operation to Control Register 2Ah
DSP Error Status Read
CRC result Read
Read operation from MIR1
0x76
32bit
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
None
Read operation from MIR2
0x78
32bit
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
None
Read operation from MIR3
0x7A
32bit
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
None
Read operation from MIR4
0x7C
32bit
28-bit is upper-bit justified. Lower 4-bits are for validity flags.
Reading other than this command code is prohibited.
5. Echo-Back Mode
The AK7755 has an echo-back mode that the device outputs write data sequentially from the SO pin.
5-1. Write Sequence
CSN
SI
COMMAND
SO
ADDRESS1
COMMAND
ADDRESS2
ADDRESS1
DATA1
don’tcare
(L/H)
DATA2
ADDRESS2
DATA1
COMMAND
ADDRESS1
COMMAND
Hi-Z or Low
Figure 49. Echo-Back Writing 1 (SPI)
The input data of the SI pin is echoed back on the SO pin by shifting 8-bit to the right.
CSN
SI
SO
n=3~5
0xB4
X (Hi-Z or low)
0x00
0x00
COMMAND
ADDRESS1
DATA1
ADDRESS2
DATAn
Dummy 8bit
DATA1
DATAn
X (Hi-Z or Low)
Figure 50. Echo-Back Writing 2 (SPI)
It is possible to verify the written data by inputting an extra 8-bit clock. If the dummy data is more than
the data length, this dummy data is written on the next address. (40 bits for PRAM, 24 bits for CRAM
and 24 bits for OFREG writings)
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5-2. Read Sequence1 (with PRAM, CRAM, OFREG addresses)
CSN
SI
COMMAND
ADDRESS1
SO
COMMAND
ADDRESS2
ADDRESS1
don’tcare
(L/H)
COMMAND
READ DATA
READ DATA
Hi-Z or Low
ADDRESS1
COMMAND
Figure 51. Read Sequence1 in Echo-Back Mode (SPI)
Data of the address2 field is not echoed back in read operation. The read data on the SO pin is output
after writing to the address2 field.
5-3. Read Sequence2 (No Register address）
CSN
SI
COMMAND
SO
don’tcare
(L/H)
READ DATA
COMMAND
Hi-Z or Low
don’tcare
(L/H)
READ DATA
Hi-Z or Low
Figure 52. Read Sequence2 in Echo Back Mode (SPI)
Data output has priority in read sequence.
6. Format
6-1. Write Operation during System Reset
1. Program RAM (PRAM) Write (during system reset)
Field
Write data
(1) COMMAND Code
0xB8
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
2. Coefficient RAM (CRAM) Write (during system reset)
Field
Write data
(1) COMMAND Code
0xB4
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
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3. Offset REG (OFREG) Write (during system reset)
Field
Write data
(1) COMMAND Code
0xB2
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 A5 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 0 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
4. Accelerator Coefficient RAM (ACRAM) Write (during system reset)
Field
Write data
(1) COMMAND Code
0xBB
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 A6 A5 A4 A3 A2 A1 A0
(4) DATA1
D19~D12
(5) DATA2
D11~D4
(6) DATA3
D3~D0 0 0 0 0
Three bytes of data may be written continuously for each address.
6-2. Write Operation during System Reset / RUN
1. Control Register Write (during system reset / RUN)
Field
Write data
(1) COMMAND Code
0xC0~0xDF, 0xE6, 0xEA
(2) DATA
D7~D0
2. External Conditional Jump Code Write (during system reset / RUN)
Field
Write data
(1) COMMAND Code
0xF4
(2) DATA
D7~D0
3. CRC Code Write (during system reset / RUN)
Field
Write data
(1) COMMAND Code
0xF2
(2) DATA
D15~D8
(3) DATA
D7~D0
6-3. Write Operation during RUN
1. Coefficient RAM (CRAM) Write Preparation (during RUN)
Preparation
Write data
(1) COMMAND Code
0x80~0x8F (one data at 80h, sixteen data at 8Fh)
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 ~ A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
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2. Coefficient RAM (CRAM) Write Operation (RUN)
Execute
Write data
(1) COMMAND Code
0xA4
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
Note 46. The COMMAND determines the length of the data. If the written data exceeds the allotted
amount, the excess data is ignored.
3. Offset REG (OFREG) Write Preparation (during RUN)
Preparation
Write data
(1) COMMAND Code
0x90~0x9F (one data at 0x90, sixteen data at 0x9F)
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 0 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
0 0 0 D12 D11 D10 D9 D8
(6) DATA3
D7~D0
4. Offset REG (OFREG) Write Operation (during RUN)
Execute
Write data
(1) COMMAND Code
0xA2
(2) ADDRESS1
00000000
(3) ADDRESS2
00000000
Note 47. The COMMAND determines the length of the data. If the written data exceeds the allotted
amount, the excess data is ignored.
6-4. Read Operation during System Reset
1. Program RAM (PRAM) Read (during system reset)
Field
Write data
Readout data
(1) COMMAND Code 0x38
00000000
(2) ADDRESS1
(3) ADDRESS2
00000000
(4) DATA1
0 0 0 0 D35 D34 D33 D32
(5) DATA2
D31~D24
(6) DATA3
D23~D16
(7) DATA4
D15~D8
(8) DATA5
D7~D0
Five bytes of data may be written continuously for each address.
2. Coefficient RAM (CRAM) Read (during system reset)
Field
Write data
Readout data
(1) COMMAND Code 0x34
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 ~ A0
(4) DATA1
D23~D16
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
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3. Offset REG (OFREG) Read (during system reset)
Field
Write data
Readout data
(1) COMMAND Code 0x32
(2) ADDRESS1
00000000
(3) ADDRESS2
0 0 0 A4 A3 A2 A1 A0
(4) DATA1
00000000
(5) DATA2
D15~D8
(6) DATA3
D7~D0
Three bytes of data may be written continuously for each address.
4. Accelerator Coefficient RAM (CRAM) Read (during system reset)
Field
Write data
Readout data
(1) COMMAND Code 0x3B
(2) ADDRESS1
0 0 0 0 0 A10 A9 A8
(3) ADDRESS2
A7 ~ A0
(4) DATA1
D19~D12
(5) DATA2
D11~D4
(6) DATA3
D3~D0 0 0 0 0
Three bytes of data may be written continuously for each address.
6-5. Read Operation during System Rest / RUN
1. Control Register Read (during system reset / RUN)
Field
Write data
(1) COMMAND Code 0x40~0x5F, 0x66, 0x6A
(2) DATA
Readout data
D7~D0
2. Device Identification (during system rest / RUN)
Field
Write data
Readout data
(1) COMMAND Code 0x60
(2) DATA
D7 D6
0
1
D5
0
5
D4
1
D3
0
D2 D1 D0
1
0
1
5
3. CRC Result Reading (during system reset / RUN)
Field
Write data
Readout data
(1) COMMAND Code 0x72
(2) DATA1
D15~D8
(3) DATA2
D7~D0
4. DSP Error Status Read (during system reset / RUN)
Field
Write data
Output
(1) COMMAND Code 0x70
(2) DATA
Active low output
D7: CRCERRN: 0: CRC error
D6: WDTERRN : 0: Watch Dog Timer error
D5: GP0
0:clear 1: set
D4: GP1
0:clear 1: set
D3: PLLLOCK
0:unlock 1:lock
D2: N/A
D1: N/A
D0: N/A
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6-6. Read Operation during RUN
1. CRAM Write Preparation Read (during RUN)
Field
Write data
(1) COMMAND Code 0x24
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
2. OFREG Write Preparation Read (during RUN)
Field
Write data
(1) COMMAND Code 0x24
(2) ADDRESS1
(3) ADDRESS2
(4) DATA1
(5) DATA2
(6) DATA3
Readout data
A15~A8
A8~A0
D23~D16
D15~D8
D7~D0
Readout data
A15~A8
A8~A0
00000000
D15~D8
D7~D0
3. MIR1/2/3/4 Read (during RUN)
Field
Write data
Readout data
(1) COMMAND Code 0x76(MIR1)
0x78(MIR2)
0x7A(MIR3)
0x7C(MIR4)
(2) DATA1
D27~D20
(3) DATA2
D19~D12
(4) DATA3
D11~D4
(5) DATA4
D3 D2 D1 D0 (flag3) (flag2) (flag1) (flag0)
Note 48. Data is valid only when all flags are zero.
7. Timing
7-1. RAM Writing Timing during System Reset
Write to Program RAM (PRAM), Coefficient RAM (CRAM), Offset REG (OFREG) and Accelerator
Coefficient RAM (CRAM) during system reset in the order of command code, address and data. The
PRAM start address is fixed to 0h. When writing the data to consecutive address locations, continue to
input data only. PRAM address is incremented by 1 automatically.
DSPRESETN bit
CSN
SCLK
SI
don’t care
(L/H)
Command
Address
DATA
DATA
DATA
DATA
DATA
don’t care
(L/H)
RDY = “H”
Figure 53. Writing to RAM at Consecutive Address Locations (SPI)
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DSPRESETN bit
CSN
SCLK
SI
don’tcare
(L/H)
Command
don’tcare
(L/H)
Address DATA
Command
Address DATA
don’tcare
(L/H)
RDY = “H”
Figure 54. Writing to RAM at Random Address Locations (SPI)
7-2. RAM Writing Timing during RUN
These operations are to rewrite the Coefficient RAM (CRAM) and Offset REG (OFREG) during
RUN. Data writing is executed in two steps; write preparation and write execution. The written data
can be confirmed by reading the write preparation data.
1. Write Preparation
After inputting the assigned command code (8 bits) to select the number of data from 1 to 16, input the
starting address of write (16 bits all “0”) and the number of data assigned by command code in this
order. In slave mode, a write preparation command is prohibited for “2 LRCK” cycles (2/fs) after
releasing DSP reset (DSPRESETN bit).
2. Write Preparation Data Confirmation
After write preparation, prepared data for writing can be confirmed. Address and Data are read in this
order by write preparation data confirmation command “24h”. The data will be “0x000001” when
reading more than write preparation data. Execute write preparation again when the address and data
are disturbed by external noise.
3. Write Execution
Upon completion of this operation, execute a RAM write during RUN by inputting the corresponding
command code and address (16 bits, all “0”) in this order.
Note 49. Execute write preparation, write preparation read and write execution in this order. When
writing to RAM without a write preparation sequence, a malfunction occurs. Access operation
by a microcontroller is prohibited until RDY changes to “H”.
Write modification of the RAM content is executed whenever the RAM address for modification is
assigned. For example, when 5 data are written, from RAM address “10”, it is executed as shown
below.
RAM execution address
Write execution position
7
8
9
10 11 13 16 11 12 13 14 15
↓ ↓
↓ ↓ ↓
○ ○ ↑
○ ○ ○
Note 50. Address “13” is not executed until rewriting address “12”.
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DSPRESETN bit= “1”
CSN
(Ex.) When # of DATA is 4
CRAM Command Code 0x83
OFREG Command Code 0x93
SCLK
SI
don’tcare
(L/H)
Command Address DATA0
Code
RDY = “H”
CRAM
DATA1
DATAn-1 DATAn
don’tcare
(L/H)
0x80(# of DATA: 1)~0x8F(# of DATA: 16)
OFREG 0x90(# of DATA: 1)~0x9F(# of DATA: 16)
Figure 55. CRAM/OFREG Write Preparation (SPI)
DSPRESTN bit= “1”
CSN
SCLK
don’t care
(L/H)
SI
don’t care
(L/H)
0x24
Hi-Z or Low
SO
Address
DATA
DATA
DATA
DATA
DATA
RDY= “H”
Figure 56. CRAM/OFREG Write Preparation Confirm (SPI)
DSPRESETN bit= “1”
CSN
SCLK
SI
don’tcare
(L/H)
Command
00000000
00000000
max 400ns
CRAM0xA4, OFREG0xA2
RDY
RDYLG (Note 52)
Figure 57. CRAM/OFREG Write (SPI)
Note 51. If the DSP program is designed to refer all coefficients which may be changed by an external
microcontroller, RDY signal rises to high within 2LRCK after a writing command. No further
access to DSP is permitted until this write operation is completed. However, while the CSN pin is
“L” level, RDY signal keeps “L” level.
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7-3. External Conditional Jump
External Conditional Jump Code Writing (during System Reset and RUN)
(1) COMMAND
0xF4
(2) DATA
D7~D0
External Conditional Jump code can be input during both DSP Reset and RUN. Input data is set to the
designated register on the rising edge of LRCKO. The RDY pin changes to “L” when the command code
is transferred, and it changes to “H” when write operations are completed. When any single bit of “1”
data in 8-bit External Jump code matches an “1” bit data in the IFCON field, a Jump instruction is
executed. Then, the RDY pin changes to “H” when the rise of LRCKO is captured. Access operation by
microcontroller is prohibited until the RDY pin changes to “H”. IFCON field is the area where the
external conditions are written. This Jump code is reset to 00h by setting the IRSTN pin to “L”, but it is
not reset by System Reset.
7
■
4 3 2 1 0
■ ■ ■ ■ ■
↑
Check if “1” of IFCON field corresponds with External Conditional Jump including Jump pins
by at least one at the same location.
7
↓
0
IFCON Field
       
External Conditional Jump Code
■ ■ ■ ■ ■ ■ ■ ■
External Conditional Jump Code
6
■
5
■
DSPRESETN bit
SCLK
SI
don’tcare
(L/H)
F4h
D7…D0
don’tcare
(L/H)
CSN
LRCK
RDY
Next command write is available
Figure 58. External Conditional Timing in System Reset (SPI)
DSPRESETN bit
SCLK
SI
don’tcare
(L/H)
F4h
D7 … D0
don’tcare
(L/H)
CSN
LRCK
RDY
Figure 59. External Conditional Jump Timing during RUN (SPI)
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7-4. RAM Reading Timing during System Reset
Read Program RAM (PRAM), Coefficient RAM (CRAM), Offset REG (OFREG) and Accelerator
Coefficient RAM (ACRAM) during System Reset in the order of the input Command code and the
Address. After writing the Command, the data comes out from the SO pin synchronous with falling
edge of SCLK. (The SI pin input data is “Don’t care”) When reading Data at consecutive address
locations, continue to input SCLK as is.
DSPRESETN bit
CSN
SCLK
don’t care
(L/H)
SI
Command
Address
don’t care
(L/H)
Hi-Z or Low
SO
DATA
Echo Back Output
DATA
DATA
DATA
DATA
RDY = “H”
Figure 60. RAM Reading at Consecutive Address (SPI)
7-5. RAM Reading Timing during System Reset and RUN
Write a command code, to read control registers, device identification code, CRC result and error
status during RUN time or system reset state. After completing a Command code write, the data comes
out from the SO pin synchronous with falling edge of SCLK. (The SI pin input data is “Don’t care”)
DSPRSTN bit
CSN
SCLK
SI
don’tcare
(L/H)
Hi-Z or Low
SO
Command
Address
don’tcare
(L/H)
DATA
Echo Back Output
RDY = “H”
Figure 61. AM Reading during System Reset/RUN (SPI)
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■ I2C Bus Interface (I2CSEL pin= “H”)
Access to the AK7755 registers and RAM is controlled by an I²C bus. The AK7755 supports fast-mode
I2C-bus (max: 400kHz) only.
1. Data Transfer
In order to access any IC devices on the I2C bus, input a start condition first, followed by a single Slave
address which includes the Devices Address. IC devices on the BUS compare this Slave address with
their own addresses and the IC device which has an identical address with the Slave address generates an
acknowledgement. An IC device with the identical address then executes either a read or a write
operation. After the command execution, input a Stop condition.
1-1. Data Change
Change the data on the SDA line while the SCL line is “L”. The SDA line condition must be stable
and fixed while the clock is “H”. Change the Data line condition between “H” and “L” only when the
clock signal on the SCL line is “L”. Change the SDA line condition while the SCL line is “H” only
when the start condition or stop condition is input.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 62. Data Change (I2C)
1-2. Start Condition and Stop Condition
A start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is
“H”. All instructions are initiated by a Start condition. A stop condition is generated by the transition
of “L” to “H” on the SDA line while the SCL line is “H”. All instructions end by a Stop condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 63. Start Condition and Stop Condition (I2C)
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1-3. Repeated Start Condition
When a Start condition is received again instead of a Stop condition, the bus changes to a Repeated
Start condition. A Repeated Start condition is functionally the same as a Start condition.
SCL
SDA
START CONDITION
Repeated Start CONDITION
Figure 64. Repeated Start Conditions (I2C)
1-4. Acknowledge
An external device that is sending data to the AK7755 releases the SDA line (“H”) after receiving one
byte of data. An external device that receives data from the AK7755 then sets the SDA line to “L” at
the next clock. This operation is called “acknowledgement”, and it enables verification that the data
transfer has been properly executed. The AK7755 generates an acknowledgement upon receipt of a
Start condition and a Slave address. For a write instruction, an acknowledgement is generated
whenever receipt of each byte is completed. For a read instruction, succeeded by generation of an
acknowledgement, the AK7755 releases the SDA line after outputting data at the designated address,
and it monitors the SDA line condition. When the Master side generates an acknowledgement without
sending a Stop condition, the AK7755 outputs data at the next address location. When no
acknowledgement is generated, the AK7755 ends data output (not acknowledged).
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
START
CONDITION
Figure 65. Generation of Acknowledgement (I2C)
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1-5. The First Byte
The First Byte, which includes the Slave-address, is input after the Start condition is set, and a target IC
device that will be accessed on the bus is selected by the Slave-address. The Slave-address is configured
with the upper 7-bits. When the I2CSEL pin = “H” and the EXTEEP pin = “L”, data of the upper 6-bits is
“001100”. The next 1 bit is the address bits that select the desired IC which are set by the CAD pin. The
slave address will be “0011000” when the I2CSEL pin =“H” and the EXTEEP pin = “L”. However, the
CAD pin should be set to “L” if the MATSEL pin = “L” to set the slave address to “0011000” when
downloading from EEPROM by DLS bit even if the I2CSEL pin =“H” and the EXTEEP pin = “L”.
When the Slave-address is inputted, an external device that has the identical device address generates an
acknowledgement and instructions are then executed. The 8th bit of the First Byte (lowest bit) is allocated
as the R/W Bit. When the R/W Bit is “1”, the read instruction is executed, and when it is “0”, the write
instruction is executed.
Note 52. In this document, there is a case that describes a “Write Slave-address assignment” when both
address bits match and a Slave-address at R/W Bit = “0” is received. There is a case that
describes “Read Slave-address assignment” when both address bits matches and a Slave-address
at R/W Bit = “1” is received.
0
0
1
1
0
0
CAD
R/W
When I2CSEL pin = “H” and EXTEEP pin = “L”
0
0
1
1
0
0
0
R/W
When I2CSEL pin = “H” and EXTEEP pin = “H”, or using DLS bit
Figure 66. First Byte Configuration (I2C)
1-6. The Second and Succeeding Bytes
The data format of the second and succeeding bytes of the AK7755 Transfer / Receive Serial data
(command code, address and data in microcontroller interface format) on the I2C BUS are all
configured with a multiple of 8-bits. When transferring or receiving those data on the I2C BUS, they
are divided into an 8-bit data stream segment and they are transferred / received with the MSB side
data first with an acknowledgement in-between.
Example)
When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format:
(1)マイコンインターフェースのフォーマット
(1) Microcontroller
Interface Format
A1
B2
のフォーマット
(2) I(1)I
C CFormat
2
C3
2
A1
B2
A
24BIT
8BIT
C3
A
8BIT
8BIT
A …Acknowledge
Figure 67. Division of Data (I2C)
Note 53. In this document, there is a case that describes a write instruction command code which is
received at the second byte as “Write Command”. There is a case that describes a read
instruction command code which is received at the second byte as “Read Command”.
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2. Write Sequence
In the AK7755, when a “Write-Slave-address assignment” is received at the first byte, the write
command at the second byte and data at the third and succeeding bytes are received. At the data block,
address and write data are received in a single-byte unit each in accordance with a command code. The
number of write data bytes is fixed by the received command code.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Command
Code
A
C
K
Data(n)
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 68. Write Sequence (I2C)
3. Read Sequence
In the AK7755, when a “write- slave-address assignment” is received at the first byte, the read command
at the second byte and the data at the third and succeeding bytes are received. At the data block, the
address is received in a single byte unit in accordance with a read command code. When the last address
byte (or command code if no address assignment is specified) is received and an acknowledgement is
transferred, the read command waits for the next restart condition. When a “read slave-address
assignment” is received at the first byte, data is transferred at the second and succeeding bytes. The
number of readable data bytes is fixed by the received read command.
After reading the last byte, assure that a “not acknowledged” signal is received. If this “not
acknowledged” signal is not received, the AK7755 continues to send data regardless whether data is
present or not, and since it does not release the BUS, the stop condition cannot be properly received.
S
T
A
R
T
SDA
R
E
S
T
A
R
T
R/W="0"
Slave
S Address
Command
code
A
C
K
Slave
S Address
Data(n)
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
A C
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
T C
E K
R
Figure 69. Read Sequence (I2C)
014006643-E-00
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[AK7755]
4. Acknowledgement Polling
The AK7755 cannot receive instructions while the RDY pin (Data Write Ready pin) is at low level.
The maximum transition time of the RDY pin from low level to high level is 2/fs (fs: sampling
frequency), but it is possible to confirm in a faster cycle that the RDY pin has become high by
checking the AK7755 internal condition, which is made by verifying the acknowledgement.
4-1. Generation of “Not Acknowledged”
The AK7755 does not accept command codes until the RDY pin is set to a high level, when a
command is received to set the RDY pin to a low level. In order to confirm the RDY pin condition, a
“Write Slave-Address assignment” should be sent after a Start condition. If the RDY pin is then at a
low level, “Acknowledgement” is not generated at the succeeding clock (generation of “Not
Acknowledged”). After sending “Not Acknowledged”, the BUS is released and all receiving data are
ignored until the next start condition (behaves as if it received Slave address of other device).
4-2. When Read Slave-address assignment is received without receiving read command code
Data read in the AK7755 can be made only in the previously documented Read sequence. Data cannot
be read out without receiving a read command code. The AK7755 generates a “Not Acknowledged”
when a “Read Slave-address Assignment” is received without proper receipt of read command.
5. Limitation in use of I2C Interface
The I2C interface does not support the following features.
No operation in Hs Mode (max:3.4MHz). The AK7755 Supports FAST mode (max:400KHz).
Note 54. Do not turn off the power of the AK7755 whenever the power supplies of other devices of the
same system are turned on. The source of the pull-up of SDA and SCL of I2C BUS must not
exceed the TVDD. (The diode exists for TVDD in the SDA and SCL pins.)
014006643-E-00
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[AK7755]
■ Analog Input Block
1. Microphone Input Selector
Either analog input or digital microphone interface can be chosen for the AK7755. Set AINE bit
(CONT00: D3) to “1” when using #31-34 pins as analog input pins, and set DMIC1(CONT1E: D7) or
DMIC2 bit (CONT1E: D4) to “1” when using these pins as digital microphone interface. ADC input
signals can be switched by DIFL bit (CONT09: D5), DIFR bit (CONT09: D7), INL bit (CONT09: D4)
and INTR bit (CONT09: D6) for analog inputs. When DIFL bit = “0” and DIFR bit = “0”, input signals
of IN1, IN2, IN3 and IN4 pins for microphone amplifiers can be selected by INL and INR bits. When
DIFL bit = “1” and DIFR bit = “1”, a differential input is acceptable as input pins becomes INP1/INN1
pins and INP2/INN2 pins.
IN1/INP1/DMDAT1 pin
IN2/INN1/DMCLK1 pin
ADC
Lch
DIFL bit
IN3/INP2/DMDAT2 pin
IN4/INN2/DMCLK2 pin
AK7755
INL bit
MIC-Amp
Lch
INR bit
ADC
Rch
DIFR bit
MIC-Amp
Rch
Figure 70. Microphone Input Selector
ADC Lch Microphone Input Selector
DIFL bit INL bit
ADC Lch
0
0
IN1
0
1
IN2
1
X
INP1/INN1
(x: Do not care)
ADC Rch Microphone Input Selector
DIFR bit INR bit
ADC Rch
(default)
0
0
IN3
(default)
0
1
IN4
1
X
INP2/INN2
(x: Do not care)
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[AK7755]
2. Microphone Input Gain
The AK7755 has a microphone gain amplifier. L and R channel gains can be set independently by
MGNL[3:0] bits (CONT12: D3-D0) and MGNR[3:0] bits (CONT12: D7-D4). Input impedance is typ.
20k. This gain amplifier executes zero cross detection when changing the gain by setting MICLZCE bit
(CONT1A: D0) = “1” / MICRZCE bit (CONT1A: D1) = “1”. Zero cross detection is executed on L and
R channels independently. Timeout period of the zero cross detection is 16ms. When MICLZCE bit =
“0” / MICRZCE bit = “0”, zero cross detection is not performed and the volume is changed immediately
when register is written.
When writing to MGNL3-0/MGNR3-0 bits continually, take an interval of zero crossing timeout periods
or more. If the MGNL3-0/MGNR3-0 bits are changed before zero crossing, the volume of Lch and Rch
may differ. When the volume that is same as the present is set, the zero crossing counter is not reset and
timeout according to the previous writing timing.
Zero Crossing Timeout
When MICLZCE bit = “1” / MICRZCE bit = “1”, the Lch/Rch volume level are changed independently
by zero crossing detection or zero crossing timeout.
fs
48kHz
Mode
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Zero cross Timeout Period
16ms
MGNL[3] MGNL[2] MGNL[1] MGNL[0]
Input Gain
MGNR[3] MGNR[2] MGNR[1] MGNR[0]
0
0
0
0
0dB
(default)
0
0
0
1
2dB
0
0
1
0
4dB
0
0
1
1
6dB
0
1
0
0
8dB
0
1
0
1
10dB
0
1
1
0
12dB
0
1
1
1
14dB
1
0
0
0
16dB
1
0
0
1
18dB
1
0
1
0
21dB
1
0
1
1
24dB
1
1
0
0
27dB
1
1
0
1
30dB
1
1
1
0
33dB
1
1
1
1
36dB
Table 2. Microphone Input Gain
3. Analog DRC (ADRC)
The microphone input gain can be set by DSP programs with the AK7755. This function is enabled by
setting ADRCRE bit = “1”/ADRCLE bit = “1” (CONT1A: D3/D2). In this setting, control registers
MGNL[3:0] and MDNR[3:0] bits (CONT12) are not valid. By reading AMGNL[3:0] (CONT1B:
D3-D0) / AMGNR[3:0] (CONT1B: D7-D4) bits, gain settings can be downloaded externally.
When MICLZCE bit = “1”/MICRZCE bit = “1”, the Lch/Rch volume level are changed independently
by zero crossing detection or zero crossing timeout. Please refer to the AK7755 programing manual for
DSP programs.
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[AK7755]
4. LINE Input Gain Amplifier
The AK7755 has a gain amplifier for line inputs. It is enabled by setting PMLI bit (CONT0F: D5) =
“1”, and it outputs a signal to the L channel of the ADC2. LIGN[3:0] bits (CONT13: D7-D4) controls
the gain. The typical input impedance is 20k (typ). A pop noise occurs if the input gain is changed
during operation.
The AK7755 becomes digital microphone interface mode when DMIC2 bit (CONT1E: D4) = “1”.
Digital microphone input data to the DMDAT2 pin is input to the Lch/Rch of the ADC2.
ADC2 Input Setting
DMIC2 bit
ADC2 Lch Input
0
LIN
1
Digital Microphone
Mode LIGN[3]
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
1
9
1
A
1
B
1
C
1
D
1
E
1
F
1
LIGN[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ADC2 Rch Input
No
Digital Microphone
LIGN[1]
LIGN[0]
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Table 3. Line Input Gain
014006643-E-00
(default)
Input Gain
0dB
(default)
-3dB
-6dB
-9dB
-12dB
-15dB
-18dB
-21dB
N/A
+3dB
+6dB
+9dB
+12dB
+15dB
+18dB
+21dB
2014/10
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[AK7755]
■ ADC Block
1. ADC High Pass Filter
A digital High Pass Filter (HPF) is integrated for DC offset cancellation of the ADC input. The cut-off
frequency of the HPF is approximately 1Hz (at fs=48kHz).
fs
Cut-off frequency
48kHz
3.73Hz
44.1kHz
3.43Hz
8kHz
0.62Hz
2. ADC Soft Mute
2-1. Description
The ADC block has a digital soft mute circuit. The soft mute operation is performed in the digital
domain. The output signal is attenuated to -∞ in “ADC Digital Volume Level x ATT transition time”
from the current ADC Digital Volume Setting Level by setting ADMUTE and AD2MUTE bits to “1”.
When the ADMUTE (CONT1A: D7) and AD2MUTE (CONT1A: D6) bits are returned to “0”, the
mute is cancelled and the output attenuation gradually changes to ADC Digital Volume Setting Level
in “ADC Digital Volume Level x ATT transition time”. If the soft mute is cancelled before attenuating
to -∞ after starting the operation, the attenuation is discontinued and returned to ADC Digital Volume
Setting Level by the same cycle. The soft mute is effective for changing the signal source without
stopping the signal transmission. The transition time from 0dB to -∞ and vice versa is 828 LRCK
cycles.
The soft mute function works when the ADC is in operation. The attenuation value is initialized by the
PDN pin = “L”.
SMUTE Register Value
Group Delay (GD)
0dB
Attenuation
Group Delay (GD)
828/fs
-∞dB
828/fs
Output Image
Figure 71. ADC Soft Mute
2-2. Input Selector Switching Sequence
The input selector should be changed after soft muting to avoid the switching noise of the input
selector.
· Input Selector Switching Sequence
1. Enable soft mute before changing the channel.
2. Change the Channel.
3. Disable softer mute.
ADMUTE
(2)
(1)
DATT Level
(1)
Attenuation
(3)
-∞
Channel
IN1/IN3
IN2/IN4
Figure 72. ADC Input Channel Switching Sequence Example
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[AK7755]
The period of (1) varies by the setting value of DATT bit. The transition time of attenuation amount
from 0dB to -∞ and vice versa is shown below.
ATSPAD
0
1
LRCK Cycle
828/fs
828/fs x 4
(1)Period (max)
fs=48kHz
17.25ms
69ms
fs=44.1kHz
18.82ms
75.27ms
fs=8kHz
103.5ms
414ms
When changing channels, the input channel should be changed during (2). The period of (2) should be
around 200ms because there is some DC difference between the channels (3).
2-3. ADC Digital Volume
The ADC of the AK7755 has channel-independent digital volume control (256 levels, 0.5dB step).
VOLADL [7:0] bits (CONT15:D7-D0), VOLADR [7:0] bits (CONT16:D7-D0), VOLAD2L [7:0] bits
(CONT17:D7-D0) and VOLAD2R [7:0] bits (CONT1D:D7-D0) control these volume values
independently.
ADC Stereo Lch
VOLADL [7:0]
00h
01h
02h
:
2Fh
30h
31h
:
FDh
FEh
FFh
ADC Stereo Rch
ADC2 Lch
ADC2 Rch
VOLADR [7:0]
VOLAD2L [7:0] VOLAD2R [7:0]
00h
00h
00h
01h
01h
01h
02h
02h
02h
:
:
:
2Fh
2Fh
2Fh
30h
30h
30h
31h
31h
31h
:
:
:
FDh
FDh
FDh
FEh
FEh
FEh
FFh
FFh
FFh
Table 4. ADC Digital Volume Level Setting
Attenuation Level
+24.0dB
+23.5dB
+23.0dB
:
+0.5dB
0.0dB
-0.5dB
:
-102.5dB
-103.0dB
Mute (-∞)
Transition time between set values can be selected by ATSPAD bit (CONT0C: D5).
MODE
ATSPAD
ATT speed
0
0
1/fs
1
1
4/fs
Table 5. ADC Volume Transition Time Setting
The transition between set values is soft transition of 1021 levels in Mode 0. It takes 1021/fs
(21.3ms@fs=48kHz) from 00h to FFh(MUTE). If the PDN pin is set to “L”, the VOLADL/R[7:0] bits
are initialized to 30h.
014006643-E-00
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(default)
[AK7755]
code
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
dB
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
code
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
dB
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-.6.0
-6.5
-7.0
-7.5
code
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
dB
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
-14.0
-14.5
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
-18.0
-18.5
-19.0
-19.5
-20.0
-20.5
-21.0
-21.5
-22.0
-22.5
-23.0
-23.5
code
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
dB
-24.0
-24.5
-25.0
-25.5
-26.0
-26.5
-27.0
-27.5
-28.0
-28.5
-29.0
-29.5
-30.0
-30.5
-31.0
-31.5
-32.0
-32.5
-33.0
-33.5
-34.0
-34.5
-35.0
-35.5
-36.0
-36.5
-37.0
-37.5
-38.0
-38.5
-39.0
-39.5
code
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
dB
-40.0
-40.5
-41.0
-41.5
-42.0
-42.5
-43.0
-43.5
-44.0
-44.5
-45.0
-45.5
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
-51.5
-52.0
-52.5
-53.0
-53.5
-54.0
-54.5
-55.0
-55.5
code
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
dB
-56.0
-56.5
-57.0
-57.5
-58.0
-58.5
-59.0
-59.5
-60.0
-60.5
-61.0
-61.5
-62.0
-62.5
-63.0
-63.5
-64.0
-64.5
-65.0
-65.5
-66.0
-66.5
-67.0
-67.5
-68.0
-68.5
-69.0
-69.5
-70.0
-70.5
-71.0
-71.5
code
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
dB
-72.0
-72.5
-73.0
-73.5
-74.0
-74.5
-75.0
-75.5
-76.0
-76.5
-77.0
-77.5
-78.0
-78.5
-79.0
-79.5
-80.0
-80.5
-81.0
-81.5
-82.0
-82.5
-83.0
-83.5
-84.0
-84.5
-85.0
-85.5
-86.0
-86.5
-87.0
-87.5
code
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
dB
-88.0
-88.5
-89.0
-89.5
-90.0
-90.5
-91.0
-91.5
-92.0
-92.5
-93.0
-93.5
-94.0
-94.5
-95.0
-95.5
-96.0
-96.5
-97.0
-97.5
-98.0
-98.5
-99.0
-99.5
-100.0
-100.5
-101.0
-101.5
-102.0
-102.5
-103.0
Mute
Table 6. ADC Digital Volume Setting List
014006643-E-00
2014/10
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[AK7755]
■ DAC Blocks
1. De-emphasis Filter
The AK7755 has a digital de-emphasis filter (tc=50/15µs) by IIR filter, corresponding to 48kHz
sampling frequency. DEM[1:0] bits control the de-emphasis filter.
DEM mode
0
1
2
3
DEM[1:0]
Sampling Frequency (fs)
00
OFF
01
48kHz
10
44.1kHz
11
32kHz
Table 7. De-emphasis Control
(default)
2. DAC Digital Volume Control
The DACs of the AK7755 have channel independent volume control (256 levels, 0.5 step). The
VOLDAL/R[7:0] bits (CONT18: D7-D0 / CONT19: D7-D0), set the attenuation level of each DAC
channel.
DAC Lch VOLDAL
[7:0]
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
DAC Rch VOLDAR [7:0]
Attenuation Level
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
Table 8. DAC Digital Volume Setting
+12.0dB
+11.5dB
+11.0dB
:
+0.5dB
0.0dB
-0.5dB
:
-114.5dB
-115.0dB
Mute (-∞)
(default)
Transition time between set values can be selected by ATSPDA bit (CONT0C: D5).
MODE
ATSPDA
ATT speed
0
0
1/fs
1
1
4/fs
Table 9. DAC Volume Transition Time Setting
The transition between set values is soft transition of 1021 levels in Mode 0. It takes 1021/fs
(21.3ms@fs=48kHz) from 00h to FFh (MUTE) in Mode 0. If the PDN pin is set to “L”, the
VOLDAL/R[7:0] bits are initialized to 18h.
014006643-E-00
2014/10
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[AK7755]
code
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
dB
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
code
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
dB
-4.0
-4.5
-5.0
-5.5
-.6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
-14.0
-14.5
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
-18.0
-18.5
-19.0
-19.5
code
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
dB
-20.0
-20.5
-21.0
-21.5
-22.0
-22.5
-23.0
-23.5
-24.0
-24.5
-25.0
-25.5
-26.0
-26.5
-27.0
-27.5
-28.0
-28.5
-29.0
-29.5
-30.0
-30.5
-31.0
-31.5
-32.0
-32.5
-33.0
-33.5
-34.0
-34.5
-35.0
-35.5
code
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
dB
-36.0
-36.5
-37.0
-37.5
-38.0
-38.5
-39.0
-39.5
-40.0
-40.5
-41.0
-41.5
-42.0
-42.5
-43.0
-43.5
-44.0
-44.5
-45.0
-45.5
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
-51.5
code
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
dB
-52.0
-52.5
-53.0
-53.5
-54.0
-54.5
-55.0
-55.5
-56.0
-56.5
-57.0
-57.5
-58.0
-58.5
-59.0
-59.5
-60.0
-60.5
-61.0
-61.5
-62.0
-62.5
-63.0
-63.5
-64.0
-64.5
-65.0
-65.5
-66.0
-66.5
-67.0
-67.5
code
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
dB
-68.0
-68.5
-69.0
-69.5
-70.0
-70.5
-71.0
-71.5
-72.0
-72.5
-73.0
-73.5
-74.0
-74.5
-75.0
-75.5
-76.0
-76.5
-77.0
-77.5
-78.0
-78.5
-79.0
-79.5
-80.0
-80.5
-81.0
-81.5
-82.0
-82.5
-83.0
-83.5
code
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
DB
-84.0
-84.5
-85.0
-85.5
-86.0
-86.5
-87.0
-87.5
-88.0
-88.5
-89.0
-89.5
-90.0
-90.5
-91.0
-91.5
-92.0
-92.5
-93.0
-93.5
-94.0
-94.5
-95.0
-95.5
-96.0
-96.5
-97.0
-97.5
-98.0
-98.5
-99.0
-99.5
code
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
dB
-100.0
-100.5
-101.0
-101.5
-102.0
-102.5
-103.0
-103.5
-104.0
-104.5
-105.0
-105.5
-106.0
-106.5
-107.0
-107.5
-108.0
-108.5
-109.0
-109.5
-110.0
-110.5
-111.0
-111.5
-112.0
-112.5
-113.0
-113.5
-114.0
-114.5
-115.0
Mute
Table 10. DAC Digital Volume Setting List
3. DAC Soft Mute
The DAC block has a digital soft mute circuit. The soft mute operation is performed in the digital
domain. The input signal is attenuated to -∞ in “DAC Digital Volume Level x ATT transition time”
from the current DAC Digital Volume Setting Level by setting DAMUTE bit (CONT1A: D5) to “1”.
When the DAMUTE bit is returned to “0”, the mute is cancelled and the input attenuation gradually
changes to DAC Digital Volume Setting Level in “DAC Digital Volume Level x ATT transition
time”. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation
is discontinued and returned to DAC Digital Volume Setting Level by the same cycle. The soft mute is
effective for changing the signal source without stopping the signal transmission. The soft mute
function works when the DAC is in operation. Since the DAC block is in reset state, there is a
possibility that a click noise occurs by a reset and a reset release when CRESETN bit (CONT0F: D3)
= “0” and PMDAL/R bit (CONT0E: D0/D1) = “0”. This click noise should be muted externally. The
attenuation value is initialized by the PDN pin = “L”.
(Setting+2)/fs(max)
DAMUTE Register
(Setting+2)/fs(max)
0dB
Attenuation
-∞dB
GD
GD
Output Image
Soft Mute Operation
Figure 73. DAC Soft Mute Operation
014006643-E-00
2014/10
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[AK7755]
■ Analog Output Block
The AK7755 can output an analog mixing signal of DAC and line-in amplifier outputs from the OUT3
pin. AD conversion is available by setting PMAD2L bit (CONT0E: D5) to “1” even when the analog
mixing output is ON.
AK7755
Mono
ADC
LIN pin
Stereo
DAC Lch
OUT1 pin
LOVOL1[3:0]
LIGN[3:0]
Stereo
DAC Rch
OUT2 pin
LO3SW1(SW1)
LO3SW2(SW2) M
I
LO3SW3(SW3) X
LOVOL2[3:0]
OUT3 pin
LOVOL3[3:0]
Figure 74. Analog Output Circuit
1. Line Output Amplifier
The AK7755 has a line output amplifier. The maximum amplitude is 0.76 × AVDD (2.51[Vpp]
@AVDD=3.3V) and load resistance is 10k (min). LOVOL1/2/3[3:0] bits (CONT14: D3-D0/
CONT14: D7-D4/ CONT13: D3-D0) control the stereo line output volume. A pop noise occurs if the
output gain is changed during operation.
LOVOL1,L2,L3[3:0]
0h
1h
2h
3h
4h
5h
6h
7h
Attenuation
LOVOL1, L2, L3[3:0]
Mute(default)
8h
-28dB
9h
-26dB
Ah
-24dB
Bh
-22dB
Ch
-20dB
Dh
-18dB
Eh
-16dB
Fh
Table 11. Line Output Volume
Attenuation
-14dB
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
0dB
2. Output1 and Output2
The OUT1 and OUT2 pins are connected to the L and R channels of the internal stereo DAC,
respectively. The relationship of each control bit and the OUT1 and OUT2 pins are shown below.
The OUT1 and OUT2 pins output settings are controlled by PMLO1/2 bit (CONT0E: D2/D3),
PMDAL/R bit (CONT0E: D0 /D1) and LOVOL1/2[3:0] bits (CONT014: D3-D0/D7-D4).
PMLO1 bit
0
1
1
1
PMDAL bit
X
0
1
1
LOVOL1[3:0] bits
X
X
0h(mute)
1h-Fh
OUT1 pin Output
Hi-Z
1/2 x AVDD
1/2 x AVDD
DAC Lch Output
PMLO2 bit
0
1
1
1
PMDAR bit
X
0
1
1
LOVOL2[3:0] bits
X
X
0h(mute)
1h-Fh
OUT2 pin Output
Hi-Z
1/2 x AVDD
1/2 x AVDD
DAC Rch Output
014006643-E-00
2014/10
- 92 -
[AK7755]
3. OUT3 (Analog Mixer）
The AK7755 can output an analog mixing signal of DAC and line-in amplifier outputs from the OUT3
pin by setting LO3SW1 bit (CONT09: D1), LO3SW2 bit (CONT09: D2) and LO3SW3 bit (CONT09:
D3).
The line-out amplifier is powered up by setting PMLO3 bit = “1”. Each switch is disconnected and the
OUT3 pin outputs 1/2 × AVDD when LOVOL3[3:0] bits (CONT13: D3-D0) = 0h. L and R channel
signals of the DAC are input to the mixer by setting LO3SW1 bit and LO3SW2 bit to “1” while the
setting of LOVOL3[3:0] bits is not 0h. L and R channel signals of the DAC are not gained by the mixer
block.
The output signal of line-in amplifier is input to the mixer by setting LO3SW3 bit to “1” while the
setting of LOVOL3[3:0] bits is not 0h. Adjust the input voltage and line-in amplifier gain (LIGN[3:0]
bits (CONT13: D7-D4)) to prevent the mixing output exceeds 0.67 × AVDD[Vpp] since the line-in
amplifier output is gained +18dB by the mixer block.
The maximum amplitude of the line-out output is 0.76 × AVDD[Vpp]. VOLDAL[7:0] bits (CONT18:
D7-D0), VOLDAR[7:0] bits (CONT19: D7-D0), LIGN[3:0] bits and LOVOL3[3:0] bits should be
adjusted to not exceed this maximum level.
PMLO3
0
1
1
1
1
1
1
1
1
1
LOVOL3[3:0]
X
0h(mute)
1h-Fh
1h-Fh
1h-Fh
1h-Fh
1h-Fh
1h-Fh
1h-Fh
1h-Fh
LO3SW1
X
X
0
0
0
0
1
1
1
1
LO3SW2
X
X
0
0
1
1
0
0
1
1
LO3SW3
X
X
0
1
0
1
0
1
0
1
SW1
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
SW2
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
ON
SW3
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
Table 12. OUT3 pin Output Switching Setting
014006643-E-00
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- 93 -
[AK7755]
■ Simple Write Error Check
RAM and register data can be checked by cyclic redundancy check (CRC). It realizes a simple error
check of a written data.
1. Checked Data
1-1. SPI Interface
The serial input data of the AK7755 can be checked from a falling edge of the CSN signal to rising
edge of the CSN signal.
· Serial Data D (x): Input data from a falling edge to a rising edge of the CSN.
· Generating Polynomial: G(x)=x16+x12+x5+1 (default=0)
· R(x) is defined as the remainder when D(x) is divided by G(x).
CSN
SCLK
SI
don’tcare
Command Code (8bit)
Address (16bit or 0bit)
X (L/H)
Data (write)
(L/H)
2
1-2. I C Interface
The data after second byte: command code, address and data are checked. (Acknowledge is not
included in the checked data. Therefore, if the command code, address and data are the same as when
SPI interface is used, the CRC error result will also be the same.) The first byte which includes slave
address is excluded. The first byte can be checked with Acknowledge.
· Serial Data D(x): Command Code, Address and Data (Expect slave address)
· Generating Polynomial: G(x)=x16+x12+x5+1 (default=0)
· R (x) is defined as the remainder when D(x) is divided by G(x).
2. Simple Write Error Check Sequence
There are two ways to execute a simple write error check.
2-1. CRC Result Reading
(1) Write serial data D(x) that need to be checked.
(2) Read CRC result (the remainder R(x)) by the command code 72h.
(3) Check the result by a microcomputer.
(4) Repeat (1) ~ (3) when checking another serial data.
Note 55. The internal CRC result is not reflected by the command code
2-2. Checking by the STO pin
(1) Set control register CRCE bit to “1”.
(2) Write serial data D(x) that need to be checked.
(3) Write the remainder R(x) of D(x) ti registers by the command code F2H.
(4) The SDO pin outputs “H” when the calculated remainder of D(x) divided by G(x) equals to the
R(x) value. If not, the STO pin outputs “L”.
(5) Repeat (2) ~ (4) when checking another serial data.
Note 56. The STO pin keeps “L” output until an appropriate remainder R(x) is written to the registers.
014006643-E-00
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[AK7755]
■ EEPROM Interface
1. Data Download
The AK7755 has EEPROM boot mode to read out necessary data from an external EEPROM to the
internal memory via I2C bus. A hands-free function is easily realized in the system using EEPROM
without extra overloads on the microprocessor. The external EEPROM should be connected to the I2C
interface of the AK7755 (I2CSEL pin= “H”). A SPI interface type EEPROM cannot be connected. Write
data as shown in “2. Program Map” to the EEPROM.
Control registers can shift the WRITE command code and data in 2 BYTE unit. However, the data
location from the PRAM WRITE command code (0034h) to OFREG address 31LSB (689Ch) is fixed.
Set “1010000” to I2C slave address of the EEPROM when 256K bit, and set “101000+A16” when 1M
bit.
The AK7755 starts downloading the data from the EEPROM when setting the EXTEEP pin to “H” or
DLS bit (CONT0D: D0) to “1” while the EXTEEP pin = “L” after inputting a 12.288MHz clock to the
XTI pin or connecting a 12.288MHz crystal oscillator to the XTI pin and the XTO pin. The EEST
(SDOUT1) pin goes to “H” while downloading data and the AK7755 becomes an I2C master. Do not
write/read to the other devices that are connected to the same I2C bus during downloading. The EEST
pin returns to “L” after downloading data and the AK7755 will be in I2C slave mode. Interfacing to a
microcontroller becomes available when the EEST pin = “L”.
When accessing the AK7755 after downloading data by CRC function, set CRCE bit (CONT10: D6) to
“0” before access the AK7755. The EEPROM download period is 0.8s (max). Set the EXTEEP pin “H”
→ “L” → “H” or DLS bit (CONT0D, D0) “1” → “0” → “1” to start a data downloading again.
However, data downloading cannnot be executed by DLS bit when selecting memory mat (I2CSEL pin
= MATSEL pin = “H”).
μP
STO
STO
Control
GPI1
Control
EEST (SDOUT1)
EEST (SDOUT1)
GPI2
SCL
SDA
μP/
EEPROM
Interface
EEPROM
SCL
SCL
SDA
μP/
EEPROM
Interface
EEPROM
SCL
SCL
SDA
SDA
SDA
EXTEEP
EXTEEP
I2CSEL= “H”
I2CSEL = “H”
PDN
PDN
Figure 75. EEPROM Connection (Left: EEPROM only, Right: CPU and EEPROM)
014006643-E-00
2014/10
- 95 -
[AK7755]
2. Program Map
EEPROM Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
DATA
C0h
DATA
C1h
DATA
C2h
DATA
C3h
DATA
C4h
DATA
C5h
DATA
C6h
DATA
C7h
DATA
C8h
DATA
C9h
DATA
CAh
DATA
CCh
DATA
D0h
DATA
D1h
DATA
D2h
DATA
D3h
DATA
D4h
DATA
D5h
DATA
D6h
DATA
D7h
DATA
D8h
DATA
D9h
DATA
DAh
DATA
00h
00h
00h
00h
00h
00h
Note
CONT00 Write Command Code
CONT00 Data
CONT01 Write Command Code
CONT01 Data
CONT02 Write Command Code
CONT02 Data
CONT03 Write Command Code
CONT03 Data
CONT04 Write Command Code
CONT04 Data
CONT05 Write Command Code
CONT05 Data
CONT06 Write Command Code
CONT06 Data
CONT07 Write Command Code
CONT07 Data
CONT08 Write Command Code
CONT08 Data
CONT09 Write Command Code
CONT09 Data
CONT0A Write Command Code
CONT0A Data
CONT0CWrite Command Code
CONT0C Data
CONT10 Write Command Code
CONT10 Data
CONT11 Write Command Code
CONT11 Data
CONT12 Write Command Code
CONT12 Data
CONT13 Write Command Code
CONT13 Data
CONT14 Write Command Code
CONT14 Data
CONT15 Write Command Code
CONT15 Data
CONT16 Write Command Code
CONT16 Data
CONT17 Write Command Code
CONT17 Data
CONT18 Write Command Code
CONT18 Data
CONT19 Write Command Code
CONT19 Data
CONT1A Write Command Code
CONT1A Data
Dummy Data0 0 (Note 58)
Dummy Data0 1
Dummy Data1 0
Dummy Data1 1
Dummy Data2 0 (Note 57)
Dummy Data2 1
014006643-E-00
2014/10
- 96 -
[AK7755]
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
•••
5031h
5032h
5033h
5034h
5035h
5036h
5037h
5038h
5039h
503Ah
503Bh
503Ch
503Dh
•••
6836h
6837h
6838h
6839h
683Ah
683Bh
683Ch
683Dh
683Eh
683Fh
6840h
•••
6899h
689Ah
689Bh
689Ch
689Dh
689Eh
689Fh
68A0h
68A1h
68A2h
68A3h
68A4h
68A5h
68A6h
68A7h
68A8h
68A9h
68AAh
B8h
00h
00h
PRAM0 DATA39-32
PRAM0 DATA31-24
PRAM0 DATA23-16
PRAM0:DATA15-8
PRAM0 DATA7-0
PRAM1 DATA39-32
PRAM1 DATA31-24
PRAM1 DATA23-16
PRAM1:DATA15-8
PRAM1 DATA7-0
PRAM2 DATA39-32
•••
PRAM4094 DATA7-0
PRAM4095 DATA39-32
PRAM4095 DATA31-24
PRAM4095 DATA23-16
PRAM4095 DATA15-8
PRAM4095 DATA7-0
B4h
00h
00h
CRAM0 DATA23-16
CRAM0 DATA15-8
CRAM0 DATA7-0
CRAM1 DATA23-16
•••
CRAM2046 DATA7-0
CRAM2047 DATA23-16
CRAM2047 DATA15-8
CRAM2047 DATA7-0
B2h
00h
00h
OFREG0 DATA23-16
OFREG0 DATA15-8
OFREG0 DATA7-0
OFREG1 DATA23-16
•••
OFREG30 DATA7-0
OFREG31 DATA23-16
OFREG31 DATA15-8
OFREG31 DATA7-0
CDh
40h
E6h
01h
EAh
80h
CEh
DATA
CFh
DATA
00h
00h
00h
00h
PRAM WRITE Command Code
PRAM Address MSB side
PRAM Address LSB side
PRAM Address0 MSB 8-bit Data
PRAM Address0 MSB-1 8-bit Data
PRAM Address0 MSB-2 8-bit Data
PRAM Address0 MSB-3 8-bit Data
PRAM Address0 LSB
8-bit Data
PRAM Address1 MSB 8-bit Data
PRAM Address1 MSB-1 8-bit Data
PRAM Address1 MSB-2 8-bit Data
PRAM Address1 MSB-3 8-bit Data
PRAM Address1 LSB 8-bit Data
PRAM Address2 MSB-1 8-bit Data
PRAM Address4094 LSB
8-bit Data
PRAM Address4095 MSB 8-bit Data
PRAM Address4095 MSB-1 8-bit Data
PRAM Address4095 MSB-2 8-bit Data
PRAM Address4095 MSB-3 8-bit Data
PRAM Address4095 LSB 8-bit Data
CRAM WRITE Command Code
CRAM Address MSB side
CRAM Address LSB side
CRAM Address0 MSB
8-bit Data
CRAM Address0 MSB-1
8-bit Data
CRAM Address0 LSB
8-bit Data
CRAM Address1 MSB
8-bit Data
CRAM Address2046 LSB
8-bit Data
CRAM Address2047 MSB
8-bit Data
CRAM Address2047 MSB-1 8-bit Data
CRAM Address2047 LSB
8-bit Data
OFREG WRITE Command Code
OFREG Address MSB side
OFREG Address LSB side
OFREG Address0 MSB
8-bit Data
OFREG Address0 MSB-1
8-bit Data
OFREG Address0 LSB
8-bit Data
OFREG Address1 MSB
8-bit Data
OFREG Address30 LSB
8-bit Data
OFREG Address31 MSB
8-bit Data
OFREG Address31 MSB-1
8-bit Data
OFREG Address31 LSB
8-bit Data
CONT0D Write Command Code
CONT0D Data
CONT26 Write Command Code
CONT26 Data
CONT2A Write Command Code
CONT2A Data
CONT0E WRITE Command Code
CONT0E Data
CONT0F WRITE Command Code
CONT0F Data
Dummy Data0_0
Dummy Data0_1
Dummy Data1_0
Dummy Data1_1
014006643-E-00
2014/10
- 97 -
[AK7755]
68ABh
68ACh
68ADh
68AEh
68AFh
68B0h
68B1h
68B2h
68B3h
68B4h
68B5h
68B6h
68B7h
68B8h
•••
7FFFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
F2h
CRC DATA15-8
CRC DATA7-0
00h
•••
00h
Dummy Data2_0
Dummy Data2_1
Dummy Data3_0
Dummy Data3_1
Dummy Data4_0
Dummy Data4_1
Dummy Data5_0
Dummy Data5_1
Dummy Data6_0
Dummy Data6_1
CRC WRITE Command Code
CRC MSB 8-bit Data
CRC LSB 8-bit Data
Reserve
Reserve
Note 57. DSPRESETN bit (CONT0F: D2) must be “0” when downloading a DSP program. Especially this
setting is necessary when changing the DSP program during operation by selecting EEPROM
mat.
Note 58. A WRITE command for arbitrary control register can be written to Dummy data *_0, and write
register setting for the control register to Dummy data*_1 in the table above.
Data transffer from EEPROM can be confirmed by writing R(x) (16-bit) data to CRCDATA (addr:
787Ch, 787Dh) which is the remainder of serial data D(x) from addres 0000h to 68B7h devided by a
generating polynominal; G(x)=x16+x12+x5+1 (Initial Value= 0).
3. EEPROM Automatic Re-downloading
When a programmed WDT or CRC error is detected, automatic re-downloading of the EEPROM data is
available up to 4 times by setting the EXPEEP pin = “H”. When an error occurs after re-downloading
more than 4 times, “L” level is output on the STO pin and the device stops. The device status can be
checked by reading STO bit (CONT0D: D7). The CRC function is enabled by setting CRCE bit
(CONT10: D6) to “1”. The default setting of CRCE bit is “0” (disabled).
This setting is initialized (error count: 0) by the PDN pin = “L”. It is not initialized by a clock reset.
4. EEPROM Mat Select
The pin number 20 becomes the MATSEL pin that enables EEPROM program mat selecting when the
EXTEEP pin = “H”.
Connect a 256K-bit EEPROM and bring the MATSEL pin = “L” when not selecting the EEPROM mat.
Connect a 1M-bit EEPROM and bring the MATSEL pin = “H” when selecting the EEPROM mat. In
this case, the pin number 14 (MAT1) and 15 (MAT0) are address pins of the mat select.
Single program is stored in every 256K bits as a program map. The EEPROM can store four programs
in total. The MAT1 and MAT0 pins select a program to download to the AK7755. OUT3E bit
(CONT0A, D2) and OUT2E bit (CONT0A, D1) must not set to “1” when selecting an EEPROM mat
(MATSEL pin = “H”).
Program No.
1
2
3
4
MAT1
(14pin)
0
0
1
1
MAT0
(15pin)
0
1
0
1
014006643-E-00
EEPROM Storing
Beginning Address
17’h00000
17’h08000
17’h10000
17’h18000
I2C 1st Byte
“1 0 1 0 0 0 0 R/Wn
“1 0 1 0 0 0 0 R/Wn
“1 0 1 0 0 0 1 R/Wn”
“1 0 1 0 0 0 1 R/Wn”
2014/10
- 98 -
[AK7755]
■ Digital Microphone Interface
1. Digital MIC Connection
Four digital microphones can be connected to the AK7755 at the maximum. When DMIC1 (CONT1E:
D7) or DMIC2 (CONT1E: D4) bit is set to “1”, the #34 pin becomes DMDAT1 (digital microphone data
input), the #33 pin becomes DMCLK1 (digital microphone clock supply) pins, the #32 pin becomes
DMDAT2 pin and the #31 pin becomes DMCLK2 pin.
The DMCLK1/2 clock is an input to a digital microphone from the AK7755. The digital microphone
outputs 1bit data, which is generated by Modulator using DMCLK1/2 clock, to the DMDAT1/2 pin.
DMIC1/2 bit controls power up/down of the digital block (Decimation Filter and Digital Filter).
DCLKE1/2 bit (CONT1E: D5/D2) controls ON/OFF of the output clock from the DMCLK1/2 pin. When
the AK7755 is powered down (PDN pin= “L”), the DMCLK1/2 and DMDAT1/2 pins become floating
state. Pull-down resistors must be connected to DMCLK and DMDAT pins externally to avoid this
floating state. Figure 76 shows a stereo 4ch connection example.
AVDD
AK7755
VDD
AMP



DMCLK1(64fs)
DMIC1 or DMIC2 bit = “1”
100k
Modulator
Decimation
Filter
DMDAT1
Lch
100k
SDOUTAD
Digital
Filter
DMIC1 bit = “1”
VDD
AMP



Modulator
Rch
VDD
AMP



DMCLK2(64fs)
DMIC1 or DMIC2 bit = “1”
100k
Modulator
DMDAT2
Lch
100k
Decimation
Filter
Digital
Filter
SDOUTAD2
DMIC2 bit = “1”
VDD
AMP



Modulator
Rch
Figure 76. Connection Example for 4ch Stereo Digital Microphone
014006643-E-00
2014/10
- 99 -
[AK7755]
2. Interface
The input data channel of the DMDAT1/2 pin is set by DCLKP1/2 bit (CONT1E: D6/D3). When
DCLKP1/2 bit = “1”, L channel data is input to the decimation filter if the DMCLK1/2 pin= “H”, and R
channel data is input if the DMCLK1/2 = “L”. When DCLKP1/2 bit = “0”, R channel data is input to the
decimation filter while DMCLK1/2 pin= “H”, and L channel data is input while DMCLK1/2 pin= “L”.
The DMCLK1/2 pin only supports 64fs. It outputs “L” when DCLKE1/2 bit = “0”, and outputs 64fs clock
when DCLKE1/2 bit = “1”. The output data through “the Decimation and Digital Filters” is 24bit full
scale when the 1bit data density is 0%~100%.
DCLKP1 bit
0
1
DMCLK1 pin = “H”
Rch
Lch
DMCLK1 pin = “L”
Lch
(default)
Rch
DCLKP2 bit DMCLK2 pin = “H” DMCLK2 pin = “L”
0
Rch
Lch
(default)
1
Lch
Rch
Table 13. Data Input/Output Timing with Digital MIC
DMCLK1/2(64fs)
DMDAT1/2(Lch)
Valid
Data
Valid
Data
Valid
Data
DMDAT1/2(Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 77. Data Input/Output Timing with Digital MIC (DCLKP1/2 bit = “1”)
DMCLK1/2(64fs)
DMDAT1/2(Lch)
DMDAT1/2(Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 78. Data Input/Output Timing with Digital MIC (DCLKP1/2 bit = “0”)
■ Digital Mixer
ADC output (SDATAD), ADC2 output (SDATAD2) and DSP-DOUT4 data can be mixed into a signle
serial data by a mixer circuit. SELMIX[2:0] bits (CONT09: D0, CONT08: D1, D0) control mixing
setting. Delay time of the mixer circuit is 4Ts (4/fs).
SELMIX SELMIX
MIXOUT Lch
MIXOUT Rch
mode
[2:0]
0
000
SDOUTAD Lch
SDOUTAD Rch
SDOUTAD Lch/2 + SDOUTAD2 Lch/2 SDOUTAD Rch
1
001
SDOUTAD Lch/2 + SDOUTAD2 Lch/2
2
010
SDOUTAD Lch
SDOUTAD2 Lch
3
011
SDOUTAD2 Rch
4
100
DSP-DOUT4 Lch
SDOUTAD2 Rch
5
101
SDOUTAD2 Lch
DSP-DOUT4 Rch
6
110
DSP-DOUT4 Lch
SDOUTAD Rch
7
111
SDOUTAD Lch
DSP-DOUT4 Rch
Table 14. Digital Mixer Output Setting
014006643-E-00
(default)
2014/10
- 100 -
[AK7755]
10. Recommended External Circuits
■ Connection Diagram
1. I2CSEL pin = “L”, LDOE pin = “L”
I2CSEL
CLOCK
&
Audio I/F
9
8
7
16
15
14
5
4
LDOE
CLKO
BICK
LRCK
SDOUT1
SDOUT2
SDOUT3
SDIN1
SDIN2
CSN
SI
SCLK
SO
STO/RDY
PDN
1
31
1
32
1
33
1
34
1
35
IN4/INN2
OUT1
IN3/INP2
OUT2
IN2/INN1
OUT3
IN1/INP1
3
“L”
23
“L”
20
19
uP
18
17
6
22
RESET
CONTROL
28
1
26
1
27
1
LIN
AK7755
VCOM
1
2.2
Digital Core 1.2V
24
10
DVDD
0.1
Digital IO 1.8～3.3V
10
12
AVDD
TVDD
Analog +3.3V
21,29,36
10
0.1
0.1
AVSS
13,25
2,30
DVSS
XTO
XTI
Rd
10
CL=22pF/15pF
11
CL=22pF/15pF
Figure 79. Serial Interface Connection with External Power Supply
2. I2CSEL pin = “L”, LDOE pin = “H”
I2CSEL
CLOCK
&
Audio I/F
9
8
7
16
15
14
5
4
LDOE
CLKO
BICK
LRCK
SDOUT1
SDOUT2
SDOUT3
SDIN1
SDIN2
CSN
SI
SCLK
SO
STO/RDY
PDN
1
31
1
32
1
33
1
34
1
35
IN4/INN2
OUT1
IN3/INP2
OUT2
IN2/INN1
OUT3
IN1/INP1
3
“L”
23
“H”
20
19
uP
18
17
6
22
RESET
CONTROL
28
1
26
1
27
1
LIN
AK7755
VCOM
1
2.2
24
AVDRV
1
Digital IO 1.8～3.3V
10
12
AVDD
TVDD
Analog +3.3V
21,29,36
10
0.1
0.1
AVSS
13,25
2,30
DVSS
XTO
XTI
10
Rd
CL=22pF/15pF
11
CL=22pF/15pF
Figure 80. Serial Interface Connection with Internal LDO
014006643-E-00
2014/10
- 101 -
[AK7755]
3. I2CSEL pin = “H”, EXTEEP pin = “L”, LDOE pin = “L”
I2CSEL
CLOCK
&
Audio I/F
9
8
7
16
15
14
5
4
LDOE
CLKO
BICK
LRCK
SDOUT1
SDOUT2
SDOUT3
SDIN1
SDIN2
1
31
1
32
1
33
1
34
1
35
EXTEEP
CAD
SCL
SDA
STO/RDY
PDN
IN4/INN2
3
“H”
23
“L”
19
“L”
20
uP
18
17
6
22
RESET
CONTROL
IN3/INP2
IN2/INN1
OUT1
IN1/INP1
OUT2
LIN
OUT3
AK7755
VCOM
28
1
26
1
27
1
1
2.2
Digital Core 1.2V
24
10
DVDD
0.1
Digital IO 1.8～3.3V
10
12
AVDD
TVDD
Analog +3.3V
21,29,36
10
0.1
0.1
AVSS
13,25
2,30
DVSS
XTO
XTI
Rd
10
CL=22pF/15pF
11
CL=22pF/15pF
Figure 81. I2C Interface Connection with External Power Supply
4. I2CSEL pin = “H”, EXTEEP pin = “L”, LDOE pin = “H”
I2CSEL
CLOCK
&
Audio I/F
9
8
7
16
15
14
5
4
LDOE
CLKO
BICK
LRCK
SDOUT1
SDOUT2
SDOUT3
SDIN1
SDIN2
1
31
1
32
1
33
1
34
1
35
EXTEEP
CAD
SCL
SDA
STO/RDY
PDN
IN4/INN2
3
“H”
23
“H”
19
“L”
20
uP
18
17
6
22
RESET
CONTROL
IN3/INP2
IN2/INN1
OUT1
IN1/INP1
OUT2
LIN
OUT3
AK7755
VCOM
28
1
26
1
27
1
1
2.2
24
AVDRV
1
Digital IO 1.8～3.3V
10
12
AVDD
TVDD
Analog +3.3V
21,29,36
10
0.1
0.1
AVSS
13,25
2,30
DVSS
XTO
XTI
10
Rd
CL=22pF/15pF
11
CL=22pF/15pF
Figure 82. I2C Interface Connection with Internal LDO
014006643-E-00
2014/10
- 102 -
[AK7755]
5. I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “L”, LDOE pin = “L”
I2CSEL
CLOCK
&
Audio I/F
9
8
7
16
15
14
5
4
LDOE
CLKO
BICK
LRCK
SDOUT1
SDOUT2
SDOUT3
SDIN1
SDIN2
EXTEEP
MATSEL
SCL
SDA
STO/RDY
1
31
1
32
1
33
1
34
1
35
IN4/INN2
PDN
3
“H”
23
“L”
19
20
“H”
“L”
uP
18
EEPROM
256Kbit
17
6
22
RESET
CONTROL
IN3/INP2
IN2/INN1
OUT1
IN1/INP1
OUT2
LIN
AK7755
OUT3
VCOM
28
1
26
1
27
1
1
2.2
Digital Core 1.2V
24
10
DVDD
0.1
Digital IO 1.8～3.3V
10
12
AVDD
TVDD
Analog +3.3V
21,29,36
10
0.1
0.1
AVSS
13,25
2,30
DVSS
XTO
XTI
Rd
10
CL=22pF/15pF
11
CL=22pF/15pF
Figure 83. I2C Interface Connection with External Power Supply and EEPROM
6. I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “L”, LDOE pin = “H”
I2CSEL
CLOCK
&
Audio I/F
9
8
7
16
15
14
5
4
LDOE
CLKO
BICK
LRCK
SDOUT1
SDOUT2
SDOUT3
SDIN1
SDIN2
EXTEEP
MATSEL
SCL
SDA
STO/RDY
1
31
1
32
1
33
1
34
1
35
IN4/INN2
PDN
3
“H”
23
“H”
19
20
“H”
“L”
uP
18
EEPROM
256Kbit
17
6
22
RESET
CONTROL
IN3/INP2
IN2/INN1
OUT1
IN1/INP1
OUT2
LIN
AK7755
OUT3
VCOM
28
1
26
1
27
1
1
2.2
24
AVDRV
1
Digital IO 1.8～3.3V
10
12
AVDD
TVDD
Analog +3.3V
21,29,36
10
0.1
0.1
AVSS
13,25
2,30
DVSS
XTO
XTI
10
Rd
CL=22pF/15pF
11
CL=22pF/15pF
Figure 84. I2C Interface Connection with Internal LDO and EEPROM
014006643-E-00
2014/10
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[AK7755]
7. I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “H”, LDOE pin = “L”
I2CSEL
CLOCK
&
Audio I/F
9
8
7
16
LDOE
CLKO
BICK
LRCK
SDOUT1
5
4
EXTEEP
MATSEL
SDIN1
SDIN2
SCL
SDA
STO/RDY
MAT0
1
31
1
32
1
33
1
34
1
35
MAT1
IN4/INN2
PDN
IN3/INP2
IN2/INN1
OUT1
IN1/INP1
OUT2
LIN
AK7755
OUT3
VCOM
3
“H”
23
“L”
19
20
“H”
“H”
uP
18
EEPROM
1Mbit
17
6
15
14
RESET
CONTROL
22
28
1
26
1
27
1
1
2.2
Digital Core 1.2V
24
10
DVDD
0.1
Digital IO 1.8～3.3V
10
12
AVDD
TVDD
Analog +3.3V
21,29,36
10
0.1
0.1
AVSS
13,25
2,30
DVSS
XTO
XTI
Rd
10
CL=22pF/15pF
11
CL=22pF/15pF
Figure 85. I2C Interface Connection with External Power Supply and EEPROM (Mat Select ON)
8. I2CSEL pin = “H”, EXTEEP pin = “H”, MATSEL pin = “H”, LDOE pin = “H”
I2CSEL
CLOCK
&
Audio I/F
9
8
7
16
LDOE
CLKO
BICK
LRCK
SDOUT1
5
4
EXTEEP
MATSEL
SDIN1
SDIN2
SCL
SDA
STO/RDY
MAT0
1
31
1
32
1
33
1
34
1
35
MAT1
IN4/INN2
PDN
IN3/INP2
IN2/INN1
OUT1
IN1/INP1
OUT2
LIN
AK7755
OUT3
VCOM
3
“H”
23
“H”
19
20
“H”
“H”
uP
18
EEPROM
1Mbit
17
6
15
14
22
RESET
CONTROL
28
1
26
1
27
1
1
2.2
24
AVDRV
1
Digital IO 1.8～3.3V
10
12
AVDD
TVDD
Analog +3.3V
21,29,36
10
0.1
0.1
AVSS
13,25
2,30
DVSS
XTO
XTI
10
Rd
CL=22pF/15pF
11
CL=22pF/15pF
Figure 86. I2C Interface Connection with Internal LDO and EEPROM (Mat Select ON)
014006643-E-00
2014/10
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[AK7755]
■ Peripheral Circuit
1. Ground
AVSS and DVSS must be connected to the same analog ground plane. Decoupling capacitors,
particularly small capacity capacitors, should be connected as close as possible to the AK7755.
2. Reference Voltage
The AVDD voltage controls analog signal range. VCOM is a common voltage of this chip and the
VCOM pin outputs AVDD/2. A 2.2µF ceramic capacitor connected between the VCOM and AVSS pins
eliminates the effects of high frequency noise. The ceramic capacitor should be connected as close as
possible to the VCOM pin. The VCOM pin must not be connected to external circuits. Digital signal
lines, especially clock signal line should be kept away as far as possible from the VCOM pin in order to
avoid unwanted coupling into the AK7755.
3. Analog Input
Analog input signals are applied to the modulator through the input pin of each channel. Input voltage is
±FS = ±(AVDD-AVSS) x 2.2/3.3 for differential pin and FS = (AVDD-AVSS) x 2.2/3.3 for single-end
pin. When AVDD = 3.3V and AVSS=0.0V, the differential input range is ±2.20Vpp (typ) and it is
2.20Vpp (typ) for single-ended input. The digital output code format is 2's complements. DC offset can
be cancelled by an internal HPF.
The AK7755 samples the analog inputs in 3.072MHz at fs = 48kHz. The digital filter removes noise in
the range from 30kHz to 3.042MHz. The AK7755 includes an anti-aliasing filter (RC filter) to attenuate
a noise around the range from 3.042MHz to 3.072MHz witch is not removed by the HPF. An external
Low Pass Filter is not necessary since most of audio signals do not have large noise in the band around
3.072MHz. However, it is recommended to connect a Low Pass Filter before the ADC when a signal
with large out-of-band noises is input.
The analog source voltage to the AK7755 is +3.3V (typ). Voltage of AVDD + 0.3V or more, voltage of
AVSS – 0.3V or less, and current of 10mA or more must not be applied to analog input pins. Excessive
current will damage the internal protection circuit and will cause latch-up, damaging the IC. If the
external analog circuit voltage is ±15V, the analog input pins must be protected from signals which are in
absolute maximum rating level or more.
10k
Signal
22μ
+
10k
68p
10k
+
10k
68p
+
2.20Vpp
+
INP*
1μ
+
1μ
INN*
2.20Vpp
Figure 87. Input Buffer Circuit Example (Differential Input)
014006643-E-00
2014/10
- 105 -
[AK7755]
4. Analog Output
The analog line-outputs are single-ended. The output signal range is 0.76 × AVDD Vpp (typ.) centered
around VCOM voltage. The input code format is in 2’s complement. The output voltage is a positive full
scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal voltage at 000000H
is VCOM. The VCOM voltage is AVDD/2 (typ). The internal switched-capacitor filter (SCF) and
continuous-time filter (CTF) attenuate the noise generated by the delta-sigma modulator beyond the audio
passband.
5. Connection to Digital Circuit
To minimize the noise from digital circuits, the digital output of the AK7755 must be connected to CMOS
or low voltage logic ICs such as 74HC and 74AC for CMOS and 74LV, 74LV-A, 74ALVC and 74AVC for
low voltage logic ICs.
6. Cristal Oscillator
The resistor and capacitor values for the oscillator RC circuit are shown blow.
TVDD = 3.0 - 3.6V
CKM mode
0
1
XTAL
Oscillator
12.288MHz
18.432MHz
R1_max
C0_max
120Ω
80Ω
2.5pF
2.5pF
R1_max
C0_max
50Ω
25Ω
1.2pF
1.2pF
XTI, XTO pin
Connection Capacity
22pF
15pF
TVDD = 1.7 - 3.0V
CKM mode
0
1
XTAL
Oscillator
12.288MHz
18.432MHz
XTI, XTO pin
Connection Capacity
10pF
10pF
Table 15. Crystal Oscillator
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2014/10
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[AK7755]
11. Package
■ Outline Dimensions
■ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
014006643-E-00
2014/10
- 107 -
[AK7755]
■ Marking
AKM
7755EN
XXXX
36
1
1) Pin #1 indication
2) Date Code: XXXX(4 digits)
3) Marking Code: 7755EN
AKM
7755VN
XXXX
36
1
1) Pin #1 indication
2) Date Code: XXXX(4 digits)
3) Marking Code: 7755VN
014006643-E-00
2014/10
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[AK7755]
12. Revision History
Date (Y/M/D) Revision
14/10/20
00
Reason
Page
First Edition
Contents
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants
any license to any intellectual property rights or any other rights of AKM or any third party with
respect to the information in this document. You are fully responsible for use of such information
contained in this document in your product design or applications. AKM ASSUMES NO
LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which
may cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace
industry, medical equipment, equipment used for automobiles, trains, ships and other
transportation, traffic signaling equipment, equipment used to control combustions or explosions,
safety devices, elevators and escalators, devices related to electric power, and equipment used in
finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in
writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and safeguards
for your hardware, software and systems which minimize risk and avoid situations in which a
malfunction or failure of the Product could cause loss of human life, bodily injury or damage to
property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and
regulations. The Products and related technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or
foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
014006643-E-00
2014/10
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