GT3200
(64-PIN TQFP PACKAGES)
USB3250
(56-PIN QFN PACKAGE)
USB2.0 PHY IC
PRODUCT FEATURES
Datasheet
USB-IF "Hi-Speed" certified to USB2.0 electrical
specification
Interface compliant with the UTMI specification
(60MHz 8-bit unidirectional interface or 30MHz 16-bit
bidirectional interface)
Supports 480Mbps High Speed (HS) and 12Mbps
Full Speed (FS) serial data transmission rates
Integrated 45Ω and 1.5kΩ termination resistors
reduce external component count
Internal short circuit protection of DP and DM lines
On-chip oscillator operates with low cost 12MHz
crystal
Robust and low power digital clock and data recovery
circuit
SYNC and EOP generation on transmit packets and
detection on receive packets
SMSC GT3200, SMSC USB3250
NRZI encoding and decoding
Bit stuffing and unstuffing with error detection
Supports the USB suspend state, HS detection, HS
Chirp, Reset and Resume
Support for all test modes defined in the USB2.0
specification
Draws 72mA (185mW) maximum current
consumption in HS mode - ideal for bus powered
functions
On-die decoupling capacitance and isolation for
immunity to digital switching noise
Available in three 64-pin TQFP packages (GT3200)
or a 56-pin QFN package (USB3250)
Full industrial operating temperature range from
-40oC to +85oC (ambient)
DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
ORDER NUMBER(S):
GT3200-JD FOR 64 PIN 10 X 10 X 1.4MM TQFP PACKAGE
GT3200-JN FOR 64 PIN 7 X 7 X 1.4MM TQFP PACKAGE
GT3200-JV FOR 64 PIN 7 X 7 X 1.4MM TQFP PACKAGE (GREEN, LEAD-FREE)
USB3250-ABZJ FOR 56 PIN 8 X 8 X 0.85MM QFN PACKAGE (GREEN, LEAD-FREE)
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © 2006 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently,
complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be
accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any
time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this
information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual
property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may
contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other
application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written
approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other
SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a
registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective
holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE,
AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE
LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA,
PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT;
NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY
OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
Revision 1.5 (03-24-06)
2
DATASHEET
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 4 Interface Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 5 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
6.2
Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers . . . . . . . . . . . . 18
High-speed Signaling Eye Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 7 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and Data Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FS/HS RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FS/HS TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
24
25
26
27
31
31
31
31
Chapter 8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
Linestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HS Detection Handshake - FS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HS Detection Handshake - HS Downstream Facing Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HS Detection Handshake - Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
33
33
33
34
34
35
36
38
40
42
43
43
45
Chapter 9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SMSC GT3200, SMSC USB3250
3
DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
List of Figures
Figure 2.1
Figure 3.1
Figure 3.2
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
Figure 7.5
Figure 7.6
Figure 7.7
Figure 7.8
Figure 7.9
Figure 7.10
Figure 7.11
Figure 7.12
Figure 8.1
Figure 8.2
Figure 8.3
Figure 8.4
Figure 8.5
Figure 8.6
Figure 8.7
Figure 8.8
Figure 8.9
Figure 8.10
Figure 9.1
Figure 9.2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
64 pin GT3200 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
56 pin USB3250 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver . . . . . . . . 18
Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver. . . . . . . . . 19
Eye Pattern Measurement Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . 21
Eye Pattern for Receive Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . . 22
Bidirectional 16-bit interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
FS CLK Relationship to Transmit Data and Control Signals (8-bit mode) . . . . . . . . . . . . . . . 25
FS CLK Relationship to Receive Data and Control Signals (8-bit mode) . . . . . . . . . . . . . . . 25
Transmit Timing for a Data Packet (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Transmit Timing for 16-bit Data, Even Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Transmit Timing for 16-bit Data, Odd Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Receive Timing for Data with Unstuffed Bits (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Receive Timing for 16-bit Data, Even Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Receive Timing for 16-bit Data, Odd Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Receive Timing for Data (with CRC-16 in 8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Receive Timing for Setup Packet (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Receive Timing for Data Packet with CRC-16 (8-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Application Diagram for 64-pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Application Diagram for 56-pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
GT3200 TQFP Package Outline and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
USB3250 QFN Package Outline and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision 1.5 (03-24-06)
4
DATASHEET
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
List of Tables
Table 4.1 System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.2 Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.3 USB I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.4 Biasing and Clock Oscillator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.5 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.1 Electrical Characteristics: Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.2 DC Electrical Characteristics: Logic Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.5 Dynamic Characteristics: Digital UTMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.6 Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . .
Table 6.7 Eye Pattern for Receive Waveform and Eye Pattern Definition. . . . . . . . . . . . . . . . . . . . . . . .
Table 8.1 Linestate States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.3 USB2.0 Test Mode to Macrocell Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.8 HS Detection Handshake Timing Values from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMSC GT3200, SMSC USB3250
5
DATASHEET
10
11
12
12
12
13
13
13
14
15
15
16
17
21
22
32
33
33
34
35
37
39
41
42
44
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
Chapter 1 General Description
The GT3200 and USB3250 provide the Physical Layer (PHY) interface to a USB2.0 Device Controller.
The IC is available in a 64 pin lead TQFP (GT3200) or a 56 pin QFN (USB3250).
1.1
Applications
The Universal Serial Bus (USB) is the preferred interface to connect high-speed PC peripherals.
1.2
Scanners
Printers
External Storage and System Backup
Still and Video Cameras
PDAs
CD-RW
Gaming Devices
Product Description
The GT3200 and USB3250 are USB2.0 physical layer transceiver (PHY) integrated circuits. SMSC's
proprietary technology results in low power dissipation, which is ideal for building a bus powered
USB2.0 peripheral. The PHY can be configured for either an 8-bit unidirectional or a 16-bit
bidirectional parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI)
specification. It supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1
legacy protocol at 12Mbps.
All required termination for the USB2.0 Transceiver is internal. Internal 5.25V short circuit protection of
DP and DM lines is provided for USB compliance.
While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs
needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming
data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.
Revision 1.5 (03-24-06)
6
DATASHEET
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
Chapter 2 Functional Block Diagram
XO
XI
VDD1.8
VDD3.3
PWR
CONTROL
PLL and
XTAL OSC
TX
LOGIC
TX
RPU_EN
1.5kΩ
TX State
Machine
VPO
VMO
Parallel to
Serial
Conversion
DATABUS16_8
RESET
SUSPENDN
Bit Stuff
XCVRSELECT
NRZI
Encode
System
Clocking
FS TX
OEB
HS_DATA
HS_DRIVE_ENABLE
HS_CS_ENABLE
HS TX
TERMSELECT
DP
OPMODE[1:0]
RX
DATA[15:0] *
TXVALID
TXREADY
VALIDH
RX
LOGIC
FS SE+
VP
VM
RX State
Machine
Serial to
Parallel
Conversion
FS SE-
Clock
Recovery Unit
Clock
and
Data
Recovery
Bit Unstuff
RXVALID
RXACTIVE
DM
NRZI
Decode
Elasticity
Buffer
RXERROR
FS RX
MUX
CLKOUT
UTMI Interface
LINESTATE[1:0]
HS RX
BIASING
Bandgap Voltage Reference
HS SQ
RBIAS
Current Reference
Figure 2.1 Block Diagram
Note: See Section 7.1, "Modes of Operation," on page 23 for a description of the digital interface.
SMSC GT3200, SMSC USB3250
7
DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
DATABUS16_8
VDD1.8
RXERROR
TXREADY
RXACTIVE
CLKOUT
VSS
VALIDH
RXVALID
TXVALID
DATA[0]
VDD3.3
60
59
58
57
56
55
54
53
52
51
50
49
VSS
62
VSS
VSS
63
61
VSS
64
Chapter 3 Pinout
NC
1
48
VSS
VSSA
2
47
DATA[1]
NC
46
DATA[2]
DM
3
4
45
DATA[3]
DP
5
44
DATA[4]
VDDA3.3
6
43
VDD1.8
VSSA
7
RBIAS
8
VDDA3.3
9
USB2.0
GT3200
PHY IC
42
DATA[5]
41
DATA[6]
40
DATA[7]
VSSA
10
39
DATA[8]
XI
11
38
VSS
XO
12
37
DATA[9]
VDDA1.8
13
36
DATA[10]
26
27
28
29
30
31
32
RESET
DATA[15]
DATA[14]
DATA[13]
VDD3.3
24
OPMODE[0]
VDD1.8
23
OPMODE[1]
LINESTATE[0]
22
VSS
25
21
TERMSELECT
LINESTATE[1]
20
VSS
19
33
VDD1.8
16
XCVRSELECT
DATA[12]
VSS
18
DATA[11]
34
VDD3.3
35
15
17
14
VSS
NC
SUSPENDN
Figure 3.1 64 pin GT3200 Pinout
Revision 1.5 (03-24-06)
8
DATASHEET
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
VALIDH
RXVALID
TXVALID
DATA[0]
VDD3.3
45
44
43
RXACTIVE
50
46
TXREADY
51
47
RXERROR
52
CLKOUT
VDD1.8
53
VSS
DATABUS16_8
54
48
VSS
55
49
VSS
56
Datasheet
1
42
DATA[1]
2
41
DATA[2]
DP
3
40
DATA[3]
VDDA3.3
4
39
DATA[4]
38
VDD1.8
37
DATA[5]
36
DATA[6]
35
DATA[7]
9
34
DATA[8]
10
33
VSS
XO
11
32
DATA[9]
VDDA1.8
12
31
DATA[10]
13
30
DATA[11]
14
29
DATA[12]
19
20
21
22
23
24
25
26
27
28
OPMODE[0]
LINESTATE[1]
LINESTATE[0]
VDD1.8
RESET
DATA[15]
DATA[14]
DATA[13]
VDD3.3
VSS
OPMODE[1]
SUSPENDN
18
XI
TERMSELECT
VSSA
8
17
VSSA
7
XCVRSELECT
VDDA3.3
6
16
RBIAS
5
VDD1.8
VSSA
USB2.0
USB3250
PHY IC
15
DM
VDD3.3
VSSA
Figure 3.2 56 pin USB3250 Pinout
SMSC GT3200, SMSC USB3250
9
DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
Chapter 4 Interface Signal Definition
Table 4.1 System Interface Signals
DIRECTION
ACTIVE
LEVEL
RESET
Input
High
Reset. Reset all state machines. After coming out of reset, must
wait 5 rising edges of clock before asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to CLKOUT
De-assertion of Reset: Must be synchronous to CLKOUT
XCVRSELECT
Input
N/A
Transceiver Select. This signal selects between the FS and HS
transceivers:
0: HS transceiver enabled
1: FS transceiver enabled.
TERMSELECT
Input
N/A
Termination Select. This signal selects between the FS and HS
terminations:
0: HS termination enabled
1: FS termination enabled
SUSPENDN
Input
Low
Suspend. Places the transceiver in a mode that draws minimal
power from supplies. Shuts down all blocks not necessary for
Suspend/Resume operation. While suspended, TERMSELECT
must always be in FS mode to ensure that the 1.5k Ω pull-up on
DP remains powered.
0: Transceiver circuitry drawing suspend current
1: Transceiver circuitry drawing normal current
Output
Rising Edge
System Clock. This output is used for clocking receive and
transmit parallel data at 60MHz (8-bit mode) or 30MHz (16-bit
mode). When in 8-bit mode, this specification refers to CLKOUT
as CLK60. When in 16-bit mode, CLKOUT is referred to as
CLK30.
Input
N/A
Operational Mode. These signals select between the various
operational modes:
[1] [0] Description
0
0
0: Normal Operation
0
1
1: Non-driving (all terminations removed)
1
0
2: Disable bit stuffing and NRZI encoding
1
1
3: Reserved
LINESTATE[1:0]
Output
N/A
Line State. These signals reflect the current state of the USB
data bus in FS mode, with [0] reflecting the state of DP and [1]
reflecting the state of DM. When the device is suspended or
resuming from a suspended state, the signals are combinatorial.
Otherwise, the signals are synchronized to CLKOUT.
[1] [0] Description
0
0
0: SE0
0
1
1: J State
1
0
2: K State
1
1
3: SE1
DATABUS16_8
Input
N/A
Databus Select. Selects between 8-bit and 16-bit data transfers.
0: 8-bit data path enabled. VALIDH is undefined. CLKOUT =
60MHz.
1: 16-bit data path enabled. CLKOUT = 30MHz.
NAME
CLKOUT
OPMODE[1:0]
Revision 1.5 (03-24-06)
DESCRIPTION
10
DATASHEET
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
Table 4.2 Data Interface Signals
NAME
DATA[15:0]
DIRECTION
ACTIVE
LEVEL
DESCRIPTION
Bidir
N/A
DATA BUS. 16-BIT BIDIRECTIONAL MODE.
TXVALID
RXVALID
VALIDH
DATA[15:0]
0
0
X
Not used
0
1
0
DATA[7:0] output is valid
for receive
VALIDH is an output
0
1
1
DATA[15:0] output is
valid for receive
VALIDH is an output
1
X
0
DATA[7:0] input is valid
for transmit
VALIDH is an input
1
X
1
DATA[15:0] input is valid
for transmit
VALIDH is an input
DATA BUS. 8-BIT UNIDIRECTIONAL MODE.
TXVALID
Input
High
TXVALID
RXVALID
DATA[15:0]
0
0
Not used
0
1
DATA[15:8] output is valid for receive
1
X
DATA[7:0] input is valid for transmit
Transmit Valid. Indicates that the TXDATA bus is valid for
transmit. The assertion of TXVALID initiates the transmission of
SYNC on the USB bus. The negation of TXVALID initiates EOP
on the USB.
Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT)
must not be changed on the de-assertion or assertion of TXVALID.
The PHY must be in a quiescent state when these inputs are
changed.
TXREADY
VALIDH
Output
High
Transmit Data Ready. If TXVALID is asserted, the SIE must
always have data available for clocking into the TX Holding
Register on the rising edge of CLKOUT. TXREADY is an
acknowledgement to the SIE that the transceiver has clocked the
data from the bus and is ready for the next transfer on the bus. If
TXVALID is negated, TXREADY can be ignored by the SIE.
Bidir
N/A
Transmit/Receive High Data Bit Valid (used in 16-bit mode
only). When TXVALID = 1, the 16-bit data bus direction is
changed to inputs, and VALIDH is an input. If VALIDH is asserted,
DATA[15:0] is valid for transmission. If deasserted, only DATA[7:0]
is valid for transmission. The DATA bus is driven by the SIE.
When TXVALID = 0 and RXVALID = 1, the 16-bit data bus
direction is changed to outputs, and VALIDH is an output. If
VALIDH is asserted, the DATA[15:0] outputs are valid for receive.
If deasseted, only DATA[7:0] is valid for receive. The DATA bus
is read by the SIE.
RXVALID
Output
High
Receive Data Valid. Indicates that the RXDATA bus has received
valid data. The Receive Data Holding Register is full and ready to
be unloaded. The SIE is expected to latch the RXDATA bus on the
rising edge of CLKOUT.
RXACTIVE
Output
High
Receive Active. Indicates that the receive state machine has
detected Start of Packet and is active.
RXERROR
Output
High
Receive Error. 0: Indicates no error. 1: Indicates a receive error
has been detected. This output is clocked with the same timing as
the RXDATA lines and can occur at anytime during a transfer.
SMSC GT3200, SMSC USB3250
11
DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
Table 4.3 USB I/O Signals
DIRECTION
ACTIVE
LEVEL
DP
I/O
N/A
USB Positive Data Pin.
DM
I/O
N/A
USB Negative Data Pin.
NAME
DESCRIPTION
Table 4.4 Biasing and Clock Oscillator Signals
DIRECTION
ACTIVE
LEVEL
RBIAS
Input
N/A
External 1% bias resistor. Requires a 12KΩ resistor to ground.
Used for setting HS transmit current level and on-chip termination
impedance.
XI/XO
Input
N/A
External crystal. 12MHz crystal connected from XI to XO.
NAME
DESCRIPTION
Table 4.5 Power and Ground Signals
NAME
DIRECTION
ACTIVE
LEVEL
DESCRIPTION
VDD3.3
N/A
N/A
3.3V Digital Supply. Powers digital pads. See Note 4.1
VDD1.8
N/A
N/A
1.8V Digital Supply. Powers digital core.
VSS
N/A
N/A
Digital Ground. See Note 4.2
VDDA3.3
N/A
N/A
3.3V Analog Supply. Powers analog I/O and 3.3V analog
circuitry.
VDDA1.8
N/A
N/A
1.8V Analog Supply. Powers 1.8V analog circuitry. See Note 4.1
VSSA
N/A
N/A
Analog Ground. See Note 4.2
Note 4.1
A Ferrite Bead (with DC resistance <.5 Ohms) is recommended for filtering between both
the VDD3.3 and VDDA3.3 supplies and the VDD1.8 and VDDA1.8 Supplies. See
Figure 8.9 Application Diagram for 64-pin TQFP Package on page 45.
Note 4.2
56-pin QFN package will down-bond all VSS and VSSA to exposed pad under IC.
Exposed pad must be connected to solid GND plane on printed circuit board.
Revision 1.5 (03-24-06)
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SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
Chapter 5 Limiting Values
Table 5.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.8V Supply Voltage
(VDD1.8 and VDDA1.8)
VDD1.8
-0.5
TBD
V
3.3V Supply Voltage
(VDD3.3 and VDDA3.3)
VDD3.3
-0.5
4.6
V
VI
-0.5
4.6
Input Voltage
Storage Temperature
-40
TSTG
+125
V
o
C
[1] Equivalent to discharging a 100pF capacitor via a 1.5kΩ resistor (HBM).
Note: In accordance with the Absolute Maximum Rating System (IEC 60134
Table 5.2 Recommended Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.8V Supply Voltage
(VDD1.8 and VDDA1.8)
VDD1.8
1.6
1.8
2.0
V
3.3V Supply Voltage
(VDD3.3 and VDDA3.3)
VDD3.3
3.0
3.3
3.6
V
Input Voltage on Digital Pins
VI
0.0
VDD3.3
V
Input Voltage on Analog I/O
Pins (DP, DM)
VI(I/O)
0.0
VDD3.3
V
TA
-40
+85
oC
MAX
UNITS
Ambient Temperature
Table 5.3 Recommended External Clock Conditions
PARAMETER
SYMBOL
CONDITIONS
System Clock Frequency
XO driven by the
external clock; and no
connection at XI
System Clock Duty Cycle
XO driven by the
external clock; and no
connection at XI
SMSC GT3200, SMSC USB3250
13
DATASHEET
MIN
TYP
12
(+/- 100ppm)
45
50
MHz
55
%
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
Chapter 6 Electrical Characteristics
Table 6.1 Electrical Characteristics: Supply Pins
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
UNITS
86
115
mW
57
76
mW
29
39
mW
Total Power
PTOT(FSTX)
FS
TRANSMIT
VDD3.3
Power
P3.3V(FSTX)
VDD1.8
Power
P1.8V(FSTX)
Total Power
PTOT(FSRX)
75
115
mW
FS RECEIVE
VDD3.3
Power
P3.3V(FSRX)
46
76
mW
VDD1.8
Power
P1.8V(FSRX)
29
39
mW
Total Power
PTOT(HSTX)
158
185
mW
VDD3.3
Power
P3.3V (HSTX)
110
130
mW
VDD1.8
Power
P1.8V (HSTX)
48
55
mW
Total Power
PTOT(HSRX)
155
185
mW
VDD3.3
Power
P3.3V (HSRX)
107
130
mW
VDD1.8
Power
P1.8V (HSRX)
48
55
mW
Total Current
IDD(SUSP1)
123
240
uA
VDD3.3
Current
I3.3V (SUSP1)
68
120
uA
VDD1.8
Current
I1.8V (SUSP1)
55
120
uA
HS
TRANSMIT
HS RECEIVE
SUSPEND
MODE 1
SUSPEND
MODE 2
Total Current
IDD(SUSP2)
VDD3.3
Current
I3.3V (SUSP2)
VDD1.8
Current
I1.8V (SUSP2)
FS transmitting at 12Mb/s;
50pF load on DP and DM
MIN
FS receiving at 12Mb/s
HS transmitting into a 45Ω
load
HS receiving at 480Mb/s
15kΩ pull-down and 1.5kΩ
pull-up resistor on pin DP
not connected.
15kΩ pull-down and 1.5kΩ
pull-up resistor on pin DP
connected.
323
460
uA
268
340
uA
55
120
uA
(VDD1.8 =1.6 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.)
Revision 1.5 (03-24-06)
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SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
Table 6.2 DC Electrical Characteristics: Logic Pins
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Low-Level Input Voltage
VIL
VSS
0.8
V
High-Level Input Voltage
VIH
2.0
VDD3.3
V
Low-Level Output Voltage
VOL
IOL = 4mA
0.4
V
High-Level Output Voltage
VOH
IOH = -4mA
Input Leakage Current
Pin Capacitance
VDD3.3
- 0.5
V
ILI
±1
uA
Cpin
4
pF
(VDD1.8 =1.6 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.
Pins Data[15:0] and VALIDH have passive pull-down elements.)
Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FS FUNCTIONALITY
INPUT LEVELS
| V(DP) - V(DM) |
0.2
Differential Receiver Input
Sensitivity
VDIFS
Differential Receiver
Common-Mode Voltage
VCMFS
Single-Ended Receiver Low
Level Input Voltage
VILSE
Single-Ended Receiver High
Level Input Voltage
VIHSE
2.0
VHYSSE
0.050
Single-Ended Receiver
Hysteresis
V
0.8
2.5
V
0.8
V
V
0.150
V
0.3
V
3.6
V
49.5
Ω
OUTPUT LEVELS
Low Level Output Voltage
VFSOL
Pull-up resistor on DP;
RL = 1.5kΩ to VDD3.3
High Level Output Voltage
VFSOH
Pull-down resistor on
DP, DM;
RL = 15kΩ to GND
2.8
ZHSDRV
Steady state drive (See
Figure 6.1)
40.5
TERMINATION
Driver Output Impedance for
HS and FS
TX, RPU disabled
45
10
MΩ
Input Impedance
ZINP
Pull-up Resistor Impedance
ZPU
1.425
1.575
KΩ
VTERM
3.0
3.6
V
Termination Voltage For Pullup Resistor On Pin DP
HS FUNCTIONALITY
INPUT LEVELS
HS Differential Input
Sensitivity
VDIHS
| V(DP) - V(DM) |
100
mV
(VDD1.8 =1.6 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.)
SMSC GT3200, SMSC USB3250
15
DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (continued)
PARAMETER
SYMBOL
HS Data Signaling Common
Mode Voltage Range
VCMHS
HS Squelch Detection
Threshold (Differential)
VHSSQ
CONDITIONS
MIN
TYP
-50
Squelch Threshold
Unsquelch Threshold
150
MAX
UNITS
500
mV
100
mV
mV
OUTPUT LEVELS
High Speed Low Level Output
Voltage (DP/DM referenced to
GND)
VHSOL
45Ω load
-10
10
mV
High Speed High Level Output
Voltage (DP/DM referenced to
GND)
VHSOH
45Ω load
360
440
mV
High Speed IDLE Level
Output Voltage (DP/DM
referenced to GND)
VOLHS
45Ω load
-10
10
mV
Chirp-J Output Voltage
(Differential)
VCHIRPJ
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
700
1100
mV
Chirp-K Output Voltage
(Differential)
VCHIRPK
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
-900
-500
mV
±1
uA
10
pF
LEAKAGE CURRENT
OFF-State Leakage Current
ILZ
PORT CAPACITANCE
Transceiver Input Capacitance
CIN
Pin to GND
(VDD1.8 =1.6 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = -40
5
oC
to
+85oC;
unless otherwise specified.)
Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM)
PARAMETER
SYMBOL
CONDITIONS
MIN
Rise Time
TFSR
CL = 50pF; 10 to 90% of
|VOH - VOL|
Fall Time
TFFF
CL = 50pF; 10 to 90% of
|VOH - VOL|
Output Signal Crossover
Voltage
VCRS
Differential Rise/Fall Time
Matching
FRFM
TYP
MAX
UNITS
4
20
ns
4
20
ns
Excluding the first
transition from IDLE
state
1.3
2.0
V
Excluding the first
transition from IDLE
state
90
111.1
%
FS OUTPUT DRIVER TIMING
(VDD1.8 =1.6 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.)
Revision 1.5 (03-24-06)
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SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HS OUTPUT DRIVER TIMING
Differential Rise Time
THSR
Differential Fall Time
THSF
Driver Waveform
Requirements
500
ps
500
ps
Eye pattern of Template
1 in USB2.0 specification
See
Figure
6.2
Receiver Waveform
Requirements
Eye pattern of Template
4 in USB2.0 specification
See
Figure
6.2
Data Source Jitter and
Receiver Jitter Tolerance
Eye pattern of Template
4 in USB2.0 specification
See
Figure
6.2
HIGH SPEED MODE TIMING
(VDD1.8 =1.6 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.)
Table 6.5 Dynamic Characteristics: Digital UTMI Pins
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Propagation delay from
CLKOUT to signal
2
4
ns
2
4
CL = 10pF
UTMI TIMING
RXDATA[7:0]
TPD
RXVALID
RXACTIVE
2
4
RXERROR
2
4
LINESTATE[1:0]
2
4
TXREADY
2
4
TXDATA[7:0]
TSU
TXVALID
Setup time from signal to
CLKOUT
4
OPMODE[1:0]
4
XCVRSELECT
4
TERMSELECT
4
SUSPENDN
4
TXDATA[7:0]
TXVALID
TH
Hold time from CLKOUT
to signal
0
0
XCVRSELECT
0
TERMSELECT
0
0
(VDD1.8 =1.6 to 2.0V; VDD3.3 =3.0 to 3.6V; VSS = 0V; TA = -40
SMSC GT3200, SMSC USB3250
ns
0
OPMODE[1:0]
SUSPENDN
ns
4
17
oC
DATASHEET
to
+85oC;
unless otherwise specified.)
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
6.1
Driver Characteristics of Full-Speed Drivers in High-Speed
Capable Transceivers
The USB transceiver uses a differential output driver to drive the USB data signal onto the USB cable.
Figure 6.1 shows the V/I characteristics for a full-speed driver which is part of a high-speed capable
transceiver. The normalized V/I curve for the driver must fall entirely inside the shaded region. The
V/I region is bounded by the minimum driver impedance above (40.5 Ohm) and the maximum driver
impedance below (49.5 Ohm). The output voltage must be within 10mV of ground when no current is
flowing in or out of the pin.
Drive High
Iout
(mA)
Slope = 1/49.5 Ohm
-6.1 * |VOH|
Test Limit
-10.71 * |VOH|
0
0
Slope = 1/40.5 Ohm
0.566*VOH
0.698*VOH
VOH
Vout (Volts)
Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver
Revision 1.5 (03-24-06)
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USB2.0 PHY IC
Datasheet
Drive Low
Iout
(mA)
Slope = 1/40.5 Ohm
Test Limit
10.71 * |VOH|
22
Slope = 1/49.5 Ohm
0
0
1.09V
0.434*VOH
Vout (Volts)
VOH
Figure 6.2 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver
6.2
High-speed Signaling Eye Patterns
High-speed USB signals are characterized using eye patterns. For measuring the eye patterns 4
points have been defined (see Figure 6.3). The Universal Serial Bus Specification Rev.2.0 defines the
eye patterns in several 'templates'. The two templates that are relevant to the PHY are shown below.
SMSC GT3200, SMSC USB3250
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DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
TP1 TP2
USB
Traces
Transceiver
TP3
A
Connector
Traces
B
Connector
Hub Circuit Board
TP4
Transceiver
Device Circuit Board
Figure 6.3 Eye Pattern Measurement Planes
The eye pattern in Figure 6.4 defines the transmit waveform requirements for a hub (measured at TP2
of Figure 6.3) or a device without a captive cable (measured at TP3 of Figure 6.3). The corresponding
signal levels and timings are given in Table 6.6. Time is specified as a percentage of the unit interval
(UI), which represents the nominal bit duration for a 480 Mbit/s transmission rate.
Revision 1.5 (03-24-06)
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USB2.0 PHY IC
Datasheet
Level 1
Point 3
400mV
Differential
Point 4
Point 1
0
Differential
V lt
Point 2
Point 5
Point 6
-400mV
Differential
Level 2
0%
Unit Interval
100%
Figure 6.4 Eye Pattern for Transmit Waveform and Eye Pattern Definition
.
Table 6.6 Eye Pattern for Transmit Waveform and Eye Pattern Definition
VOLTAGE LEVEL (D+, D-)
TIME
(% OF UNIT INTERVAL)
Level 1
525mV in UI following a transition,
475mV in all others
N/A
Level 2
-525mV in UI following a transition,
-475mV in all others
N/A
Point 1
0V
7.5% UI
Point 2
0V
92.5% UI
Point 3
300mV
37.5% UI
Point 4
300mV
62.5% UI
Point 5
-300mV
37.5% UI
Point 6
-300mV
62.5% UI
The eye pattern in Figure 6.5 defines the receiver sensitivity requirements for a hub (signal applied at
test point TP2 of Figure 6.3) or a device without a captive cable (signal applied at test point TP3 of
Figure 6.3). The corresponding signal levels and timings are given in Table 6.7. Timings are given as
a percentage of the unit interval (UI), which represents the nominal bit duration for a 480 Mbit/s
transmission rate.
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Level 1
400mV
Differential
Point 3
Point 4
Point 1
0 Voltｓ
Differential
Point 2
Point 5
Point 6
-400mV
Differential
Level 2
0%
100%
Figure 6.5 Eye Pattern for Receive Waveform and Eye Pattern Definition
Table 6.7 Eye Pattern for Receive Waveform and Eye Pattern Definition
VOLTAGE LEVEL (D+, D-)
TIME
(% OF UNIT INTERVAL)
Level 1
575mV
N/A
Level 2
-575mV
N/A
Point 1
0V
15% UI
Point 2
0V
85% UI
Point 3
150mV
35% UI
Point 4
150mV
65% UI
Point 5
-150mV
35% UI
Point 6
-150mV
65% UI
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Chapter 7 Functional Overview
Figure 2.1 Block Diagram on page 7 shows the functional block diagram of the PartNumber. Each of
the functions is described in detail below.
7.1
Modes of Operation
The PartNumber support two modes of operation. See Figure 7.1 for a block diagram of the digital
interface.
8-bit unidirectional mode. Selected when DATABUS16_8 = 0. CLKOUT runs at 60MHz. The 8bit transmit data bus uses the lower 8 bits of the DATA bus (ie, TXDATA[7:0] = DATA[7:0]). The
8-bit receive data bus uses the upper 8 bits of the DATA bus (ie, RXDATA[7:0] = DATA[15:8]).
16-bit bidirectional mode. Selected when DATABUS16_8 = 1. CLKOUT runs at 30MHz. An
additional signal (VALIDH) is used to identify whether the high byte of the respective 16-bit data
word is valid. The full 16-bit DATA bus is used for transmit and receive operations. If TXVALID
is asserted, then the DATA[15:0] bus accepts transmit data from the SIE. If TXVALID is deasserted,
then the DATA[15:0] bus presents received data to the SIE. VALIDH is undefined when
DATABUS16_8 = 0 (8-bit mode).
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TXVALID
1=1
-bit mode, 0=8-bit mode
6
TXVALI
D
DATAOUT[7:0
]
DATABUS16_
8
DATA[7:0]
DATAIN[7:0]
Transceiver
Core
DATAOUT[7:0
]
SELB
A
MU
X
DATAOUT[1
:8]
5
DATA[15:8]
B
DATAIN[15:8]
RXVALID
H
VALID
H
TXVALID
H
Figure 7.1 Bidirectional 16-bit interface
7.2
System Clocking
This block connects to either an external 12MHz crystal or an external clock source and generates a
480MHz multi-phase clock. The clock is used in the CRC block to over-sample the incoming received
data, resynchronize the transmit data, and is divided down to a 30MHz or 60MHz version (CLKOUT)
which acts as the system byte clock. The PLL block also outputs a clock valid signal to the other parts
of the transceiver when the clock signal is stable. All UTMI signals are synchronized to the CLKOUT
output. The behavior of the CLKOUT is as follows:
Produce the first CLKOUT transition no later than 5.6ms after negation of SUSPENDN. The
CLKOUT signal frequency error is less than 10% at this time.
The CLKOUT signal will fully meet the required accuracy of ±500ppm no later than 1.4ms after the
first transition of CLKOUT.
In HS mode there is one CLKOUT cycle per byte time. The frequency of CLKOUT does not change
when the Macrocell is switched between HS to FS modes. In FS mode (8-bit mode) there are 5 CLK60
cycles per FS bit time, typically 40 CLK60 cycles per FS byte time. If a received byte contains a stuffed
bit then the byte boundary can be stretched to 45 CLK60 cycles, and two stuffed bits would result in
a 50 CLK60 cycles.
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Figure 7.2 shows the relationship between CLK60 and the transmit data transfer signals in FS mode.
TXREADY is only asserted for one CLK60 per byte time to signal the SIE that the data on the TXDATA
lines has been read by the Macrocell. The SIE may hold the data on the TXDATA lines for the duration
of the byte time. Transitions of TXVALID must meet the defined setup and hold times relative to
CLK60.
CLKOUT
TXVALID
TXDATA[7:0]
PID
DATA1
DATA2
Don't
DATA3
DATA4
Care
TXREADY
Figure 7.2 FS CLK Relationship to Transmit Data and Control Signals (8-bit mode)
Figure 7.3 shows the relationship between CLK60 and the receive data control signals in FS mode.
RXACTIVE "frames" a packet, transitioning only at the beginning and end of a packet. However
transitions of RXVALID may take place any time 8 bits of data are available. Figure 7.3 also shows
how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be
presented for the full byte time. The XCVRSELECT signal determines whether the HS or FS timing
relationship is applied to the data and control signals.
CLK60
RXACTIVE
RXDATA[7:0]
DATA(n)
DATA(n+1)
DATA(n+2)
RXVALID
Figure 7.3 FS CLK Relationship to Receive Data and Control Signals (8-bit mode)
7.3
Clock and Data Recovery Circuit
This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer. The Elasticity
Buffer is used to compensate for differences between the transmitting and receiving clock domains.
The USB2.0 specification defines a maximum clock error of ±1000ppm of drift.
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7.4
TX Logic
This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit
operations. These operations include parallel to serial conversion, bit stuffing and NRZI encoding.
Upon valid assertion of the proper TX control lines by the SIE and TX State Machine, the TX LOGIC
block will synchronously shift, at either the FS or HS rate, the data to the FS/HS TX block to be
transmitted on the USB cable. Data transmit timing is shown in Figure 7.4.
CLK60
TXVALID
TXDATA[7:0]
DATA DATA
PID
DATA DATA
CRC
CRC
TXREADY
DP/DM
PID
SYNC
DATA DATA
DATA
DATA
CRC
CRC
EOP
Figure 7.4 Transmit Timing for a Data Packet (8-bit mode)
CLK30
TXVALID
VALIDH
DATA[7:0]
PID
DATA (1)
DATA (3)
CRC (HI)
DATA[15:8]
DATA (0)
DATA (2)
DATA (4)
CRC (LO)
TXREADY
DP/DM
SYNC
PID
DATA
DATA
DATA
DATA
DATA
CRC
0
1
2
3
4
HI
CRC
EOP
LO
Figure 7.5 Transmit Timing for 16-bit Data, Even Byte Count
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CLK30
TXVALID
VALIDH
DATA[7:0]
PID
DATA (1)
DATA (3)
DATA[15:8]
DATA (0)
DATA (2)
CRC(HI)
CRC (LO)
TXREADY
DP/DM
SYNC
PID
DATA
DATA
DATA
DATA
DATA
CRC
0
1
2
3
4
HI
CRC
EOP
LO
Figure 7.6 Transmit Timing for 16-bit Data, Odd Byte Count
The behavior of the Transmit State Machine is described below.
7.5
Asserting a RESET forces the transmit state machine into the Reset state which negates
TXREADY. When RESET is negated the transmit state machine will enter a wait state.
The SIE asserts TXVALID to begin a transmission.
After the SIE asserts TXVALID it can assume that the transmission has started when it detects
TXREADY has been asserted.
The SIE must assume that the PHY has consumed a data byte if TXREADY and TXVALID are
asserted on the rising edge of CLKOUT.
The SIE must have valid packet information (PID) asserted on the TXDATA bus coincident with the
assertion of TXVALID.
TXREADY is sampled by the SIE on the rising edge of CLKOUT.
The SIE negates TXVALID to complete a packet. Once negated, the transmit logic will never
reassert TXREADY until after the EOP has been generated. (TXREADY will not re-assert until
TXVALID asserts again).
The PHY is ready to transmit another packet immediately, however the SIE must conform to the
minimum inter-packet delays identified in the USB2.0 specification.
RX Logic
This block receives serial data from the CRC block and processes it to be transferred to the SIE on
the RXDATA bus. The processing involved includes NRZI decoding, bit unstuffing, and serial to
parallel conversion. Upon valid assertion of the proper RX control lines by the RX State Machine, the
RX Logic block will provide bytes to the RXDATA bus as shown in the figures below. The behavior of
the Receive State Machine is described below.
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CLK60
RXACTIVE
RXDATA[7:0]
Invalid Data
DATA
Invalid
DATA
DATA
DATA
DATA
Invalid
CRC
Data
CRC
RXVALID
Figure 7.7 Receive Timing for Data with Unstuffed Bits (8-bit mode)
CLK30
RXVALID
VALIDH
DATA[7:0]
PID
DATA[15:8]
DATA (0)
(1)
DATA (3)
CRC (LO)
DATA (2)
DATA (4)
CRC (HI)
DATA
RXACTIVE
DP/DM
SYNC
PID
DATA
DATA
DATA
DATA
DATA
CRC
CRC
0
1
2
3
4
LO
HI
EOP
Figure 7.8 Receive Timing for 16-bit Data, Even Byte Count
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CLK30
RXVALID
VALIDH
DATA[7:0]
DATA[15:8]
PID
DATA (1)
DATA (3)
DATA (0)
DATA (2)
CRC (LO)
CRC (HI)
RXACTIVE
DP/DM
SYNC
PID
DATA
DATA
DATA
DAT A
CRC
CRC
0
1
2
3
LO
HI
EOP
Figure 7.9 Receive Timing for 16-bit Data, Odd Byte Count
The assertion of RESET will force the Receive State Machine into the Reset state. The Reset state
deasserts RXACTIVE and RXVALID. When the RESET signal is deasserted the Receive State
Machine enters the RX Wait state and starts looking for a SYNC pattern on the USB. When a SYNC
pattern is detected the state machine will enter the Strip SYNC state and assert RXACTIVE. The length
of the received Hi-Speed SYNC pattern varies and can be up to 32 bits long or as short as 12 bits
long when at the end of five hubs. As a result, the state machine may remain in the Strip SYNC state
for several byte times before capturing the first byte of data and entering the RX Data state.
After valid serial data is received, the state machine enters the RX Data state, where the data is loaded
into the RX Holding Register on the rising edge of CLKOUT and RXVALID is asserted. The SIE must
clock the data off the RXDATA bus on the next rising edge of CLKOUT. If OPMODE = Normal, then
stuffed bits are stripped from the data stream. Each time 8 stuffed bits are accumulated the state
machine will enter the RX Data Wait state, negating RXVALID thus skipping a byte time.
When the EOP is detected the state machine will enter the Strip EOP state and negate RXACTIVE
and RXVALID. After the EOP has been stripped the Receive State Machine will reenter the RX Wait
state and begin looking for the next packet.
The behavior of the Receive State Machine is described below:
RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.
In the RX Wait state the receiver is always looking for SYNC.
The GT3200/USB3250 asserts RXACTIVE when SYNC is detected (Strip SYNC state).
The GT3200/USB3250 negates RXACTIVE when an EOP is detected and the elasticity buffer is
empty (Strip EOP state).
When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.
RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time.
This will occur if 8 stuffed bits have been accumulated.
The SIE must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data
state).
Figure 7.10 shows the timing relationship between the received data (DP/DM) , RXVALID,
RXACTIVE, RXERROR and RXDATA signals.
Note 7.1
The USB2.0 Transceiver does NOT decode Packet ID's (PIDs). They are passed to the
SIE for decoding.
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Note 7.2
Figure 7.10, Figure 7.11 and Figure 7.12 are timing examples of a HS/FS Macrocell when
it is in HS mode. When a HS/FS Macrocell is in FS Mode (8-bit mode) there are
approximately 40 CLK60 cycles every byte time. The Receive State Machine assumes that
the SIE captures the data on the RXDATA bus if RXACTIVE and RXVALID are asserted.
In FS mode, RXVALID will only be asserted for one CLK60 per byte time.
Note 7.3
Figure 7.10, Figure 7.11 and Figure 7.12 the SYNC pattern on DP/DM is shown as one
byte long. The SYNC pattern received by a device can vary in length. These figures
assume that all but the last 12 bits have been consumed by the hubs between the device
and the host controller.
CLK60
RXACTIVE
RXDATA[7:0]
PID
RXVALID
RXERROR
SYNC
DP/DM
PID
EOP
Figure 7.10 Receive Timing for Data (with CRC-16 in 8-bit mode)
CLK60
RXACTIVE
PID
RXDATA[7:0]
DATA
DATA
RXVALID
RXERROR
DP/DM
SYNC
PID
DATA
DATA
EOP
CRC-5 Computation
Figure 7.11 Receive Timing for Setup Packet (8-bit mode)
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CLK60
RXACTIVE
RXDATA[7:0]
PID
DATA
DATA
DATA
DATA
CRC
CRC
RXVALID
RXERROR
DP/DM
SYNC
PID
DATA
DATA
DATA
DATA
CRC
CRC
EOP
CRC-16 Computation
Figure 7.12 Receive Timing for Data Packet with CRC-16 (8-bit mode)
7.6
FS/HS RX
The receivers connect directly to the USB cable. The block contains a separate differential receiver
for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream
through the mulitplexer to the RX Logic block. The FS mode section of the FS/HS RX block also
consists of a single-ended receiver on each of the data lines to determine the correct FS LINESTATE.
For HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never
interpreted as data.
7.7
FS/HS TX
The transmitters connect directly to the USB cable. The block contains a separate differential FS and
HS transmitter which receive encoded, bitstuffed, serialized data from the TX Logic block and transmit
it on the USB cable. The FS/HS TX block also contains circuitry that either enables or disables the
pull-up resistor on the D+ line.
7.8
Biasing
This block consists of an internal bandgap reference circuit used for generating the driver current and
the biasing of the analog circuits. This block requires an external precision resistor (12kΩ +/- 1% from
the RBIAS pin to analog ground).
7.9
Power Control
This is the block that receives and distributes all the power for the transceiver. This block is also
responsible for handling ESD protection.
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Chapter 8 Application Notes
The following sections consist of select functional explanations to aid in implementing the PHY into a
system. For complete description and specifications consult the USB2.0 Transceiver Macrocell
Interface Specification and Universal Serial Bus Specification Revision 2.0.
8.1
Linestate
The voltage thresholds that the LINESTATE[1:0] signals use to reflect the state of DP and DM depend
on the state of XCVRSELECT. LINESTATE[1:0] uses HS thresholds when the HS transceiver is
enabled (XCVRSELECT = 0) and FS thresholds when the FS transceiver is enabled (XCVRSELECT
= 1). There is not a concept of variable single-ended thresholds in the USB2.0 specification for HS
mode.
The HS receiver is used to detect Chirp J or K, where the output of the HS receiver is always qualified
with the Squelch signal. If squelched, the output of the HS receiver is ignored. In the PartNumber, as
an alternative to using variable thresholds for the single-ended receivers, the following approach is
used.
Table 8.1 Linestate States
STATE OF DP/DM LINES
LINESTATE[1:0]
LS[1]
LS[0]
FULL SPEED
XCVRSELECT =1
TERMSELECT=1
HIGH SPEED
XCVRSELECT =0
TERMSELECT=0
CHIRP MODE
XCVRSELECT =0
TERMSELECT=1
0
0
SE0
Squelch
Squelch
0
1
J
!Squelch
!Squelch & HS
Differential Receiver
Output
1
0
K
Invalid
!Squelch & !HS
Differential Receiver
Output
1
1
SE1
Invalid
Invalid
In HS mode, 3ms of no USB activity (IDLE state) signals a reset. The SIE monitors LINESTATE[1:0]
for the IDLE state. To minimize transitions on LINESTATE[1:0] while in HS mode, the presence of
!Squelch is used to force LINESTATE[1:0] to a J state.
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8.2
OPMODES
The OPMODE[1:0] pins allow control of the operating modes.
Table 8.2 Operational Modes
MODE[1:0]
STATE#
STATE NAME
DESCRIPTION
00
0
Normal Operation
01
1
Non-Driving
Allows the transceiver logic to support a soft disconnect
feature which tri-states both the HS and FS transmitters,
and removes any termination from the USB making it
appear to an upstream port that the device has been
disconnected from the bus
10
2
Disable Bit
Stuffing and NRZI
encoding
Disables bitstuffing and NRZI encoding logic so that 1's
loaded from the TXDATA bus become 'J's on the DP/DM
and 0's become 'K's
11
3
Reserved
Transceiver operates with normal USB data encoding
and decoding
N/A
The OPMODE[1:0] signals are normally changed only when the transmitter and the receiver are
quiescent, i.e. when entering a test mode or for a device initiated resume.
When using OPMODE[1:0] = 10 (state 2), OPMODES are set, and then 5 60MHz clocks later,
TXVALID is asserted. In this case, the SYNC and EOP patterns are not transmitted.
The only exception to this is when OPMODE[1:0] is set to state 2 while TXVALID has been asserted
(the transceiver is transmitting a packet), in order to flag a transmission error. In this case, the PHY
has already transmitted the SYNC pattern so upon negation of TXVALID the EOP must also be
transmitted to properly terminate the packet. Changing the OPMODE[1:0] signals under all other
conditions, while the transceiver is transmitting or receiving data will generate undefined results.
Under no circumstances should the device controller change OPMODE while the DP/DM lines are still
transmitting or unpredictable changes on DP/DM are likely to occur. The same applies for
TERMSELECT and XCVRSELECT.
8.3
Test Mode Support
Table 8.3 USB2.0 Test Mode to Macrocell Mapping
PARTNUMBER SETUP
USB2.0 TEST MODES
OPERATIONAL MODE
SIE TRANSMITTED
DATA
XCVRSELECT &
TERMSELECT
SE0_NAK
Normal
No transmit
HS
J
Disable
All '1's
HS
K
Disable
All '0's
HS
Test_Packet
Normal
Test Packet data
HS
8.4
SE0 Handling
For FS operation, IDLE is a J state on the bus. SE0 is used as part of the EOP or to indicate reset.
When asserted in an EOP, SE0 is never asserted for more than 2 bit times. The assertion of SE0 for
more than 2.5us is interpreted as a reset by the device operating in FS mode.
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For HS operation, IDLE is a SE0 state on the bus. SE0 is also used to reset a HS device. A HS
device cannot use the 2.5us assertion of SE0 (as defined for FS operation) to indicate reset since the
bus is often in this state between packets. If no bus activity (IDLE) is detected for more than 3ms, a
HS device must determine whether the downstream facing port is signaling a suspend or a reset. The
following section details how this determination is made. If a reset is signaled, the HS device will then
initiate the HS Detection Handshake protocol.
8.5
Reset Detection
If a device in HS mode detects bus inactivity for more than 3ms (T1), it reverts to FS mode. This
enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The
SIE must then check LINESTATE for the SE0 condition. If SE0 is asserted at time T2, then the
upstream port is forcing the reset state to the device (i.e., a Driven SE0). The device will then initiate
the HS detection handshake protocol.
T0
T2
T1
time
XCVRSELECT
TERMSELECT
DP/DM
Last
Activity
Driven SE0
HS Detection
Handshake
Figure 8.1 Reset Timing Behavior (HS Mode)
Table 8.4 Reset Timing Values (HS Mode)
TIMING
PARAMETER
HS Reset T0
8.6
DESCRIPTION
VALUE
Bus activity ceases, signaling either a reset or a
SUSPEND.
0 (reference)
T1
Earliest time at which the device may place itself in
FS mode after bus activity stops.
HS Reset T0 + 3. 0ms < T1 < HS
Reset T0 + 3.125ms
T2
SIE samples LINESTATE. If LINESTATE = SE0, then
the SE0 on the bus is due to a Reset state. The
device now enters the HS Detection Handshake
protocol.
T1 + 100µs < T2 < T1 + 875µs
Suspend Detection
If a HS device detects SE0 asserted on the bus for more than 3ms (T1), it reverts to FS mode. This
enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The
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SIE must then check LINESTATE for the J condition. If J is asserted at time T2, then the upstream
port is asserting a soft SE0 and the USB is in a J state indicating a suspend condition. By time T4
the device must be fully suspended.
T0
T1
T2
T3
T4
time
SUSPENDN
XCVRSELECT
TERMSELECT
DP/DM
Last
Activity
Soft SE0
'J' State
Device is suspended
Figure 8.2 Suspend Timing Behavior (HS Mode)
Table 8.5 Suspend Timing Values (HS Mode)
TIMING
PARAMETER
8.7
DESCRIPTION
VALUE
HS Reset T0
End of last bus activity, signaling either a reset or
a SUSPEND.
0 (reference)
T1
The time at which the device must place itself in
FS mode after bus activity stops.
HS Reset T0 + 3. 0ms < T1 <
HS Reset T0 + 3.125ms
T2
SIE samples LINESTATE. If LINESTATE = 'J', then
the initial SE0 on the bus (T0 - T1) had been due
to a Suspend state and the SIE remains in HS
mode.
T1 + 100 µs < T2 < T1 + 875µs
T3
The earliest time where a device can issue
Resume signaling.
HS Reset T0 + 5ms
T4
The latest time that a device must actually be
suspended, drawing no more than the suspend
current from the bus.
HS Reset T0 + 10ms
HS Detection Handshake
The High Speed Detection Handshake process is entered from one of three states: suspend, active
FS or active HS. The downstream facing port asserting an SE0 state on the bus initiates the HS
Detection Handshake. Depending on the initial state, an SE0 condition can be asserted from 0 to 4
ms before initiating the HS Detection Handshake. These states are described in the USB2.0
specification.
There are three ways in which a device may enter the HS Handshake Detection process:
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1. If the device is suspended and it detects an SE0 state on the bus it may immediately enter the HS
handshake detection process.
2. If the device is in FS mode and an SE0 state is detected for more than 2.5µs. it may enter the HS
handshake detection process.
3. If the device is in HS mode and an SE0 state is detected for more than 3.0ms. it may enter the
HS handshake detection process. In HS mode, a device must first determine whether the SE0 state
is signaling a suspend or a reset condition. To do this the device reverts to FS mode by placing
XCVRSELECT and TERMSELECT into FS mode. The device must not wait more than 3.125ms
before the reversion to FS mode. After reverting to FS mode, no less than 100µs and no more
than 875µs later the SIE must check the LINESTATE signals. If a J state is detected the device
will enter a suspend state. If an SE0 state is detected, then the device will enter the HS Handshake
detection process.
In each case, the assertion of the SE0 state on the bus initiates the reset. The minimum reset interval
is 10ms. Depending on the previous mode that the bus was in, the delay between the initial assertion
of the SE0 state and entering the HS Handshake detection can be from 0 to 4ms.
This transceiver design pushes as much of the responsibility for timing events on to the SIE as
possible, and the SIE requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3
above, CLKOUT has been running and is stable, however in case 1 the PHY is reset from a suspend
state, and the internal oscillator and clocks of the transceiver are assumed to be powered down. A
device has up to 6ms after the release of SUSPENDN to assert a minimum of a 1ms Chirp K.
8.8
HS Detection Handshake - FS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The
DP pull-up is asserted and the HS terminations are disabled. The SIE then sets OPMODE to Disable
Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's
data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and
must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp
sequence from the host port.
If the downstream facing port is not HS capable, then the HS K asserted by the device is ignored and
the alternating sequence of HS Chirp K's and J's is not generated. If no chirps are detected (T4) by
the device, it will enter FS mode by returning XCVRSELECT to FS mode.
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T1
T0
T2 T3
T5
T4
time
OPMODE 0
OPMODE 1
XCVRSELECT
TERMSELECT
TXVALID
SOF
DP/DM
SE0
FS Mode
Device Chirp K
No
Downstream
Facing Port
Chirps
Figure 8.3 HS Detection Handshake Timing Behavior (FS Mode)
Table 8.6 HS Detection Handshake Timing Values (FS Mode)
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
HS Handshake begins. DP pull-up enabled, HS
terminations disabled. The XCVRSELECT and
OPMODE inputs are then set for HS with bitstuffing
disabled, and TXVALID is asserted at least 5
60MHz clocks later.
0 (reference)
T1
Device enables HS Transceiver and asserts Chirp
K on the bus.
T0 < T1 < HS Reset T0 + 6.0ms
T2
Device removes Chirp K from the bus. 1ms
minimum width.
T1 + 1.0 ms < T2 < HS Reset
T0 + 7.0ms
T3
Earliest time when downstream facing port may
assert Chirp KJ sequence on the bus.
T2 < T3 < T2+100µs
T4
Chirp not detected by the device. Device reverts to
FS default state and waits for end of reset.
T2 + 1.0ms < T4 < T2 + 2.5ms
T5
Earliest time at which host port may end reset
HS Reset T0 + 10ms
Note 8.1
T0 may occur to 4ms after HS Reset T0.
Note 8.2
The SIE must assert the Chirp K for 66000 CLK60 cycles to ensure a 1ms minimum
duration.
SMSC GT3200, SMSC USB3250
37
DATASHEET
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USB2.0 PHY IC
Datasheet
8.9
HS Detection Handshake - HS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The
DP pull-up is asserted and the HS terminations are disabled. The SIE then sets OPMODE to Disable
Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's
data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and
must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp
sequence from the downstream facing port. If the downstream facing port is HS capable then it will
begin generating an alternating sequence of Chirp K's and Chirp J's (T3) after the termination of the
chirp from the device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it
will enter HS mode by setting TERMSELECT to HS mode (T7).
Figure 8.4 provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the
device port must terminate the sequence of Chirp K's and Chirp J's (T8) and assert SE0 (T8-T9). Note
that the sequence of Chirp K's and Chirp J's constitutes bus activity.
Start Chirp
K-J-K-JK-J
detection
!K
State
Chirp
Count = 0
K State
Detect K?
Chirp Count != 6
& !SE0
!J
INC
Chirp
Count
Chirp
Invalid
SE0
Chirp Count
=6 6 66
J State
INC
Chirp
Detect J?
Chirp
Valid
Chirp Count
!= 6
& !SE0
Figure 8.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram
The Chirp K-J-K-J-K-J sequence occurs too slow to propagate through the serial data path, therefore
LINESTATE signal transitions must be used by the SIE to step through the Chirp K-J-K-J-K-J state
diagram, where "K State" is equivalent to LINESTATE = K State and "J State" is equivalent to
LINESTATE = J State. The SIE must employ a counter (Chirp Count) to count the number of Chirp K
and Chirp J states. Note that LINESTATE does not filter the bus signals so the requirement that a bus
state must be "continuously asserted for 2.5µs" must be verified by the SIE sampling the LINESTATE
signals.
Revision 1.5 (03-24-06)
38
DATASHEET
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
T0
T1
T4 T5
T2
T8
T6 T7
T9
time
T3
OPMODE 0
OPMODE 1
XCVRSELECT
TERMSELECT
TXVALID
Device
Chirp K
DP/DM
Device
Port
Chirp
K
J
K
J
K
J
K
Downstream Facing
Port Chirps
J
SE0
SOF
HS Mode
Figure 8.5 HS Detection Handshake Timing Behavior (HS Mode)
Table 8.7 Reset Timing Values
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
HS Handshake begins. DP pull-up enabled, HS
terminations disabled.
0 (reference)
T1
Device asserts Chirp K on the bus.
T0 < T1 < HS Reset T0 + 6.0ms
T2
Device removes Chirp K from the bus. 1 ms minimum
width.
T0 + 1.0ms < T2 < HS Reset T0 +
7.0ms
T3
Downstream facing port asserts Chirp K on the bus.
T2 < T3 < T2+100µs
T4
Downstream facing port toggles Chirp K to Chirp J on
the bus.
T3 + 40µs < T4 < T3 + 60µs
T5
Downstream facing port toggles Chirp J to Chirp K on
the bus.
T4 + 40µs < T5 < T4 + 60µs
T6
Device detects downstream port chirp.
T6
T7
Chirp detected by the device. Device removes DP
pull-up and asserts HS terminations, reverts to HS
default state and waits for end of reset.
T6 < T7 < T6 + 500µs
T8
Terminate host port Chirp K-J sequence (Repeating
T4 and T5)
T9 - 500µs < T8 < T9 - 100µs
SMSC GT3200, SMSC USB3250
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DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
Table 8.7 Reset Timing Values (continued)
TIMING
PARAMETER
T9
8.10
DESCRIPTION
The earliest time at which host port may end reset.
The latest time, at which the device may remove the
DP pull-up and assert the HS terminations, reverts to
HS default state.
VALUE
HS Reset T0 + 10ms
Note 8.3
T0 may be up to 4ms after HS Reset T0.
Note 8.4
The SIE must use LINESTATE to detect the downstream port chirp sequence.
Note 8.5
Due to the assertion of the HS termination on the host port and FS termination on the
device port, between T1 and T7 the signaling levels on the bus are higher than HS
signaling levels and are less than FS signaling levels.
HS Detection Handshake - Suspend Timing
If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are
assumed to be powered down. Figure 8.6 shows how CLK60 is used to control the duration of the
chirp generated by the device.
When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE),
SUSPENDN is combinatorially negated at time T0 by the SIE. It takes approximately 5 milliseconds
for the transceiver's oscillator to stabilize. The device does not generate any transitions of the CLK60
signal until it is "usable" (where "usable" is defined as stable to within ±10% of the nominal frequency
and the duty cycle accuracy 50±5%).
The first transition of CLK60 occurs at T1. The SIE then sets OPMODE to Disable Bit Stuffing and
NRZI encoding, XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLK60 cycles to
ensure a 1ms minimum duration. If CLK60 is 10% fast (66MHz) then Chirp K will be 1.0ms. If CLK60
is 10% slow (54 MHz) then Chirp K will be 1.2ms. The 5.6ms requirement for the first CLK60 transition
after SUSPENDN, ensures enough time to assert a 1ms Chirp K and still complete before T3. Once
the Chirp K is completed (T3) the SIE can begin looking for host chirps and use CLK60 to time the
process. At this time, the device follows the same protocol as in section 8.9 for completion of the High
Speed Handshake.
Revision 1.5 (03-24-06)
40
DATASHEET
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
T0
T1
T2
T3
T4
time
OPMODE 0
OPMODE 1
XCVRSELECT
TERMSELECT
SUSPENDN
TXVALID
CLK60
DP/DM
J
SE0
CLK power up time
Device Chirp K
Look for host chirps
Figure 8.6 HS Detection Handshake Timing Behavior from Suspend
To detect the assertion of the downstream Chirp K's and Chirp J's for 2.5us {TFILT}, the SIE must see
the appropriate LINESTATE signals asserted continuously for 165 CLK60 cycles.
Table 8.8 HS Detection Handshake Timing Values from Suspend
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
While in suspend state an SE0 is detected on the
USB. HS Handshake begins. D+ pull-up enabled, HS
terminations disabled, SUSPENDN negated.
0 (HS Reset T0)
T1
First transition of CLKOUT. CLKOUT "Usable"
(frequency accurate to ±10%, duty cycle accurate to
50±5).
T0 < T1 < T0 + 5.6ms
T2
Device asserts Chirp K on the bus.
T1 < T2 < T0 + 5.8ms
T3
Device removes Chirp K from the bus. (1 ms
minimum width) and begins looking for host chirps.
T2 + 1.0 ms < T3 < T0 + 7.0 ms
T4
CLK "Nominal" (CLKOUT is frequency accurate to
±500 ppm, duty cycle accurate to 50±5).
T1 < T3 < T0 + 20.0ms
SMSC GT3200, SMSC USB3250
41
DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
8.11
Assertion of Resume
In this case, an event internal to the device initiates the resume process. A device with remote wakeup capability must wait for at least 5ms after the bus is in the idle state before sending the remote
wake-up resume signaling. This allows the hubs to get into their suspend state and prepare for
propagating resume signaling.
The device has 10ms where it can draw a non-suspend current before it must drive resume signaling.
At the beginning of this period the SIE may negate SUSPENDN, allowing the transceiver (and its
oscillator) to power up and stabilize.
Figure 8.7 illustrates the behavior of a device returning to HS mode after being suspended. At T4, a
device that was previously in FS mode would maintain TERMSELECT and XCVRSELECT high.
To generate resume signaling (FS 'K') the device is placed in the "Disable Bit Stuffing and NRZI
encoding" Operational Mode (OPMODE [1:0] = 10), TERMSELECT and XCVRSELECT must be in FS
mode, TXVALID asserted, and all 0's data is presented on the TXDATA bus for at least 1ms (T1 - T2).
T0
T1
T2
T3
T4
time
SUSPENDN
XCVRSELECT &
TERMSELECT
TXVALID
DP/DM
FS Idle ('J')
'K' State
SE0
FS Mode
HS Mode
Figure 8.7 Resume Timing Behavior (HS Mode)
Table 8.9 Resume Timing Values (HS Mode)
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
Internal device event initiating the resume process
0 (reference)
T1
Device asserts FS 'K' on the bus to signal resume
request to downstream port
T0 < T1 < T0 + 10ms.
T2
The device releases FS 'K' on the bus. However by
this time the 'K' state is held by downstream port.
T1 + 1.0ms < T2 < T1 + 15ms
T3
Downstream port asserts SE0.
T1 + 20ms
T4
Latest time at which a device, which was previously
in HS mode, must restore HS mode after bus activity
stops.
T3 + 1.33µs {2 Low-speed bit
times}
Revision 1.5 (03-24-06)
42
DATASHEET
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
8.12
Detection of Resume
Resume signaling always takes place in FS mode (TERMSELECT and XCVRSELECT = FS enabled),
so the behavior for a HS device is identical to that if a FS device. The SIE uses the LINESTATE signals
to determine when the USB transitions from the 'J' to the 'K' state and finally to the terminating FS
EOP (SE0 for 1.25us-1.5µs.).
The resume signaling (FS 'K') will be asserted for at least 20ms. At the beginning of this period the
SIE may negate SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize.
The FS EOP condition is relatively short. SIEs that simply look for an SE0 condition to exit suspend
mode do not necessarily give the transceiver's clock generator enough time to stabilize. It is
recommended that all SIE implementations key off the 'J' to 'K' transition for exiting suspend mode
(SUSPENDN = 1). And within 1.25µs after the transition to the SE0 state (low-speed EOP) the SIE
must enable normal operation, i.e. enter HS or FS mode depending on the mode the device was in
when it was suspended.
If the device was in FS mode: then the SIE leaves the FS terminations enabled. After the SE0 expires,
the downstream port will assert a J state for one low-speed bit time, and the bus will enter a FS Idle
state (maintained by the FS terminations).
If the device was in HS mode: then the SIE must switch to the FS terminations before the SE0 expires
( < 1.25µs). After the SE0 expires, the bus will then enter a HS IDLE state (maintained by the HS
terminations).
8.13
HS Device Attach
Figure 8.8 demonstrates the timing of the PHY control signals during a device attach event. When a
HS device is attached to an upstream port, power is asserted to the device and the device sets
XCVRSELECT and TERMSELECT to FS mode (time T1).
VBUS is the +5V power available on the USB cable. Device Reset in Figure 8.8 indicates that VBUS
is within normal operational range as defined in the USB2.0 specification. The assertion of Device
Reset (T0) by the upstream port will initialize the device. By monitoring LINESTATE, the SIE state
machine knows to set the XCVRSELECT and TERMSELECT signals to FS mode (T1).
The standard FS technique of using a pull-up resistor on DP to signal the attach of a FS device is
employed. The SIE must then check the LINESTATE signals for SE0. If LINESTATE = SE0 is asserted
at time T2 then the upstream port is forcing the reset state to the device (i.e. Driven SE0). The device
will then reset itself before initiating the HS Detection Handshake protocol.
SMSC GT3200, SMSC USB3250
43
DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
T0
T1
T2
time
VBUS
Device Reset
XCVRSELECT
TERMSELECT
SE0
Idle (FS 'J')
DP/DM
HS Detection
Handshake
Figure 8.8 Device Attach Behavior
Table 8.10 Attach and Reset Timing Values
TIMING
PARAMETER
DESCRIPTION
VALUE
T0
Vbus Valid.
0 (reference)
T1
Maximum time from Vbus valid to when the device
must signal attach.
T0 + 100ms < T1
T2 (HS Reset T0)
Debounce interval. The device now enters the HS
Detection Handshake protocol.
T1 + 100ms < T2
Revision 1.5 (03-24-06)
44
DATASHEET
SMSC GT3200, SMSC USB3250
USB2.0 PHY IC
Datasheet
8.14
Application Diagrams
VDD3.3
VDD1.8
UTMI
Voltage
Regulator
1uF
10uF
10uF
TXVALID
TXREADY
RXACTIVE
RXVALID
RXERROR
VALIDH
DATABUS16_8
1uF
50
47
46
45
44
42
41
40
39
37
36
35
34
31
30
29
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
0
1
2
3
4
5
6
7
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
8
9
10
11
12
13
14
15
20
XCVRSELECT
21
TERMSELECT
15
SUSPENDN
28
RESET
24
OPMODE 0
23
OPMODE 1
LINESTATE 0 26
LINESTATE 1 25
USB
C LOAD
11
51
57
56
52
58
53
60
XI
CLKOUT 55
8
RBIAS
5
DP
12KΩ
1ΜΩ
12MHz
Crystal
USB-B
12
XO
DM
4
C LOAD
POWER
13 VDDA1.8
Ferrite Bead
10uF
19
VDD1.8
27
VDD1.8
43
VDD1.8
59
VDD1.8
VDD1.8
6
VDDA3.3
9
VDDA3.3
Ferrite Bead
18 VDD3.3
32 VDD3.3
49 VDD3.3
VDD3.3
VSSA 2
VSSA 7
VSSA 10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16
17
22
33
38
48
54
61
62
63
64
GND
Figure 8.9 Application Diagram for 64-pin TQFP Package
SMSC GT3200, SMSC USB3250
45
DATASHEET
Revision 1.5 (03-24-06)
USB2.0 PHY IC
Datasheet
VDD3.3
VDD1.8
UTMI
Voltage
Regulator
1uF
10uF
TXVALID
TXREADY
RXACTIVE
RXVALID
RXERROR
VALIDH
DATABUS16_8
1uF
10uF
44
42
41
40
39
37
36
35
34
32
31
30
29
27
26
25
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
17
XCVRSELECT
18
TERMSELECT
13
SUSPENDN
24
RESET
DATA 8
DATA 9
DATA 10
DATA 11
DATA 12
DATA 13
DATA 14
DATA 15
20
OPMODE 0
19
OPMODE 1
LINESTATE 0 22
LINESTATE 1 21
USB
C LOAD
10
45
51
50
46
52
47
54
XI
CLKOUT 49
6
RBIAS
DP
3
12KΩ
1ΜΩ
12MHz
Crystal
USB-B
11
XO
DM
2
C LOAD
POWER
12 VDDA1.8
Ferrite Bead
10uF
16
VDD1.8
23
VDD1.8
38
VDD1.8
53
VDD1.8
VDD1.8
4
VDDA3.3
7
VDDA3.3
Ferrite Bead
15 VDD3.3
28 VDD3.3
43 VDD3.3
VSSA
VSSA
VSSA
VSSA
VSS
VSS
VSS
VSS
VSS
1
5
8
9
14
33
48
55
56
VDD3.3
GND
Figure 8.10 Application Diagram for 56-pin QFN Package
Revision 1.5 (03-24-06)
46
DATASHEET
SMSC GT3200, SMSC USB3250
REVISION HISTORY
DESCRIPTION
REVISION
-
DATE
RELEASED BY
-
-
R1
D
5
SEE SPEC FRONT PAGE FOR REVISION HISTORY
R2
D1
3
0.25
GAUGE PLANE
0°-7°
E1/4
D1/4
3
E1
4
E
e
L
L1
b
2
DETAIL "A" (SCALE: 2/1)
47
DATASHEET
TOP VIEW
SEE DETAIL "A"
C
A2
A
SEATING PLANE
A1
c
ccc C
SIDE VIEW
SMSC GT3200, SMSC USB3250
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETER.
2. TRUE POSITION SPREAD TOLERANCE OF EACH LEAD IS ± 0.04mm MAXIMUM.
3. DIMENSIONS "D1" AND "E1" DO NOT INCLUDE MOLD PROTRUSIONS. MAXIMUM ALLOWED
PROTRUSION IS 0.25 mm PER SIDE.
4. DIMENSION "L" IS MEASURED AT THE GAUGE PLANE, 0.25mm ABOVE THE SEATING PLANE.
5. DETAILS ON PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE
INDICATED.
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
AND TOLERANCES ARE:
DECIMAL
±0.1
X.X
X.XX ±0.05
X.XXX ±0.025
INTERPRET DIM AND TOL PER
ASME Y14.5M - 1994
MATERIAL
3-D VIEW
THIRD ANGLE PROJECTION
80 ARKAY DRIVE
HAUPPAUGE, NY 11788
USA
ANGULAR
±1°
TITLE
NAME
DATE
DRAWN
FINISH
S.K.ILIEV
12/17/04
CHECKED
PRINT WITH "SCALE TO FIT"
DO NOT SCALE DRAWING
S.K.ILIEV
Figure 9.1 GT3200 TQFP Package Outline and Parameters
REV
DWG NUMBER
MO-64-TQFP-10x10x1.4
12/17/04
APPROVED
S.K.ILIEV
PACKAGE OUTLINE
64 PIN TQFP-10x10x1.4mm BODY-0.5mm PITCH
SCALE
12/17/04
1:1
STD COMPLIANCE
JEDEC: MS-026 (D)
D
SHEET
1 OF 1
USB2.0 PHY IC
The PHY is offered in four package types: GT3200-JD (10x10x1.4mm TQFP), GT3200-JN (7x7x1.4mm TQFP), GT3200-JV (7x7x1.4mm TQFP lead
free), USB3250-ABZJ (8x8x0.85mm QFN lead free)
Datasheet
Revision 1.5 (03-24-06)
Chapter 9 Package Outlines
D2
D1
A
e
TERMINAL #1
IDENTIFIER AREA
(D/2 X E/2)
B
3
DESCRIPTION
DATE
INITIAL RELEASE
2/07/04
S.K.ILIEV
REMOVE "PRELIMINARY" NOTE
10/7/04
S.K.ILIEV
7/2/05
S.K.ILIEV
L(MAX) FROM 0.55 TO 0.50. ADDED D2/E2 VARIATIONS TABLE
C
RELEASED BY
3
TERMINAL #1
IDENTIFIER AREA
(D1/2 X E1/2)
E1
E
E2
EXPOSED PAD
Revision 1.5 (03-24-06)
REVISION HISTORY
REVISION
D
2
56X L
56X b 2
4X 45°X0.6 MAX (OPTIONAL)
TOP VIEW
48
DATASHEET
BOTTOM VIEW
A2
A
A1
SIDE VIEW
D2 / E2 VARIATIONS
CATALOG PART
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
AND TOLERANCES ARE:
DECIMAL
±0.1
X.X
X.XX ±0.05
X.XXX ±0.025
THIRD ANGLE PROJECTION
80 ARKAY DRIVE
HAUPPAUGE, NY 11788
USA
ANGULAR
±1°
TITLE
NAME
DATE
S.K.ILIEV
2/06/04
DIM AND TOL PER ASME Y14.5M - 1994
MATERIAL
3-D VIEWS
PRINT WITH "SCALE TO FIT"
DO NOT SCALE DRAWING
Datasheet
USB2.0 PHY IC
FINISH
-
PACKAGE OUTLINE
56 TERMINAL QFN, 8x8mm BODY, 0.5mm PITCH
DRAWN
DWG NUMBER
CHECKED
S.K.ILIEV
S.K.ILIEV
SCALE
2/07/04
Figure 9.2 USB3250 QFN Package Outline and Parameters
REV
MO-56-QFN-8x8
2/07/04
APPROVED
STD COMPLIANCE
1:1
JEDEC: MO-220
C
SHEET
1 OF 1
SMSC GT3200, SMSC USB3250
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETER.
2. POSITION TOLERANCE OF EACH TERMINAL AND EXPOSED PAD IS ± 0.05mm AT MAXIMUM MATERIAL
CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED.