ATMEL ATTINY13 8-bit microcontroller with 1k bytes in-system programmable flash Datasheet

Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
•
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Througput at 20 MHz
High Endurance Non-volatile Memory segments
– 1K Bytes of In-System Self-programmable Flash program memory
– 64 Bytes EEPROM
– 64 Bytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C (see page 6)
– Programming Lock for Self-Programming Flash & EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 4-channel, 10-bit ADC with Internal Voltage Reference
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– 8-pin PDIP/SOIC: Six Programmable I/O Lines
– 20-pad MLF: Six Programmable I/O Lines
Operating Voltage:
– 1.8 - 5.5V for ATtiny13V
– 2.7 - 5.5V for ATtiny13
Speed Grade
– ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode:
• 1 MHz, 1.8V: 240 µA
– Power-down Mode:
• < 0.1 µA at 1.8V
8-bit
Microcontroller
with 1K Bytes
In-System
Programmable
Flash
ATtiny13
ATtiny13V
Summary
Rev. 2535JS–AVR–08/10
1. Pin Configurations
Figure 1-1.
Pinout ATtiny13/ATtiny13V
8-PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
(PCINT4/ADC2) PB4
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/ADC1/T0/PCINT2)
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
15
14
13
12
11
6
7
8
9
10
1
2
3
4
5
VCC
PB2 (SCK/ADC1/T0/PCINT2)
DNC
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
DNC
DNC
GND
DNC
DNC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
DNC
DNC
(PCINT4/ADC2) PB4
20
19
18
17
16
DNC
DNC
DNC
DNC
DNC
20-QFN/MLF
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
10-QFN/MLF
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
DNC
(PCINT4/ADC2) PB4
GND
1
2
3
4
5
10
9
8
7
6
VCC
PB2 (SCK/ADC1/T0/PCINT2)
DNC
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
2
ATtiny13
2535JS–AVR–08/10
ATtiny13
1.1
1.1.1
Pin Descriptions
VCC
Digital supply voltage.
1.1.2
GND
Ground.
1.1.3
Port B (PB5:PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny13 as listed on page 54.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 18-1 on page
115. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
3
2535JS–AVR–08/10
2. Overview
The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
8-BIT DATABUS
STACK
POINTER
SRAM
VCC
PROGRAM
COUNTER
GND
PROGRAM
FLASH
WATCHDOG
OSCILLATOR
CALIBRATED
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
TIMING AND
CONTROL
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
GENERAL
PURPOSE
REGISTERS
INTERRUPT
UNIT
X
Y
Z
PROGRAMMING
LOGIC
ALU
DATA
EEPROM
STATUS
REGISTER
ADC /
ANALOG COMPARATOR
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT B DRIVERS
RESET
CLKI
PB0-PB5
4
ATtiny13
2535JS–AVR–08/10
ATtiny13
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64
bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny13 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.
5
2535JS–AVR–08/10
3. General Information
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
6
ATtiny13
2535JS–AVR–08/10
ATtiny13
4. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
SREG
I
T
H
S
V
N
Z
C
page 9
0x3E
Reserved
–
–
–
–
–
–
–
–
0x3D
SPL
SP[7:0]
0x3C
Reserved
–
page 11
0x3B
GIMSK
–
INT0
PCIE
–
–
–
–
–
page 46
0x3A
GIFR
–
INTF0
PCIF
–
–
–
–
–
page 47
0x39
TIMSK0
–
–
–
–
OCIE0B
OCIE0A
TOIE0
–
page 74
0x38
TIFR0
–
–
–
–
OCF0B
OCF0A
TOV0
0x37
SPMCSR
–
–
–
CTPB
RFLB
PGWRT
PGERS
–
SELFPR-
page 97
Timer/Counter – Output Compare Register A
page 75
0x36
OCR0A
0x35
MCUCR
–
PUD
SE
SM1
SM0
–
ISC01
ISC00
page 32
0x34
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
page 41
0x33
TCCR0B
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
page 72
0x32
TCNT0
Timer/Counter (8-bit)
page 73
0x31
OSCCAL
Oscillator Calibration Register
page 27
0x30
Reserved
–
0x2F
TCCR0A
0x2E
DWDR
COM0A1
DWDR[7:0]
0x2D
Reserved
–
0x2C
Reserved
–
0x2B
Reserved
–
0x2A
Reserved
–
0x29
OCR0B
Timer/Counter – Output Compare Register B
0x28
GTCCR
0x27
Reserved
TSM
COM0A0
–
COM0B1
–
COM0B0
–
–
page 74
–
WGM01
WGM00
page 69
page 96
page 74
–
–
–
PSR10
page 77
CLKPS3
CLKPS2
CLKPS1
CLKPS0
page 28
WDE
WDP2
WDP1
WDP0
page 41
–
CLKPCE
–
–
–
0x26
CLKPR
0x25
Reserved
–
0x24
Reserved
–
0x23
Reserved
–
0x22
Reserved
0x21
WDTCR
0x20
Reserved
–
WDTIF
WDTIE
WDP3
WDCE
–
–
0x1F
Reserved
0x1E
EEARL
0x1D
EEDR
0x1C
EECR
0x1B
Reserved
–
0x1A
Reserved
–
0x19
Reserved
0x18
PORTB
–
–
PORTB5
0x17
DDRB
–
–
0x16
PINB
–
0x15
PCMSK
0x14
DIDR0
–
–
EEPROM Address Register
page 20
EEPROM Data Register
–
–
EEPM1
EEPM0
page 20
EERIE
EEMPE
EEPE
EERE
page 21
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
page 56
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
page 56
–
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 57
–
–
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
page 47
–
–
ADC0D
ADC2D
ADC3D
ADC1D
AIN1D
AIN0D
page 80, page 94
–
0x13
Reserved
–
0x12
Reserved
–
0x11
Reserved
–
0x10
Reserved
–
0x0F
Reserved
–
0x0E
Reserved
–
0x0D
Reserved
–
0x0C
Reserved
–
0x0B
Reserved
–
0x0A
Reserved
–
0x09
Reserved
0x08
ACSR
ACD
ACBG
ACO
ACI
ACIE
–
ACIS1
ACIS0
page 79
0x07
ADMUX
–
REFS0
ADLAR
–
–
–
MUX1
MUX0
page 91
0x06
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
page 92
0x05
ADCH
ADC Data Register High Byte
0x04
ADCL
ADC Data Register Low Byte
0x03
ADCSRB
0x02
Reserved
–
0x01
Reserved
–
0x00
Reserved
–
–
–
ACME
–
–
–
page 93
page 93
ADTS2
ADTS1
ADTS0
page 94
7
2535JS–AVR–08/10
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.ome of the Status Flags are
cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation
the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work
with registers 0x00 to 0x1F only.
8
ATtiny13
2535JS–AVR–08/10
ATtiny13
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
2
BRANCH INSTRUCTIONS
RJMP
k
IJMP
RCALL
k
Relative Jump
PC ← PC + k + 1
None
Indirect Jump to (Z)
PC ← Z
None
2
Relative Subroutine Call
PC ← PC + k + 1
None
3
ICALL
Indirect Call to (Z)
PC ← Z
None
3
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
4
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
1/2/3
CPSE
Rd,Rr
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
1
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
BIT AND BIT-TEST INSTRUCTIONS
9
2535JS–AVR–08/10
Mnemonics
Operands
Description
Operation
Flags
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
#Clocks
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
1
SEC
Set Carry
C←1
C
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
1
Rd, Rr
Copy Register Word
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
None
MOVW
None
1
LDI
Rd, K
Load Immediate
Rd ← K
None
1
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
2
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program Memory
(z) ← R1:R0
None
SPM
IN
Rd, P
In Port
Rd ← P
None
1
OUT
P, Rr
Out Port
P ← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
MCU CONTROL INSTRUCTIONS
10
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/Timer)
For On-chip Debug Only
None
None
1
N/A
ATtiny13
2535JS–AVR–08/10
ATtiny13
6. Ordering Information
Speed (MHz) (3)
10
20
Notes:
Package (2)
Operation Range
1.8 - 5.5
ATtiny13V-10PU
ATtiny13V-10SU
ATtiny13V-10SUR
ATtiny13V-10SSU
ATtiny13V-10SSUR
ATtiny13V-10MU
ATtiny13V-10MUR
ATtiny13V-10MMU
ATtiny13V-10MMUR
8P3
8S2
8S2
S8S1
S8S1
20M1
20M1
10M1
10M1
Industrial
(-40°C to +85°C)(1)
2.7 - 5.5
ATtiny13-20PU
ATtiny13-20SU
ATtiny13-20SUR
ATtiny13-20SSU
ATtiny13-20SSUR
ATtiny13-20MU
ATtiny13-20MUR
ATtiny13-20MMU
ATtiny13-20MMUR
8P3
8S2
8S2
S8S1
S8S1
20M1
20M1
10M1
10M1
Industrial
(-40°C to +85°C)(1)
Power Supply (V)
Ordering Code (4)
1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS).
3. For Speed vs. VCC, see “Speed Grades” on page 117.
4. Code indicators:
– U: matte tin
– R: tape & reel
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Small Outline Package (EIAJ SOIC)
S8S1
8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
20M1
20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
10M1
10-pad, 3 x 3 x 1 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
11
2535JS–AVR–08/10
7. Packaging Information
7.1
8P3
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
SYMBOL
MIN
NOM
A
b2
b3
b
4 PLCS
Side View
L
0.210
NOTE
2
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
0.100 BSC
eA
0.300 BSC
0.115
3
3
e
L
Notes:
MAX
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
ATtiny13
2535JS–AVR–08/10
ATtiny13
7.2
8S2
C
1
E
E1
L
N
θ
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
SIDE VIEW
MAX
NOM
NOTE
A
1.70
A1
0.05
0.25
b
0.35
0.48
4
C
0.15
0.35
4
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
θ
0°
8°
e
Notes: 1.
2.
3.
4.
MIN
2.16
1.27 BSC
2
3
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs aren't included.
Determines the true geometric position.
Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
Package Drawing Contact:
[email protected]
TITLE
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
GPC
STN
4/15/08
DRAWING NO. REV.
8S2
F
13
2535JS–AVR–08/10
7.3
S8S1
3
2
1
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
A2
C
L
SYMBOL
MIN
NOM
MAX
A
–
–
1.75
B
–
–
0.51
C
–
–
0.25
D
–
–
5.00
E
–
–
4.00
e
E
End View
NOTE
1.27 BSC
H
–
–
6.20
L
–
–
1.27
Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
A
ATtiny13
2535JS–AVR–08/10
ATtiny13
7.4
20M1
D
1
Pin 1 ID
2
SIDE VIEW
E
3
TOP VIEW
A2
D2
A1
A
0.08
1
2
Pin #1
Notch
(0.20 R)
3
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
b
L
e
BOTTOM VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
–
0.01
0.05
A2
b
0.18
D
D2
E2
L
0.23
0.30
4.00 BSC
2.45
2.60
2.75
4.00 BSC
2.45
e
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
NOTE
0.20 REF
E
Note:
C
2.60
2.75
0.50 BSC
0.35
0.40
0.55
10/27/04
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
20M1
REV.
A
15
2535JS–AVR–08/10
7.5
10M1
D
y
Pin 1 ID
SIDE VIEW
E
TOP VIEW
A1
A
D1
K
COMMON DIMENSIONS
(Unit of Measure = mm)
1
2
b
E1
e
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
2.90
3.00
3.10
D1
1.40
–
1.75
E
2.90
3.00
3.10
E1
2.20
–
2.70
e
L
BOTTOM VIEW
NOTE
0.50
L
0.30
–
0.50
y
–
–
0.08
K
0.20
–
–
Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5.
2. The terminal #1 ID is a Lasser-marked Feature.
R
16
TITLE
2325 Orchard Parkway 10M1, 10-pad, 3 x 3 x 1.0 mm Body, Lead Pitch 0.50 mm,
San Jose, CA 95131
1.64 x 2.60 mm Exposed Pad, Micro Lead Frame Package
7/7/06
DRAWING NO.
REV.
10M1
A
ATtiny13
2535JS–AVR–08/10
ATtiny13
8. Errata
The revision letter in this section refers to the revision of the ATtiny13 device.
8.1
ATtiny13 Rev. D
• EEPROM can not be written below 1.9 Volt
1. EEPROM can not be written below 1.9 Volt
Writing the EEPROM at VCC below 1.9 volts might fail.
Problem Fix/Workaround
Do not write the EEPROM when VCC is below 1.9 volts.
8.2
ATtiny13 Rev. C
Revision C has not been sampled.
8.3
ATtiny13 Rev. B
•
•
•
•
•
•
8.3.1
Wrong values read after Erase Only operation
High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail
Device may lock for further programming
debugWIRE communication not blocked by lock-bits
Watchdog Timer Interrupt disabled
EEPROM can not be written below 1.9 Volt
Wrong values read after Erase Only operation
At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00).
Problem Fix/Workaround
If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can
be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed.
8.3.2
High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail
Writing to any of these locations and bits may in some occasions fail.
Problem Fix/Workaround
After a writing has been initiated, always observe the RDY/BSY signal. If the writing should
fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed in revision D.
8.3.3
Device may lock for further programming
Special combinations of fuse bits will lock the device for further programming effectively
turning it into an OTP device. The following combinations of settings/fuse bits will cause this
effect:
– 128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.
– 9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.
17
2535JS–AVR–08/10
– 4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.
Problem fix/ Workaround
Avoid the above fuse combinations. Selecting longer start-up time will eliminate the problem.
8.3.4
debugWIRE communication not blocked by lock-bits
When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program memory
and EEPROM data memory can be read even if the lock-bits are set to block further reading
of the device.
Problem fix/ Workaround
Do not ship products with on-chip debug of the tiny13 enabled.
8.3.5
Watchdog Timer Interrupt disabled
If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog
will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in
interrupt only mode. If the Watchdog is configured to reset the device in the watchdog timeout following an interrupt, the device works correctly.
Problem fix / Workaround
Make sure there is enough time to always service the first timeout event before a new
watchdog timeout occurs. This is done by selecting a long enough time-out period.
8.3.6
EEPROM can not be written below 1.9 Volt
Writing the EEPROM at VCC below 1.9 volts might fail.
Problem Fix/Workaround
Do not write the EEPROM when VCC is below 1.9 volts.
8.4
ATtiny13 Rev. A
Revision A has not been sampled.
18
ATtiny13
2535JS–AVR–08/10
ATtiny13
9. Datasheet Revision History
Please note that the referring page numbers in this section refer to the complete document.
9.1
Rev. 2535J-08/10
Added tape and reel part numbers in “Ordering Information” on page 160. Removed text “Not
recommended for new design” from cover page. Updated last page.
9.2
Rev. 2535I-05/08
1. Updated document template, layout and paragraph formats.
2. Updated “Features” on page 1.
3. Created Sections:
– “Calibrated Internal RC Oscillator Accuracy” on page 118
– “Analog Comparator Characteristics” on page 119
4. Updated Sections:
– “System Clock and Clock Options” on page 23
– “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25
– “External Interrupts” on page 45
– “Analog Noise Canceling Techniques” on page 88
– “Limitations of debugWIRE” on page 96
– “Reading Fuse and Lock Bits from Firmware” on page 99
– “Fuse Bytes” on page 103
– “Calibration Bytes” on page 104
– “High-Voltage Serial Programming” on page 108
– “Ordering Information” on page 160
5. Updated Figure:
– “Analog Input Circuitry” on page 87
– “High-voltage Serial Programming Timing” on page 122
6. Moved Figures:
– “Serial Programming Timing” on page 121
– “Serial Programming Waveform” on page 121
– “High-voltage Serial Programming Timing” on page 122
7. Updated Tables:
– “DC Characteristics, TA = -40°C to +85°C” on page 115
– “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless
Otherwise Noted)” on page 121
8. Moved Tables:
– “Serial Programming Instruction Set” on page 107
– “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless
Otherwise Noted)” on page 121
– “High-voltage Serial Programming Characteristics TA = 25°C, VCC = 5.0V ± 10%
(Unless otherwise noted)” on page 122
9. Updated Register Description for Sections:
19
2535JS–AVR–08/10
– “TCCR0A – Timer/Counter Control Register A” on page 69
– “DIDR0 – Digital Input Disable Register 0” on page 94
10. Updated description in Step 1. on page 106.
11. Changed device status to “Not Recommended for New Designs”.
9.3
Rev. 2535H-10/07
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
9.4
Rev. 2535G-01/07
1.
2.
3.
4.
5.
6.
7.
8.
9.
9.5
Revision not published.
Rev. 2535E-10/04
1.
2.
3.
2.
4.
5.
6.
7.
20
Removed Preliminary.
Updated Table 7-1 on page 30, Table 8-1 on page 42,Table 18-8 on page 121.
Removed Note from Table 7-1 on page 30.
Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 79.
Updated “Prescaling and Conversion Timing” on page 83.
Updated Figure 18-4 on page 121.
Updated “DC Characteristics” on page 115.
Updated “Ordering Information” on page 160.
Updated “Packaging Information” on page 161.
Rev. 2535F-04/06
1.
9.6
Updated “Features” on page 1.
Updated “Pin Configurations” on page 2.
Added “Data Retention” on page 6.
Updated “Assembly Code Example(1)” on page 39.
Updated Table 21 in “Alternate Functions of Port B” on page 54.
Updated Bit 5 description in “GIMSK – General Interrupt Mask Register” on page 46.
Updated “ADC Voltage Reference” on page 87.
Updated “Calibration Bytes” on page 104.
Updated “Read Calibration Byte” on page 108.
Updated Table 51 in “Serial Programming Characteristics” on page 121.
Updated Algorithm in “High-Voltage Serial Programming Algorithm” on page 109.
Updated “Read Calibration Byte” on page 112.
Updated values in “External Clock Drive” on page 118.
Updated “Ordering Information” on page 160.
Updated “Packaging Information” on page 161.
Bits EEMWE/EEWE changed to EEMPE/EEPE in document.
Updated “Pinout ATtiny13/ATtiny13V” on page 2.
Updated “Write Fuse Low Bits” in Table 17-13 on page 110, Table 18-3 on page 118.
Added “Pin Change Interrupt Timing” on page 45.
Updated “GIMSK – General Interrupt Mask Register” on page 46.
Updated “PCMSK – Pin Change Mask Register” on page 47.
Updated item 4 in “Serial Programming Algorithm” on page 106.
Updated “High-Voltage Serial Programming Algorithm” on page 109.
ATtiny13
2535JS–AVR–08/10
ATtiny13
8.
9.
10.
11.
12.
9.7
Rev. 2535D-04/04
1.
2.
3.
4.
9.8
C-code examples updated to use legal IAR syntax.
Replaced occurrences of WDIF with WDTIF and WDIE with WDTIE.
Updated “Stack Pointer” on page 11.
Updated “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25.
Updated “OSCCAL – Oscillator Calibration Register” on page 27.
Updated typo in introduction on “Watchdog Timer” on page 37.
Updated “ADC Conversion Time” on page 86.
Updated “Serial Programming” on page 105.
Updated “Electrical Characteristics” on page 115.
Updated “Ordering Information” on page 160.
Removed rev. C from “Errata” on page 166.
Rev. 2535B-01/04
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
9.10
Maximum Speed Grades changed: 12MHz to 10MHz, 24MHz to 20MHz
Updated “Serial Programming Instruction Set” on page 107.
Updated “Speed Grades” on page 117
Updated “Ordering Information” on page 160
Rev. 2535C-02/04
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
9.9
Updated “DC Characteristics” on page 115.
Updated “Typical Characteristics” on page 122.
Updated “Ordering Information” on page 160.
Updated “Packaging Information” on page 161.
Updated “Errata” on page 166.
Updated Figure 2-1 on page 4.
Updated Table 7-1, Table 8-1, Table 14-2 and Table 18-3.
Updated “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25.
Updated the whole “Watchdog Timer” on page 37.
Updated Figure 17-1 on page 105 and Figure 17-2 on page 108.
Updated registers “MCUCR – MCU Control Register”, “TCCR0B – Timer/Counter Control Register B” and “DIDR0 – Digital Input Disable Register 0”.
Updated Absolute Maximum Ratings and DC Characteristics in “Electrical Characteristics” on page 115.
Added “Speed Grades” on page 117
Updated “” on page 120.
Updated “Typical Characteristics” on page 123.
Updated “Ordering Information” on page 160.
Updated “Packaging Information” on page 161.
Updated “Errata” on page 166.
Changed instances of EEAR to EEARL.
Rev. 2535A-06/03
1.
Initial Revision.
21
2535JS–AVR–08/10
Headquarters
International
Atmel Corporation
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Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
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2535JS–AVR–08/10