GSI GS8160E32T-200I 1m x 18, 512k x 36 18mb sync burst sram Datasheet

GS8160E18/32/36T-250/225/200/166/150/133
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
1M x 18, 512K x 36
18Mb Sync Burst SRAMs
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin (Pin 14). Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the Data
Output Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8160E18/32/36T is a DCD (Dual Cycle Deselect) pipelined
synchronous SRAM. SCD (Single Cycle Deselect) versions are also
available. DCD SRAMs pipeline disable commands to the same
degree as read commands. DCD RAMs hold the deselect command
for one full cycle and then begin turning off their outputs just after the
second rising edge of clock.
Functional Description
Applications
Byte Write and Global Write
The GS8160E18/32/36T is an 18,874,368-bit (16,777,216-bit for x32
version) high performance synchronous SRAM with a 2-bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Controls
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Addresses, data I/Os, chip enables (E1, E2, E3), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW)
are synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
Core and Interface Voltages
The GS8160E18/32/36T operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(VDDQ) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Rev: 2.13 11/2004
Pipeline
3-1-1-1
tKQ
tCycle
2.5
4.0
2.7
4.4
3.0
5.0
3.4
6.0
3.8
6.7
4.0
7.5
ns
ns
3.3 V
Curr (x18)
Curr (x32/x36)
280
330
255
300
230
270
200
230
185
215
165
190
mA
mA
2.5 V
Curr (x18)
Curr (x32/x36)
275
320
250
295
230
265
195
225
180
210
165
185
mA
mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.5
5.5
6.0
6.0
6.5
6.5
7.0
7.0
7.5
7.5
8.5
8.5
ns
ns
3.3 V
Curr (x18)
Curr (x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
2.5 V
Curr (x18)
Curr (x32/x36)
175
200
165
190
160
180
150
170
145
165
135
150
mA
mA
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
A
A
E1
E2
NC
NC
BB
BA
E3
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A
A
GS8160E18 100-Pin TQFP Pinout (Package T)
NC
NC
NC
VDDQ
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
FT
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
1M x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.13 11/2004
2/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
A
A
E1
E2
BD
BC
BB
BA
E3
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A
A
GS8160E32 100-Pin TQFP Pinout (Package T)
NC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
NC
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 32
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.13 11/2004
3/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
A
A
E1
E2
BD
BC
BB
BA
E3
VDD
VSS
CK
GW
BW
G
ADSC
ADSP
ADV
A
A
GS8160E36 100-Pin TQFP Pinout (Package T)
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
FT
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.13 11/2004
4/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
TQFP Pin Description
Symbol
Type
Description
A 0, A 1
I
Address field LSBs and Address Counter preset Inputs
A
I
Address Input
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
NC
—
No Connect
BW
I
Byte Write—Writes all enabled bytes; active low
BA, BB, BC, BD
I
Byte Write Enable for DQA, DQB Data I/Os; active low
CK
I
Clock Input Signal; active high
GW
I
Global Write Enable—Writes all bytes; active low
E1
I
Chip Enable; active low
E2
I
Chip Enable; active high
E3
I
Chip Enable; active low
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active low
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller); active low
ZZ
I
Sleep Mode control; active high
LBO
I
Linear Burst Order mode; active low
VDD
I
Core power supply
VSS
I
I/O and Core Ground
VDDQ
I
Output driver power supply
Rev: 2.13 11/2004
5/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
GS8160E18/32/36 Block Diagram
Register
A0–An
D
Q
A0
A0
D0
A1
Q0
A1
D1
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
Register
D
36
Q
BB
36
4
Register
D
Q
D
Q
D
Q
Register
Register
D
Q
Register
BC
BD
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
FT
G
ZZ
0
Power Down
DQx1–DQx9
Control
Note: Only x36 version shown for simplicity.
Rev: 2.13 11/2004
6/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Mode Pin Functions
Mode Name
Pin Name
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
State
Function
L
Linear Burst
H
Interleaved Burst
L
Flow Through
H or NC
Pipeline
L or NC
Active
H
Standby, IDD = ISB
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
1st address
00
01
10
11
2nd address
01
10
11
00
2nd address
01
00
11
10
3rd address
10
11
00
01
3rd address
10
11
00
01
4th address
11
00
01
10
4th address
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.13 11/2004
7/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 2.13 11/2004
8/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key5
E1
E2
Deselect Cycle, Power Down
None
X
H
X
X
Deselect Cycle, Power Down
None
X
L
F
Deselect Cycle, Power Down
None
X
L
Read Cycle, Begin Burst
External
R
Read Cycle, Begin Burst
External
Write Cycle, Begin Burst
ADV
W3
DQ4
L
X
X
High-Z
L
X
X
X
High-Z
F
H
L
X
X
High-Z
L
T
L
X
X
X
Q
R
L
T
H
L
X
F
Q
External
W
L
T
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
X
H
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
X
H
H
H
T
D
ADSP ADSC
Write Cycle, Suspend Burst
Current
H
X
X
H
H
T
D
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 2.13 11/2004
9/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Simplified State Diagram
X
Deselect
W
R
Simple Burst Synchronous Operation
Simple Synchronous Operation
W
X
R
R
First Write
CW
First Read
CR
CR
W
X
R
R
X
Burst Write
Burst Read
X
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)
control inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 2.13 11/2004
10/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Simplified State Diagram with G
X
Deselect
W
R
W
X
R
R
First Write
CR
CW
W
CW
W
X
First Read
X
CR
R
Burst Write
R
CR
CW
W
Burst Read
X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 2.13 11/2004
11/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
–0.5 to 4.6
V
VI/O
Voltage on I/O Pins
–0.5 to VDDQ +0.5 (≤ 4.6 V max.)
V
VIN
Voltage on Other Input Pins
–0.5 to VDD +0.5 (≤ 4.6 V max.)
V
IIN
Input Current on Any Pin
+/–20
mA
IOUT
Output Current on Any I/O Pin
+/–20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
–55 to 125
o
TBIAS
Temperature Under Bias
–55 to 125
o
C
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
3.3 V Supply Voltage
VDD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
Notes
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 2.13 11/2004
12/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
VDDQ3 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
2.0
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.8
V
1
VDDQ I/O Input High Voltage
VIHQ
2.0
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.8
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
VDD Input High Voltage
VIH
0.6*VDD
—
VDD + 0.3
V
1
VDD Input Low Voltage
VIL
–0.3
—
0.3*VDD
V
1
VDDQ I/O Input High Voltage
VIHQ
0.6*VDD
—
VDDQ + 0.3
V
1,3
VDDQ I/O Input Low Voltage
VILQ
–0.3
—
0.3*VDD
V
1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
2
Ambient Temperature (Industrial Range Versions)
TA
–40
25
85
°C
2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 2.13 11/2004
13/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
50% tKC
VDD + 2.0 V
VSS
50%
50%
VDD
VSS – 2.0 V
50% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Input/Output Capacitance
CI/O
VOUT = 0 V
6
7
pF
Note:
These parameters are sample tested.
AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output reference level
VDDQ/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
50Ω
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
Rev: 2.13 11/2004
14/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IIN1
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
100 uA
FT Input Current
IIN2
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–100 uA
–1 uA
1 uA
1 uA
Output Leakage Current
IOL
Output Disable, VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH2
IOH = –8 mA, VDDQ = 2.375 V
1.7 V
—
Output High Voltage
VOH3
IOH = –8 mA, VDDQ = 3.135 V
2.4 V
—
Output Low Voltage
VOL
IOL = 8 mA
—
0.4 V
Rev: 2.13 11/2004
15/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
Rev: 2.13 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
16/25
—
Device Deselected;
All other inputs
≥ VIH or ≤ VIL
Deselect
Current
180
20
260
15
165
10
20
IDD
IDDQ
IDD
IDDQ
IDD
IDDQ
ISB
Pipeline
Flow
Through
Pipeline
IDD
60
85
IDD
Pipeline
Flow
Through
20
ISB
Flow
Through
Pipeline
Flow
Through
165
10
260
20
180
20
290
40
0
to
70°C
290
30
IDD
IDDQ
IDD
IDDQ
IDD
IDDQ
IDD
IDDQ
IDD
Symbol
IDDQ
Flow
Through
Pipeline
Flow
Through
Pipeline
Mode
65
90
30
30
175
10
270
15
190
20
300
30
175
10
270
20
190
20
300
40
–40
to
85°C
-250
60
80
20
20
155
10
235
15
170
20
265
30
155
10
235
20
170
20
265
35
65
85
30
30
165
10
245
15
180
20
275
30
165
10
245
20
180
20
275
35
–40
to
85°C
-225
0
to
70°C
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
—
ZZ ≥ VDD – 0.2 V
(x18)
(x32/
x36)
(x18)
(x32/
x36)
Standby
Current
2.5 V
Operating
Current
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
Device Selected;
All other inputs
≥VIH or ≤ VIL
Output open
Operating
Current
3.3 V
Test Conditions
Parameter
Operating Currents
50
75
20
20
150
10
215
15
165
15
240
25
150
10
215
15
165
15
240
30
0
to
70°C
55
80
30
30
160
10
225
15
175
15
250
25
160
10
225
15
175
15
250
30
–40
to
85°C
-200
50
64
20
20
140
10
185
10
155
15
205
20
140
10
185
15
155
15
205
25
0
to
70°C
55
70
30
30
150
10
195
10
165
15
215
20
150
10
195
15
165
15
215
25
–40
to
85°C
-166
50
60
20
20
135
10
170
10
150
15
190
20
135
10
170
15
150
15
190
25
0
to
70°C
55
65
30
30
145
10
180
10
160
15
200
20
145
10
180
15
160
15
200
25
–40
to
85°C
-150
45
50
20
20
125
10
155
10
140
10
170
15
125
10
155
10
140
10
170
20
0
to
70°C
50
55
30
30
135
10
165
10
150
10
180
15
135
10
165
10
150
10
180
20
–40
to
85°C
-133
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Unit
GS8160E18/32/36T-250/225/200/166/150/133
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
AC Electrical Characteristics
Pipeline
Flow
Through
Parameter
Symbol
Clock Cycle Time
-250
-225
-200
-166
-150
-133
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tKC
4.0
—
4.4
—
5.0
—
6.0
—
6.7
—
7.5
—
ns
Clock to Output Valid
tKQ
—
2.5
—
2.7
—
3.0
—
3.4
—
3.8
—
4.0
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
1
Clock to Output in Low-Z
tLZ
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Setup time
tS
1.2
—
1.3
—
1.4
—
1.5
—
1.5
—
1.5
—
ns
Hold time
tH
0.2
—
0.3
—
0.4
—
0.5
—
0.5
—
0.5
—
ns
Clock Cycle Time
tKC
5.5
—
6.0
—
6.5
—
7.0
—
7.5
—
8.5
—
ns
Clock to Output Valid
tKQ
—
5.5
—
6.0
—
6.5
—
7.0
—
7.5
—
8.5
ns
Clock to Output Invalid
tKQX
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Clock to Output in Low-Z
tLZ1
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Setup time
tS
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Hold time
tH
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
Clock HIGH Time
tKH
1.3
—
1.3
—
1.3
—
1.3
—
1.5
—
1.7
—
ns
Clock LOW Time
tKL
1.5
—
1.5
—
1.5
—
1.5
—
1.7
—
2
—
ns
Clock to Output in
High-Z
tHZ1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
—
2.3
—
2.5
—
3.2
—
3.5
—
3.8
—
4.0
ns
G to output in Low-Z
tOLZ1
0
—
0
—
0
—
0
—
0
—
0
—
ns
G to output in High-Z
tOHZ1
—
2.3
—
2.5
—
3.0
—
3.0
—
3.0
—
3.0
ns
ZZ setup time
tZZS2
5
—
5
—
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH2
1
—
1
—
1
—
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
20
—
20
—
20
—
ns
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 2.13 11/2004
17/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Pipeline Mode Timing
Begin
Read A
Cont
Deselect Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Cont
Deselect Deselect
tKL
tKH
tKC
CK
ADSP
tS
ADSC initiated read
tH
ADSC
tS
tH
ADV
tS
tH
Ao–An
A
B
C
tS
GW
tS
tH
BW
tH
tS
Ba–Bd
tS
Deselected with E1
tH
E1
tS
E2 and E3 only sampled with ADSC
tH
E2
tS
tH
E3
G
tS
tOE
DQa–DQd
Hi-Z
Rev: 2.13 11/2004
tOHZ
Q(A)
tKQ
tH
D(B)
tHZ
tLZ
tKQX
Q(C)
Q(C+1)
18/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q(C+2)
Q(C+3)
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Flow Through Mode Timing
Begin
Read A
Cont
Deselect Write B
Read C
Read C+1 Read C+2 Read C+3 Read C
Deselect
tKL
tKH
tKC
CK
ADSP
Fixed High
tS
tH
tS
tH
ADSC
initiated read
ADSC
tH
tS
tS
tH
ADV
tS
tH
Ao–An
A
B
C
tS
tH
GW
tS
tH
BW
tH
tS
Ba–Bd
tS
Deselected with E1
tH
E1 masks ADSP
E1
tS
tH
E2 and E3 only sampled with ADSP and ADSC
E2
tS
tH
E1 masks ADSP
E3
G
tH
tS
tOE
tKQ
DQa–DQd
Rev: 2.13 11/2004
tOHZ
Q(A)
tKQX
tHZ
tLZ
D(B)
Q(C)
Q(C+1)
Q(C+2)
19/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Q(C+3)
Q(C)
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH
tKC
tKL
CK
Setup
Hold
ADSP
ADSC
tZZR
tZZS
tZZH
ZZ
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs (like this one) do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 2.13 11/2004
20/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
TQFP Package Drawing (Package T)
L
Min. Nom. Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
—
0.20
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
—
0.65
—
L
Foot Length
0.45
0.60
0.75
L1
Lead Length
—
1.00
—
Y
Coplanarity
θ
Lead Angle
e
D
D1
Description
c
Pin 1
Symbol
L1
θ
b
A1
A2
0.10
Y
0°
—
7°
E1
E
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
Rev: 2.13 11/2004
21/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
1M x 18
GS8160E18T-250
DCD Pipeline/Flow Through
TQFP
250/5.5
C
1M x 18
GS8160E18T-225
DCD Pipeline/Flow Through
TQFP
225/6
C
1M x 18
GS8160E18T-200
DCD Pipeline/Flow Through
TQFP
200/6.5
C
1M x 18
GS8160E18T-166
DCD Pipeline/Flow Through
TQFP
166/7
C
1M x 18
GS8160E18T-150
DCD Pipeline/Flow Through
TQFP
150/7.5
C
1M x 18
GS8160E18T-133
DCD Pipeline/Flow Through
TQFP
133/8.5
C
512K x 32
GS8160E32T-250
DCD Pipeline/Flow Through
TQFP
250/5.5
C
512K x 32
GS8160E32T-225
DCD Pipeline/Flow Through
TQFP
225/6
C
512K x 32
GS8160E32T-200
DCD Pipeline/Flow Through
TQFP
200/6.5
C
512K x 32
GS8160E32T-166
DCD Pipeline/Flow Through
TQFP
166/7
C
512K x 32
GS8160E32T-150
DCD Pipeline/Flow Through
TQFP
150/7.5
C
512K x 32
GS8160E32T-133
DCD Pipeline/Flow Through
TQFP
133/8.5
C
512K x 36
GS8160E36T-250
DCD Pipeline/Flow Through
TQFP
250/5.5
C
512K x 36
GS8160E36T-225
DCD Pipeline/Flow Through
TQFP
225/6
C
512K x 36
GS8160E36T-200
DCD Pipeline/Flow Through
TQFP
200/6.5
C
512K x 36
GS8160E36T-166
DCD Pipeline/Flow Through
TQFP
166/7
C
512K x 36
GS8160E36T-150
DCD Pipeline/Flow Through
TQFP
150/7.5
C
512K x 36
GS8160E36T-133
DCD Pipeline/Flow Through
TQFP
133/8.5
C
1M x 18
GS8160E18T-250I
DCD Pipeline/Flow Through
TQFP
250/5.5
I
1M x 18
GS8160E18T-225I
DCD Pipeline/Flow Through
TQFP
225/6
I
1M x 18
GS8160E18T-200I
DCD Pipeline/Flow Through
TQFP
200/6.5
I
1M x 18
GS8160E18T-166I
DCD Pipeline/Flow Through
TQFP
166/7
I
1M x 18
GS8160E18T-150I
DCD Pipeline/Flow Through
TQFP
150/7.5
I
1M x 18
GS8160E18T-133I
DCD Pipeline/Flow Through
TQFP
133/8.5
I
512K x 32
GS8160E32T-250I
DCD Pipeline/Flow Through
TQFP
250/5.5
I
Status
512K x 32
GS8160E32T-225I
DCD Pipeline/Flow Through
TQFP
225/6
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 2.13 11/2004
22/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number1
Type
Package
Speed2
(MHz/ns)
TA3
512K x 32
GS8160E32T-200I
DCD Pipeline/Flow Through
TQFP
200/6.5
I
512K x 32
GS8160E32T-166I
DCD Pipeline/Flow Through
TQFP
166/7
I
512K x 32
GS8160E32T-150I
DCD Pipeline/Flow Through
TQFP
150/7.5
I
512K x 32
GS8160E32T-133I
DCD Pipeline/Flow Through
TQFP
133/8.5
I
512K x 36
GS8160E36T-250I
DCD Pipeline/Flow Through
TQFP
250/5.5
I
512K x 36
GS8160E36T-225I
DCD Pipeline/Flow Through
TQFP
225/6
I
512K x 36
GS8160E36T-200I
DCD Pipeline/Flow Through
TQFP
200/6.5
I
512K x 36
GS8160E36T-166I
DCD Pipeline/Flow Through
TQFP
166/7
I
512K x 36
GS8160E36T-150I
DCD Pipeline/Flow Through
TQFP
150/7.5
I
Status
512K x 36
GS8160E36T-133I
DCD Pipeline/Flow Through
TQFP
133/8.5
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18T-150IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 2.13 11/2004
23/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
GS8160E18T-150IT 1.00 9/
1999A;GS8160E18T-150IT
2.00 1/1999B
GS8160E18T- 2.00 11/
1999B;GS8160E18T 2.01 1/
2000C
Types of Changes
Format or Content
Content
• Converted from 0.25u 3.3V process to 0.18u 2.5V process.
Master File Rev B
• Added x72 Pinout.
• Added GSI Logo.
Format
• Changed Flow-Through Read-Write cycle Timing Diagram for
accuracy
• Changed pin description in TQFP to match order of pins in
pinout.
GS8160E18T 2.01 1/
2000C;GS8160E18 T 2.02 1/
2000D
• Front page; Features - changed 2.5V I/O supply to 2.5V
or3.3V I/O supply; Core and Interface voltages - Changed
paragraph to include information for 3.3V;Completeness
• Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness.
• Recommended Operating Conditions;Changed: I/O Supply
Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from
VDD +0.3 to 3.6; Same page - took out Note 1;Completeness
• Electrical Characteristics - Added second Output High Voltage
line to table; completeness.
• Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
GS18/362.0 1/2000DGS18/
362.03 2/2000E
GS18/362.03 2/2000E;
8160E18_r2_04
Page;Revisions;Reason
Content
• Changed the value of ZZ recovery in the AC Electrical
Characteristics table on page 15 from 20 ns to 100 ns
• Added 225 MHz speed bin
• Updated Pg. 1 table, AC Characteristics table, and Operating
Currents table to match 815xxx
• Updated format to comply with Technical Publications
standards
8160E18_r2_04;
8160E18_r2_05
Content/Format
8160E18_r2_05;
8160E18_r2_06
Content
• Updated Capitance table—removed Input row and changed
Output row to I/O
8160E18_r2_06;
8160E18_r2_07
Content
• Updated Features list on page 1
• Completely reworked table on page 1
• Updated Mode Pin Functions table on page 7
Content
• Added 3.3 V references to entire document
• Updated Operating Conditions table
• Added Pin 56 to Pin Description table
• Updated Operating Currents table and added note
• Updated Application Tips paragraph
• Updated table on page 1; added power numbers
8160E18_r2_07;
8160E18_r2_08
Rev: 2.13 11/2004
24/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
GS8160E18/32/36T-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
Content
• Updated Operating Currents table
• Updated table on page 1; updated power numbers
• Updated Recommended Operating Conditions table (added
VDDQ references)
Content
• Updated table on page 1
• Created recommended operating conditions tables on pages
12 and 13
• Updated AC Electrical Characteristics table
• Added Sleep mode description on page 23
• Updated Ordering Information for 225 MHz part (changed
from 7ns to 6.5 ns)
• Added 250 MHz speed bin
• Deleted 180 MHz speed bin
8160E18_r2_10;
8160E18_r2_11
Content
• Updated AC Characteristics table
• Updated FT power numbers
• Updated ZZ recovery time diagram
• Updated Mb references from 16Mb to 18Mb
• Updated AC Test Conditions table and removed Output Load
2 diagram
8160E18_r2_11;
8160E18_r2_12
Content
• Removed pin locations from pin description table
• Removed Preliminary banner
8160E18_r2_12;
8160E18_r2_13
Format/Content
8160E18_r2_08;
8160E18_r2_09
8160E18_r2_09;
8160E18_r2_10
Rev: 2.13 11/2004
• Updated format
• Updated timing diagrams
25/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology
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