ON MC14049UBDT Hex buffer Datasheet

MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic–level conversion using only one
supply voltage, VDD. The input–signal high level (VIH) can exceed the
VDD supply voltage for logic–level conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOS–to–TTL/DTL
converters (VDD = 5.0 V, VOL 0.4 V, IOL ≥ 3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
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MARKING
DIAGRAMS
v
•
•
•
•
•
•
16
PDIP–16
P SUFFIX
CASE 648
High Source and Sink Currents
High–to–Low Level Converter
Supply Voltage Range = 3.0 V to 18 V
Meets JEDEC UB Specifications
VIN can exceed VDD
Improved ESD Protection on All Inputs
MC14049UBCP
AWLYYWW
1
16
SOIC–16
D SUFFIX
CASE 751B
14049U
AWLYWW
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Parameter
Symbol
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin
Input Voltage Range
(DC or Transient)
– 0.5 to +18.0
V
Vout
Output Voltage Range
(DC or Transient)
TSSOP–16
DT SUFFIX
CASE 948F
1
16
– 0.5 to VDD +0.5
V
Iin
Input Current
(DC or Transient) per Pin
± 10
mA
Iout
Output Current
(DC or Transient) per Pin
+45
mA
PD
Power Dissipation,
per Package (Note 3.)
Plastic
SOIC
SOEIAJ–16
F SUFFIX
CASE 966
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
825
740
ORDERING INFORMATION
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
Device
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
All Packages: See Figure 4.
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
v
v
1
Package
Shipping
MC14049UBCP
PDIP–16
2000/Box
MC14049UBD
SOIC–16
2400/Box
MC14049UBDR2
SOIC–16
2500/Tape & Reel
TSSOP–16
96/Rail
MC14049UBDT
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the VSS pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high–impedance circuit. For proper operation, the ranges VSS
Vin
18 V and VSS
Vout
VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
v
MC14049U
AWLYWW
1
mW
TA
v
14
049U
ALYW
MC14049UBDTR2 TSSOP–16 2500/Tape & Reel
MC14049UBF
SOEIAJ–16
See Note 1.
MC14049UBFEL
SOEIAJ–16
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Publication Order Number:
MC14049UB/D
MC14049UB
PIN ASSIGNMENT
LOGIC DIAGRAM
MC14049UB
VDD
1
16
NC
OUTA
2
15
OUTF
INA
3
14
INF
OUTB
4
13
NC
INB
5
12
OUTE
OUTC
6
11
INE
INC
7
10
OUTD
VSS
8
9
3
2
5
4
7
6
9
10
11
12
14
15
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
VDD
MC14049UB
IND
NC = NO CONNECTION
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
VSS
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
“0” Level
VIL
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
2.25
4.50
6.75
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
—
—
—
4.0
8.0
12.5
2.75
5.50
8.25
—
—
—
4.0
8.0
12.5
—
—
—
5.0
10
15
– 1.6
– 1.6
– 4.7
—
—
—
– 1.25
– 1.3
– 3.75
– 2.5
– 2.6
– 10
—
—
—
– 1.0
– 1.0
– 3.0
—
—
—
IOL
5.0
10
15
3.75
10
30
—
—
—
3.2
8.0
24
6.0
16
40
—
—
—
2.6
6.6
19
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance (Vin = 0)
Cin
—
—
—
—
10
20
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
1.0
2.0
4.0
—
—
—
0.002
0.004
0.006
1.0
2.0
4.0
—
—
—
30
60
120
µAdc
IT
5.0
10
15
Vin = 0 or VDD
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
“1” Level
VIH
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Source
Sink
Total Supply Current (5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (1.8 µA/kHz) f + IDD
IT = (3.5 µA/kHz) f + IDD
IT = (5.3 µA/kHz) f + IDD
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
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2
µAdc
MC14049UB
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SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise Time
tTLH = (0.8 ns/pF) CL + 60 ns
tTLH = (0.3 ns/pF) CL + 35 ns
tTLH = (0.27 ns/pF) CL + 26.5 ns
tTLH
Output Fall Time
tTHL = (0.3 ns/pF) CL + 25 ns
tTHL = (0.12 ns/pF) CL + 14 ns
tTHL = (0.1 ns/pF) CL + 10 ns
tTHL
Propagation Delay Time
tPLH = (0.38 ns/pF) CL + 61 ns
tPLH = (0.20 ns/pF) CL + 30 ns
tPLH = (0.11 ns/pF) CL + 24.5 ns
tPLH
Propagation Delay Time
tPHL = (0.38 ns/pF) CL + 11 ns
tPHL = (0.12 ns/PF) CL + 9 ns
tPHL = (0.11 ns/pF) CL + 4.5 ns
tPHL
VDD
Vdc
Min
Typ (8.)
Max
5.0
10
15
—
—
—
100
50
40
160
100
60
5.0
10
15
—
—
—
40
20
15
60
40
30
5.0
10
15
—
—
—
80
40
30
120
65
50
5.0
10
15
—
—
—
30
15
10
60
30
20
ns
ns
ns
ns
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Vout , OUTPUT VOLTAGE (Vdc)
18
15
10
5
VDD = 15 Vdc
VDD = 10 Vdc
– 55°C
VDD = 5 Vdc
+125°C
5
Unit
10
Vin, INPUT VOLTAGE (Vdc)
15
18
Figure 1. Typical Voltage Transfer Characteristics versus Temperature
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3
MC14049UB
VDD
VDD
1
1
IOH
8
IOL
VOH
VSS
8
VDS = VOH – VDD
VDD = VOL
160
I OL, OUTPUT SINK CURRENT (mAdc)
0
I OH , OUTPUT SOURCE CURRNT (mAdc)
VOL
VSS
VGS = 5.0 Vdc
– 10
VGS = 15 Vdc
120
– 20
VGS = 10 Vdc
– 30
– 40
VGS = 15 Vdc
– 50
– 10
MAXIMUM CURRENT LEVEL
– 8.0
– 6.0
– 4.0
– 2.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
MAXIMUM CURRENT LEVEL
40
VGS = 5.0 Vdc
0
0
VGS = 10 Vdc
80
0
Figure 2. Typical Output Source Characteristics
2.0
4.0
6.0
8.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)
10
Figure 3. Typical Output Sink Characteristics
VDD
PD , MAXIMUM POWER DISSIPATION (mW)
PER PACKAGE
1
PULSE
GENERATOR
1200
1100
1000
Vout
Vin
8
900
825
800
740
700
600
20 ns
CL
20 ns
VDD
90%
50%
INPUT
(P) PDIP
500
400
VSS
10%
300
200
100
0
25
175 mW (P)
120 mW (D)
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
VSS
tPLH
tPHL
(D) SOIC
150
175
Figure 4. Ambient Temperature Power Derating
OUTPUT
VOH
90%
50%
10%
tTHL
tTLH
Figure 5. Switching Time Test Circuit
and Waveforms
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4
VOL
MC14049UB
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
–T–
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
M
T B
S
A
S
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5
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14049UB
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
DETAIL E
H
D
G
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC14049UB
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
16
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
0.78
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.031
MC14049UB
ON Semiconductor and
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8
MC14049UB/D