NTD60N02R Power MOSFET 62 A, 24 V, N−Channel, DPAK Features • Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Optimized for High Side Switching Requirements in High−Efficiency DC−DC Converters Pb−Free Packages are Available http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 24 V 8.4 m @ 10 V 62 A MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 24 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc Thermal Resistance Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current Continuous @ TC = 25°C, Chip Continuous @ TC = 25°C, Limited by Package Continuous @ TA = 25°C, Limited by Wires G RJC PD 2.6 58 °C/W W ID ID ID 62 50 32 A A A Thermal Resistance Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RJA PD ID 80 1.87 10.5 C/W W A Thermal Resistance Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RJA PD ID 120 1.25 8.5 °C/W W A TJ, and Tstg −55 to 175 °C EAS 60 mJ Operating and Storage Temperature Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10.0 Vdc, IL = 11 Apk, L = 1.0 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds S 4 4 4 TL 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 0.5 in sq drain pad size. 2. When surface mounted to an FR4 board using the minimum recommended pad size. 1 2 3 1 2 1 3 2 3 CASE 369C CASE 369AA CASE 369D DPAK DPAK DPAK (Surface Mount) (Surface Mount) (Straight Lead) STYLE 2 STYLE 2 STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain YWW T60 N02R Rating N−Channel D 2 1 3 Drain Gate Source 4 Drain YWW T60 N02R • • • • • 1 2 3 Gate Drain Source Y = Year WW = Work Week 60N02R = Device Code ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Semiconductor Components Industries, LLC, 2004 December, 2004 − Rev. 10 1 Publication Order Number: NTD60N02R/D NTD60N02R ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 24 − 27.5 25.5 − − − − − − 1.5 10 − − ±100 1.0 − 1.5 4.1 2.0 − − − − 11.2 8.4 8.2 12.5 10.5 − gFS − 27 − Mhos pF OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.5 Vdc, ID = 15 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 31 Adc) RDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 15 Adc) (Note 3) Vdc mV/°C m DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 20 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance Ciss − 1000 1330 Coss − 480 640 Crss − 180 225 td(on) − 7.0 − tr − 33 − td(off) − 19 − SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 Vdc, VDD = 10 Vdc, ID = 31 Adc, RG = 3.0 ) Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 31 Adc, VDS = 10 Vdc) (Note 3) ns tf − 9.0 − QT − 9.5 − QGS − 2.2 − QGD − 5.0 − VSD − − − 0.88 1.15 0 80 0.80 1.2 − − Vdc trr − 29.1 − ns ta − 13.6 − tb − 15.5 − Qrr − 0.02 − nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) (IS = 31 Adc, VGS = 0 Vdc) Ad VGS = 0 Vdc, Vd TJ = 125°C) 125 C) (IS = 15 Adc, Reverse Recovery Time (IS = 31 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 C NTD60N02R TYPICAL CHARACTERISTICS VGS = 10 V 120 TJ = 25°C 100 4.5 V 4.2 V 4.0 V 80 3.8 V 3.6 V 3.4 V 3.2 V 3.0 V 2.8 V 60 40 20 2.6 V 0 2.4 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE () ID, DRAIN CURRENT (A) 5.0 V 8.0 V 6.0 V 120 2 4 6 8 80 60 40 TJ = 175°C TJ = 25°C 20 TJ = −55°C 0 2 Figure 2. Transfer Characteristics 0.03 0.02 0.01 4 2 6 8 10 0.05 TJ = 25°C 0.04 0.03 0.02 VGS = 4.5 V VGS = 10 V 0.01 0 20 40 60 VGS, GATE−TO−SOURCE VOLTAGE (V) 80 100 120 140 ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 100000 2.0 ID = 31 A VGS = 10 V VGS = 0 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 8 Figure 1. On−Region Characteristics 0.04 10000 1.6 1.4 1.2 1.0 TJ = 175°C 1000 100 TJ = 100°C 0.8 0.6 −50 6 VGS, GATE−TO−SOURCE VOLTAGE (V) ID = 62 A TJ = 25°C 1.8 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.05 0 VDS 10 V 100 0 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE () ID, DRAIN CURRENT (A) 140 −25 0 25 50 75 100 125 150 175 10 0 6 12 18 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 24 NTD60N02R C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (V) TJ = 25°C Ciss 1500 VGS = 0 V VDS = 0 V Ciss 1000 Crss Coss 500 Crss 0 10 5 VGS 0 5 VDS 10 15 20 5 20 QT 4 QGS 16 VGS QDS 3 12 VDS 2 8 1 0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 2000 4 ID = 31 A TJ = 25°C 0 4 2 6 8 0 10 Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 1000 80 tr tf td(off) 10 td(on) VGS = 0 V TJ = 25°C 70 60 50 40 30 20 10 1 1 10 100 0 0.2 Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 0.4 0.6 0.8 1.0 10 s SINGLE PULSE TC = 25°C 100 s 10 1 ms 10 ms RDS(ON) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.4 1.6 Figure 10. Diode Forward Voltage versus Current VGS = 20 V 1 1.2 VSD, SOURCE−TO−DRAIN VOLTAGE (V) RG, GATE RESISTANCE () ID, DRAIN CURRENT (A) t, TIME (ns) 100 IS, SOURCE CURRENT (A) VDD = 10 V ID = 31 A VGS = 10 V dc 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 1.8 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) NTD60N02R 1.0 D = 0.5 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 SINGLE PULSE 0.01 0.00001 0.0001 t1 t2 DUTY CYCLE, D = t1/t2 0.001 0.01 t, TIME (s) 0.1 RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RJC(t) 1 10 Figure 12. Thermal Response ORDERING INFORMATION Package Shipping† DPAK−3 75 Units / Rail NTD60N02RG DPAK−3 (Pb−Free) 75 Units / Rail NTD60N02RT4 DPAK−3 2500 / Tape & Reel NTD60N02RT4G DPAK−3 (Pb−Free) 2500 / Tape & Reel NTD60N02R−001 DPAK−3 Straight Lead 75 Units / Rail NTD60N02R−1G DPAK−3 Straight Lead (Pb−Free) 75 Units / Rail NTD60N02R−032 DPAK−3 Straight Lead (3.2 ± 0.5 mm) 75 Units / Rail NTD60N02R−032G DPAK−3 Straight Lead (3.2 ± 0.5 mm) (Pb−Free) 75 Units / Rail Order Number NTD60N02R †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTD60N02R PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D G 2 PL 0.13 (0.005) M T INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD60N02R PACKAGE DIMENSIONS DPAK CASE 369AA−01 ISSUE O C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE −T− E R 4 Z A S 1 2 DIM A B C D E F J L R S U V Z 3 U F J L D STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 2 PL 0.13 (0.005) M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.033 0.045 0.018 0.023 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− T SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.88 0.46 0.61 0.83 1.14 0.46 0.58 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD60N02R PACKAGE DIMENSIONS DPAK CASE 369D−01 ISSUE B C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− 3 PL 0.13 (0.005) M T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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