TI1 CDCEL913PWR Programmable 1-pll vcxo clock synthesizer Datasheet

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CDCE913, CDCEL913
SCAS849F – JUNE 2007 – REVISED APRIL 2015
CDCEx913 Programmable 1-PLL VCXO Clock Synthesizer
With 1.8-V, 2.5-V, and 3.3-V Outputs
1 Features
3 Description
•
The CDCE913 and CDCEL913 devices are modular
PLL-based,
low-cost,
high-performance,
programmable clock synthesizers. They generate up
to three output clocks from a single input frequency.
Each output can be programmed in-system for any
clock frequency up to 230 MHz, using the integrated
configurable PLL.
1
•
•
•
•
•
•
•
•
•
•
Member of Programmable Clock Generator
Family
– CDCE913/CDCEL913: 1-PLL, 3 Outputs
– CDCE925/CDCEL925: 2-PLL, 5 Outputs
– CDCE937/CDCEL937: 3-PLL, 7 Outputs
– CDCE949/CDCEL949: 4-PLL, 9 Outputs
In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Settings
Flexible Input Clocking Concept
– External Crystal: 8 MHz to 32 MHz
– On-Chip VCXO: Pull Range ±150 ppm
– Single-Ended LVCMOS up to 160 MHz
Free Selectable Output Frequency up to 230 MHz
Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typical 50 ps)
Separate Output Supply Pins
– CDCE913: 3.3 V and 2.5 V
– CDCEL913: 1.8 V
Flexible Clock Driver
– Three User-Definable Control Inputs
[S0/S1/S2], for Example, SSC Selection,
Frequency Switching, Output Enable, or Power
Down
– Generates Highly Accurate Clocks for Video,
Audio, USB, IEEE1394, RFID, Bluetooth®,
WLAN, Ethernet, and GPS
– Generates Common Clock Frequencies Used
With TI-DaVinci™, OMAP™, DSPs
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
1.8-V Device Power Supply
Wide Temperature Range –40°C to 85°C
Packaged in TSSOP
Development and Programming Kit for Easy PLL
Design and Programming (TI Pro-Clock™)
The CDCx913 has separate output supply pins,
VDDOUT, which is 1.8 V for CDCEL913 and 2.5 V to
3.3 V for CDCE913.
The input accepts an external crystal or LVCMOS
clock signal. A selectable on-chip VCXO allows
synchronization of the output frequency to an external
control signal.
The PLL supports SSC (spread-spectrum clocking)
for better electromagnetic interference (EMI)
performance.
The
device
supports
nonvolatile
EEPROM
programming for easy customization of the device to
the application. All device settings are programmable
through the SDA/SCL bus, a 2-wire serial interface.
The CDCx913 operates in a 1.8-V environment. It
operates in a temperature range of –40°C to 85°C.
Device Information(1)
PART NUMBER
CDCE913
CDCEL913
PACKAGE
TSSOP (14)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Ethernet
PHY
USB
Controller
CDCE(L)9xx
Clock
25
MHz
WiFi
FPGA
2 Applications
D-TVs, STBs, IP-STBs, DVD Players, DVD
Recorders, and Printers
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCE913, CDCEL913
SCAS849F – JUNE 2007 – REVISED APRIL 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
3
4
4
5
5
6
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
EEPROM Specification .............................................
Timing Requirements: CLK_IN ................................
Timing Requirements: SDA/SCL ..............................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
11
13
14
15
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application ................................................. 20
10 Power Supply Recommendations ..................... 26
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 27
12 Device and Documentation Support ................. 28
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2010) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added in Figure 9, second S to Sr ....................................................................................................................................... 14
•
Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4 ................... 23
•
Changed under Example, fifth row, N", 2 places TO N' ....................................................................................................... 23
Changes from Revision D (October 2009) to Revision E
Page
•
Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096 foot to PLL1 Configure Register Table ......................... 19
•
Added PLL settings limits: 16≤q≤63, 0≤p≤7, 0≤r≤511 to PLL Multiplier/Divider Definition Section...................................... 22
Changes from Revision C (August 2007) to Revision D
•
2
Page
Deleted sentence - A different default setting can be programmed upon customer request. Contact Texas
Instruments sales or marketing representative for more information. .................................................................................. 12
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Copyright © 2007–2015, Texas Instruments Incorporated
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SCAS849F – JUNE 2007 – REVISED APRIL 2015
5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
Xin/CLK
S0
VDD
Vctr
GND
VDDOUT
VDDOUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Xout
S1/SDA
S2/SCL
Y1
GND
Y2
Y3
Pin Functions
PIN
NAME
GND
NO.
I/O
DESCRIPTION
5, 10
Ground
Ground
SCL/S2
12
I
SDA/S1
13
I/O or I
S0
2
I
User-programmable control input S0; LVCMOS inputs; 500-kΩ internal pullup
VCtrl
4
I
VCXO control voltage (leave open or pull up when not used)
VDD
3
Power
VDDOUT
6, 7
Power
Xin/CLK
1
I
Crystal oscillator input or LVCMOS clock Input (selectable through SDA/SCL bus)
Xout
14
O
Crystal oscillator output (leave open or pull up when not used)
Y1
11
O
LVCMOS outputs
Y2
9
O
LVCMOS outputs
Y3
8
O
LVCMOS outputs
SCL: serial clock input LVCMOS (default configuration), internal pullup 500 kΩ or
S2: user-programmable control input; LVCMOS inputs; 500-kΩ internal pullup
SDA: bidirectional serial data input/output (default configuration), LVCMOS internal pullup; or
S1: user-programmable control input; LVCMOS inputs; 500-kΩ internal pullup
1.8-V power supply for the device
CDCE913: 3.3-V or 2.5-V supply for all outputs
CDCEL913: 1.8-V supply for all outputs
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
MIN
MAX
UNIT
–0.5
2.5
V
CDCEL913
–0.5
VDD
CDCE913
–0.5
3.6 + 0.5
Supply voltage
VDDOUT
Output clocks supply voltage
V
VI
Input voltage (2) (3)
–0.5
VDD + 0.5
V
VO
Output voltage (2)
–0.5
VDDOUT + 0.5
V
II
Input current (VI < 0, VI > VDD)
20
mA
IO
Continuous output current
50
mA
TJ
Maximum junction temperature
125
Tstg
Storage temperature
(1)
(2)
(3)
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table.
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: CDCE913 CDCEL913
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CDCE913, CDCEL913
SCAS849F – JUNE 2007 – REVISED APRIL 2015
www.ti.com
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VDD
VO
MIN
NOM
MAX
Device supply voltage
1.7
1.8
1.9
Output Yx supply voltage for CDCE913, VDDOUT
2.3
3.6
Output Yx supply voltage for CDCEL913, VDDOUT
1.7
1.9
VIL
Low-level input voltage, LVCMOS
VIH
High-level input voltage, LVCMOS
VI (thresh)
Input voltage threshold, LVCMOS
VI(S)
VI(CLK)
IOH /IOL
0.3 VDD
0.7 VDD
0.5 VDD
1.9
Input voltage range S1, S2, SDA, SCL; VI(thresh) = 0.5 VDD
0
3.6
Input voltage range CLK
0
1.9
Output current (VDDOUT = 3.3 V)
±12
Output current (VDDOUT = 2.5 V)
±10
Output current (VDDOUT = 1.8 V)
±8
Output load, LVCMOS
Operating free-air temperature
V
V
V
0
TA
V
V
Input voltage range, S0
CL
UNIT
–40
V
V
mA
15
pF
85
°C
32
MHz
RECOMMENDED CRYSTAL/VCXO SPECIFICATIONS (1)
fXtal
Crystal input frequency range (fundamental mode)
ESR
Effective series resistance
fPR
Pulling range (0 V ≤ VCtrl ≤ 1.8 V) (2)
8
100
±120
Frequency control voltage, VCtrl
0
C0/C1
Pullability ratio
CL
On-chip load capacitance at Xin and Xout
(1)
(2)
4
27
±150
Ω
ppm
VDD
V
220
0
20
pF
For more information about VCXO configuration, and crystal recommendation, see application report (SCAA085).
Pulling range depends on crystal type, on-chip crystal load capacitance, and PCB stray capacitance; pulling range of minimum ±120
ppm applies for crystal listed in the application report (SCAA085).
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SCAS849F – JUNE 2007 – REVISED APRIL 2015
6.4 Thermal Information (1) (2)
over operating free-air temperature range (unless otherwise noted)
CDCEx913
THERMAL METRIC
(3)
PW [TSSOP]
UNIT
14 PINS
RθJA
RθJC(to
Junction-to-ambient thermal resistance
Airflow 0 lfm
106
Airflow 150 lfm
93
Airflow 200 lfm
92
Airflow 250 lfm
90
Airflow 500 lfm
85
Junction-to-case (top) thermal resistance
°C/W
1.4
p)
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
1.35
66
ψJB
Junction-to-board characterization parameter
61.83
RθJC(b
Junction-to-case (bottom) thermal resistance
62
ot)
(1)
(2)
(3)
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-K board).
For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
OVERALL PARAMETER
Supply current (see Figure 1)
All outputs off, fCLK = 27 MHz,
fVCO = 135 MHz;
fOUT = 27 MHz
All PLLS on
IDD
IDD(OUT)
Supply current (see Figure 2 and Figure 3)
No load, all outputs on,
fOUT = 27 MHz
VDDOUT = 3.3 V
1.3
VDDOUT = 1.8 V
0.7
IDD(PD)
Power-down current. Every circuit powered
down except SDA/SCL
fIN = 0 MHz,
VDD = 1.9 V
30
V(PUC)
Supply voltage Vdd threshold for power-up
control circuit
fVCO
VCO frequency range of PLL
fOUT
LVCMOS output frequency
11
mA
9
Per PLL
mA
μA
0.85
1.45
V
80
230
MHz
VDDOUT = 3.3 V
230
VDDOUT = 1.8 V
230
–1.2
V
±5
μA
MHz
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VDD = 1.7 V; II = –18 mA
II
LVCMOS input current
VI = 0 V or VDD; VDD = 1.9 V
IIH
LVCMOS input current for S0/S1/S2
VI = VDD; VDD = 1.9 V
5
μA
IIL
LVCMOS input current for S0/S1/S2
VI = 0 V; VDD = 1.9 V
–4
μA
Input capacitance at Xin/Clk
VIClk = 0 V or VDD
6
Input capacitance at Xout
VIXout = 0 V or VDD
2
Input capacitance at S0/S1/S2
VIS = 0 V or VDD
3
CI
pF
CDCE913 - LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE
VOH
VOL
(1)
LVCMOS high-level output voltage
LVCMOS low-level output voltage
VDDOUT = 3 V, IOH = –0.1 mA
2.9
VDDOUT = 3 V, IOH = –8 mA
2.4
VDDOUT = 3 V, IOH = –12 mA
2.2
V
VDDOUT = 3 V, IOL = 0.1 mA
0.1
VDDOUT = 3 V, IOL = 8 mA
0.5
VDDOUT = 3 V, IOL = 12 mA
0.8
V
All typical values are at respective nominal VDD.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
tPLH, tPHL
Propagation delay
PLL bypass
3.2
tr/tf
Rise and fall time
VDDOUT = 3.3 V (20%–80%)
0.6
tjit(cc)
Cycle-to-cycle jitter (2) (3)
1 PLL switching, Y2-to-Y3
50
70
ps
tjit(per)
Peak-to-peak period jitter (3)
1 PLL switching, Y2-to-Y3
60
100
ps
tsk(o)
Output skew
60
ps
odc
Output duty cycle
(4)
, See Table 2
(5)
fOUT = 50 MHz; Y1-to-Y3
fVCO = 100 MHz; Pdiv = 1
45%
ns
ns
55%
CDCE913 – LVCMOS PARAMETER for VDDOUT = 2.5 V – MODE
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 2.3 V, IOH = –0.1 mA
2.2
VDDOUT = 2.3 V, IOH = –6 mA
1.7
VDDOUT = 2.3 V, IOH = –10 mA
1.6
V
VDDOUT = 2.3 V, IOL = 0.1 mA
0.1
VDDOUT = 2.3 V, IOL = 6 mA
0.5
VDDOUT = 2.3 V, IOL = 10 mA
0.7
V
tPLH, tPHL
Propagation delay
PLL bypass
3.6
tr/tf
Rise and fall time
VDDOUT = 2.5 V (20%–80%)
0.8
tjit(cc)
Cycle-to-cycle jitter (2) (3)
1 PLL switching, Y2-to-Y3
50
70
ps
tjit(per)
Peak-to-peak period jitter (3)
1 PLL switching, Y2-to-Y3
60
100
ps
tsk(o)
Output skew (4) , See Table 2
fOUT = 50 MHz; Y1-to-Y3
60
ps
odc
Output duty cycle (5)
fVCO = 100 MHz; Pdiv = 1
45%
ns
ns
55%
CDCEL913 — LVCMOS PARAMETER for VDDOUT = 1.8 V – MODE
VOH
LVCMOS high-level output voltage
VOL
LVCMOS low-level output voltage
VDDOUT = 1.7 V, IOH = –0.1 mA
1.6
VDDOUT = 1.7 V, IOH = –4 mA
1.4
VDDOUT = 1.7 V, IOH = –8 mA
1.1
V
VDDOUT = 1.7 V, IOL = 0.1 mA
0.1
VDDOUT = 1.7 V, IOL = 4 mA
0.3
VDDOUT = 1.7 V, IOL = 8 mA
0.6
V
tPLH, tPHL
Propagation delay
PLL bypass
2.6
ns
tr/tf
Rise and fall time
VDDOUT = 1.8 V (20%–80%)
0.7
ns
(2) (3)
tjit(cc)
Cycle-to-cycle jitter
1 PLL switching, Y2-to-Y3
80
110
ps
tjit(per)
Peak-to-peak period jitter (3)
1 PLL switching, Y2-to-Y3
100
130
ps
tsk(o)
Output skew (4), See Table 2
fOUT = 50 MHz; Y1-to-Y3
50
ps
odc
Output duty cycle (5)
fVCO = 100 MHz; Pdiv = 1
45%
55%
SDA/SCL PARAMETER
VIK
SCL and SDA input clamp voltage
VDD = 1.7 V; II = –18 mA
–1.2
V
IIH
SCL and SDA input current
VI = VDD; VDD = 1.9 V
±10
μA
VIH
SDA/SCL input high voltage (6)
VIL
SDA/SCL input low voltage (6)
VOL
SDA low-level output voltage
IOL = 3 mA, VDD = 1.7 V
CI
SCL/SDA input capacitance
VI = 0 V or VDD
(2)
(3)
(4)
(5)
(6)
0.7 VDD
V
0.3 VDD
3
V
0.2 VDD
V
10
pF
10,000 cycles.
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2).
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.
odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr)
SDA and SCL pins are 3.3-V tolerant.
6.6 EEPROM Specification
EEcyc
Programming cycles of EEPROM
EEret
Data retention
6
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MIN
TYP
100
1000
10
MAX
UNIT
cycles
years
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SCAS849F – JUNE 2007 – REVISED APRIL 2015
6.7 Timing Requirements: CLK_IN
over recommended ranges of supply voltage, load, and operating free-air temperature
MIN
NOM
MAX
PLL bypass mode
0
160
PLL mode
8
160
40%
60%
fCLK
LVCMOS clock input frequency
tr / tf
Rise and fall time CLK signal (20% to 80%)
UNIT
MHz
3
Duty cycle CLK at VDD/2
ns
6.8 Timing Requirements: SDA/SCL (1)
STANDARD
MODE
fSCL
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
SCL high-pulse duration
th(SDA)
SDA hold time (SDA valid after SCL low)
tsu(SDA)
SDA setup time
tr
SCL/SDA input rise time
tf
SCL/SDA input fall time
tsu(STOP)
STOP setup time
tBUS
Bus free time between a STOP and START condition
(1)
MIN
MAX
0
100
FAST MODE
UNIT
MIN
MAX
0
400
kHz
4.7
0.6
μs
4
0.6
μs
4.7
1.3
μs
4
0.6
μs
0
3.45
250
0
0.9
100
1000
ns
300
300
μs
300
ns
ns
4
0.6
μs
4.7
1.3
μs
See Figure 13
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6.9 Typical Characteristics
16
30
VDD = 1.8 V
14
3 Outputs on
12
20
IDDOUT - mA
IDD - Supply Current - mA
25
VDD = 1.8 V,
VDDOUT = 3.3 V,
no load
1 PLL on
15
10
1 Output on
8
6
10
4
all PLL off
5
2
0
10
60
110
160
fVCO - Frequency - MHz
0
10
210
Figure 1. CDCE913, CDCEL913 Supply Current vs PLL
Frequency
all Outputs off
30
50 70 90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 2. CDCE913 Output Current vs Output Frequency
4.5
4
VDD = 1.8 V,
VDDOUT = 1.8 V,
no load
3 Outputs on
IDDOUT - mA
3.5
3
2.5
2
1 Output on
1.5
1
all Outputs off
0.5
0
10 30 50
70
90 110 130 150 170 190 210 230
fOUT - Output Frequency - MHz
Figure 3. CDCEL913 Output Current vs Output Frequency
8
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7 Parameter Measurement Information
CDCE913
CDCEL913
1 kW
LVCMOS
1 kW
10 pF
Figure 4. Test Load
CDCE913
CDCEL913
LVCMOS
LVCMOS
Series
Termination
~ 18 W
Typical Driver
Impedance
~ 32 W
Line Impedance
Zo = 50 W
Figure 5. Test Load for 50-Ω Board Environment
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8 Detailed Description
8.1 Overview
The CDCE913 and CDCEL913 devices are modular PLL-based, low-cost, high-performance, programmable
clock synthesizers, multipliers, and dividers. They generate up to three output clocks from a single input
frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using the
integrated configurable PLL.
The CDCx913 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL913 and 2.5 V to 3.3 V for
CDCE913.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control
signal, that is, the PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth,
Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from, for example, a 27-MHz reference input
frequency.
The PLL supports spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking, which
is a common technique to reduce electromagnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristics.
The device supports nonvolatile EEPROM programming for easy customization of the device to the application. It
is preset to a factory default configuration (see Default Device Configuration). It can be reprogrammed to a
different application configuration before PCB assembly, or reprogrammed by in-system programming. All device
settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1, and S2, can be used to select different frequencies, change SSC
setting for lowering EMI, or control other features like outputs disable to low, outputs 3-state, power down, PLL
bypass, and so forth).
The CDCx913 operates in a 1.8-V environment. It operates in a temperature range of –40° C to 85° C.
8.2 Functional Block Diagram
VDD
VDDOUT
GND
LV
CMOS
Y1
M2
M1
Xin/CLK
LV
CMOS
Y2
M3
Input Clock
Vctr
LV
CMOS
Y3
Pdiv1
10-Bit
VCXO
XO
with SSC
Xout
EEPROM
S0
S1/SDA
S2/SCL
10
Pdiv2
7-Bit
PLL 1
MUX1
LVCMOS
Pdiv3
7-Bit
PLL Bypass
Programming
and
SDA/SCL
Register
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8.3 Feature Description
8.3.1 Control Terminal Configuration
The CDCE913/CDCEL913 has three user-definable control terminals (S0, S1, and S2), which allow external
control of device settings. They can be programmed to any of the following functions:
• Spread-spectrum clocking selection → spread type and spread amount selection
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power-down control
The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.
Table 1. Control Terminal Definition
EXTERNAL CONTROL
BITS
PLL1 SETTING
PLL frequency
selection
Control function
SSC selection
Y1 SETTING
Output Y2/Y3 selection
Output Y1 and power-down selection
Table 2. PLLx Setting (Can Be Selected for Each PLL Individually) (1)
SSCx [3 Bits]
CENTER
DOWN
SSC SELECTION (CENTER/DOWN)
(1)
0
0
0
0% (off)
0% (off)
0
0
1
±0.25%
–0.25%
0
1
0
±0.5%
–0.5%
0
1
1
±0.75%
–0.75%
1
0
0
±1.0%
–1.0%
1
0
1
±1.25%
–1.25%
1
1
0
±1.5%
–1.5%
1
1
1
±2.0%
–2.0%
Center/down-spread, Frequency0/1 and State0/1 are user-definable in PLLx configuration register.
Table 3. PLLx Setting, Frequency Selection (Can Be Selected for Each PLL
Individually) (1)
(1)
FSx
FUNCTION
0
Frequency0
1
Frequency1
Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
Table 4. PLLx Setting, Output Selection (1) (Y2 ... Y3)
(1)
YxYx
FUNCTION
0
State0
1
State1
State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down,
3-state, low ,or active.
Table 5. Y1 Setting (1)
Y1 SELECTION
(1)
Y1
FUNCTION
0
State 0
1
State 1
State0 and State1 are user definable in the generic configuration
register and can be power down, 3-state, low, or active.
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S1/SDA and S2/SCL pins of the CDCE913/CDCEL913 are dual-function pins. In the default configuration, they
are defined as SDA/SCL for the serial programming interface. They can be programmed as control pins (S1/S2)
by setting the appropriate bits in the EEPROM. Note that changes to the control register (Bit [6] of byte 02h)
have no effect until they are written into the EEPROM.
Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is
forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).
S0 is not a multi-use pin; it is a control pin only.
8.3.2 Default Device Configuration
The internal EEPROM of CDCE913/CDCEL913 is pre-configured with a factory default configuration as shown in
Figure 6 (The input frequency is passed through the output as a default).This allows the device to operate in
default mode without the extra production step of programming it. The default setting appears after power is
supplied or after power-down/up sequence until it is reprogrammed by the user to a different application
configuration. A new register setting is programmed through the serial SDA/SCL interface.
VDD
VDDOUT
GND
27 MHz
Crystal
1 = Output Enabled
0 = Output 3-State
S0
Programming Bus
SDA
SCL
EEPROM
Programming
and
SDA/SCL
Register
Pdiv2 = 1
LV
CMOS
Y2 = 27 MHz
LV
CMOS
Y3 = 27 MHz
MUX1
Xout
Y1 = 27 MHz
Pdiv1 =1
X-tal
PLL 1
power down
LV
CMOS
M2
Xin
M3
M1
Input Clock
Pdiv3 = 1
PLL Bypass
Figure 6. Default Configuration
Table 6 shows the factory default setting for the Control Terminal Register. Note that even though eight different
register settings are possible, in the default configuration, only the first two settings (0 and 1) can be selected
with S0, as S1 and S2 are configured as programming pins in default mode.
Table 6. Factory Default Setting for Control Terminal Register (1)
Y1
OUTPUT
SELECTION
EXTERNAL CONTROL PINS
PLL1 SETTINGS
FREQUENCY
SELECTION
SSC
SELECTION
OUTPUT
SELECTION
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
SCL (I2C)
SDA (I2C)
0
3-state
fVCO1_0
off
3-state
SCL (I2C)
SDA (I2C)
1
Enabled
fVCO1_0
off
Enabled
(1)
In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any
control-pin function but they are internally interpreted as if S1 = 0 and S2 = 0. S0, however, is a control pin, which in the default mode
switches all outputs ON or OFF (as previously predefined).
8.3.3 SDA/SCL Serial Interface
The CDCE913/CDCEL913 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the
popular SMBus or I2C specification. It operates in the standard-mode transfer (up to 100 kbit/s) and fast-mode
transfer (up to 400 kbit/s) and supports 7-bit addressing.
The S1/SDA and S2/SCL pins of the CDCE913/CDCEL913 are dual function pins. In the default configuration,
they are used as the SDA/SCL serial programming interface. They can be reprogrammed as general-purpose
control pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].
12
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8.3.4 Data Protocol
The device supports Byte Write and Byte Read and Block Write and Block Read operations.
For Byte Write/Read operations, the system controller can individually access addressed bytes.
For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of
bytes read out are defined by Byte Count in the generic configuration register. At the Block Read instruction, all
bytes defined in Byte Count must be read out to finish the read cycle correctly.
Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to
each transferred byte, regardless of whether this is a Byte Write or a Block Write sequence.
If the EEPROM write cycle is initiated, the internal SDA registers are written into the EEPROM. During this write
cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read out
during the programming sequence (Byte Read or Block Read). The programming status can be monitored by
EEPIP, byte 01h–bit 6.
The offset of the indexed byte is encoded in the command code, as described in Table 7.
Table 7. Slave Receiver Address (7 Bits)
A6
A5
A4
A3
A2
A1 (1)
A0 (1)
R/W
CDCE913/CDCEL913
1
1
0
0
1
0
1
1/0
CDCE925/CDCEL925
1
1
0
0
1
0
0
1/0
CDCE937/CDCEL937
1
1
0
1
1
0
1
1/0
CDCE949/CDCEL949
1
1
0
1
1
0
0
1/0
DEVICE
(1)
Address bits A0 and A1 are programmable through the SDA/SCL bus (byte 01, bits [1:0]. This allows addressing up to 4 devices
connected to the same SDA/SCL bus. The least-significant bit of the address byte designates a write or read operation.
8.4 Device Functional Modes
8.4.1 SDA/SCL Hardware Interface
Figure 7 shows how the CDCE913/CDCEL913 clock synthesizer is connected to the SDA/SCL serial interface
bus. Multiple devices can be connected to the bus, but it may be necessary to reduce the speed (400 kHz is the
maximum) if many devices are connected.
Note that the pullup resistors (RP) depend on the supply voltage, bus capacitance, and number of connected
devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at
VOLmax = 0.4 V for the output stages (for more details see the SMBus or I2C Bus specification).
CDCE913
CDCEL913
RP
RP
Master
Slave
SDA
SCL
CBUS
CBUS
Figure 7. SDA / SCL Hardware Interface
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8.5 Programming
Table 8. Command Code Definition
BIT
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
7
(6:0)
Byte offset for Byte Read, Block Read, Byte Write, and Block Write operations
1
S
7
Slave Address
1
R/W
MSB
LSB
S
Start Condition
Sr
Repeated Start Condition
1
A
8
Data Byte
1
A
MSB
1
P
LSB
1 = Read (Rd) From CDCE9xx Device; 0 = Write (Wr) to CDCE9xxx
R/W
A
Acknowledge (ACK = 0 and NACK =1)
P
Stop Condition
Master-to-Slave Transmission
Slave-to-Master Transmission
Figure 8. Generic Programming Sequence
1
S
7
Slave Address
1
Wr
1
A
8
CommandCode
1
A
8
Data Byte
1
A
1
P
7
Slave Address
1
Rd
1
A
1
A
1
P
Figure 9. Byte Write Protocol
1
S
7
Slave Address
1
Wr
1
A
8
Data Byte
1
A
1
P
8
CommandCode
1
A
1
Sr
Figure 10. Byte Read Protocol
1
S
(1)
7
Slave Address
1
Wr
8
Data Byte 0
1
A
1
A
8
CommandCode
8
Data Byte 1
1
A
1
A
8
Byte Count = N
8
Data Byte N-1
…
1
A
Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose
and should not be overwritten.
Figure 11. Block Write Protocol
1
S
7
Slave Address
1
Wr
8
Byte Count N
1
A
1
A
8
CommandCode
8
Data Byte 0
1
A
1
A
1
Sr
…
7
Slave Address
1
Rd
1
A
8
Data Byte N-1
1
A
1
P
Figure 12. Block Read Protocol
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P
S
tw(SCLL)
Bit 7 (MSB)
tw(SCLH)
Bit 6
tr
Bit 0 (LSB)
A
P
tf
VIH
SCL
VIL
tsu(START)
th(START)
tsu(SDA)
th(SDA)
t(BUS)
tsu(STOP)
tf
tr
VIH
SDA
VIL
Figure 13. Timing Diagram for SDA/SCL Serial Control Interface
8.6 Register Maps
8.6.1 SDA/SCL Configuration Registers
The clock input, control pins, PLLs, and output stages are user configurable. The following tables and
explanations describe the programmable functions of the CDCE913/CDCEL913. All settings can be manually
written into the device through the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI
Pro-Clock™ software allows the user to quickly make all settings and automatically calculates the values for
optimized performance at lowest jitter.
Table 9. SDA/SCL Registers
ADDRESS OFFSET
REGISTER DESCRIPTION
TABLE
00h
Generic configuration register
Table 11
10h
PLL1 configuration register
Table 12
The grey-highlighted bits, described in the configuration register tables in the following pages, belong to the
control terminal register. The user can predefine up to eight different control settings. These settings then can be
selected by the external control pins, S0, S1, and S2. See Control Terminal Configuration.
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Table 10. Configuration Register, External Control Terminals
Y1
EXTERNAL
CONTROL PINS
OUTPUT SELECTION
16
FREQUENCY SELECTION
SSC SELECTION
OUTPUT
SELECTION
S2
S1
S0
Y1
FS1
SSC1
Y2Y3
0
0
0
0
Y1_0
FS1_0
SSC1_0
Y2Y3_0
1
0
0
1
Y1_1
FS1_1
SSC1_1
Y2Y3_1
2
0
1
0
Y1_2
FS1_2
SSC1_2
Y2Y3_2
3
0
1
1
Y1_3
FS1_3
SSC1_3
Y2Y3_3
4
1
0
0
Y1_4
FS1_4
SSC1_4
Y2Y3_4
5
1
0
1
Y1_5
FS1_5
SSC1_5
Y2Y3_5
6
1
1
0
Y1_6
FS1_6
SSC1_6
Y2Y3_6
7
1
1
1
Y1_7
FS1_7
SSC1_7
Y2Y3_7
04h
13h
10h–12h
15h
Address offset (1)
(1)
PLL1 Settings
Address offset refers to the byte address in the configuration register in Table 11 and Table 12.
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Table 11. Generic Configuration Register
OFFSET
(1)
00h
BIT
(2)
ACRONYM
DEFAULT
(3)
DESCRIPTION
7
E_EL
Xb
Device identification (read-only): 1 is CDCE913 (3.3 V out), 0 is CDCEL913 (1.8 V out)
6:4
RID
Xb
Revision identification number (read-only)
3:0
VID
1h
Vendor identification number (read-only)
7
–
0b
Reserved – always write 0
6
EEPIP
0b
EEPROM programming Status4: (4) (read-only)
0 – EEPROM programming is completed.
1 – EEPROM is in programming mode.
5
EELOCK
0b
Permanently lock EEPROM data (5)
0 – EEPROM is not locked.
1 – EEPROM is permanently locked.
4
PWDN
0b
Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged)
Note: PWDN cannot be set to 1 in the EEPROM.
01h
0 – Device active (PLL1 and all outputs are enabled)
1 – Device power down (PLL1 in power down and all outputs in 3-state)
3:2
INCLK
00b
00 – Xtal
10 – LVCMOS
01 – VCXO
11 – Reserved
Input clock selection:
1:0
SLAVE_ADR
01b
Address bits A0 and A1 of the slave receiver address
7
M1
1b
Clock source selection for output Y1:
0 – Input clock
1 – PLL1 clock
Operation mode selection for pin 12/13 (6)
02h
6
SPICON
0b
5:4
Y1_ST1
11b
3:2
Y1_ST0
01b
1:0
Pdiv1 [9:8]
7:0
Pdiv1 [7:0]
7
Y1_7
0b
6
Y1_6
0b
5
Y1_5
0b
4
Y1_4
0b
3
Y1_3
0b
2
Y1_2
0b
1
Y1_1
1b
0
Y1_0
0b
7:3
XCSEL
0Ah
0b
Reserved – do not write other than 0
7:1
BCOUNT
20h
7-bit byte count (defines the number of bytes which will be sent from this device at the next Block Read transfer); all bytes
must be read out to finish the read cycle correctly.
0
EEWRITE
0b
Initiate EEPROM write cycle
—
0h
Unused address range
001h
03h
04h
0 – Serial programming interface SDA (pin 13) and SCL (pin 12)
1 – Control pins S1 (pin 13) and S2 (pin 12)
Y1-State0/1 definition
00 – Device power down (all PLLs in power down and all
outputs in 3-State)
01 – Y1 disabled to 3-state
10-bit Y1-output-divider Pdiv1:
0 – Divider reset and stand-by
1 to 1023 – Divider value
Y1_x State Selection (7)
0 – State0 (predefined by Y1_ST0)
1 – State1 (predefined by Y1_ST1)
Crystal load capacitor selection (8)
05h
2:0
10 – Y1 disabled to low
11 – Y1 enabled
00h – 0 pF
01h – 1 pF
02h – 2 pF
:14h to 1Fh – 20 pF
06h
07h-0Fh
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(4) (9)
0– No EEPROM write cycle
1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)
Writing data beyond ‘20h may affect device function.
All data transferred with the MSB first
Unless customer-specific setting
During EEPROM programming, no data is allowed to be sent to the device through the SDA/SCL bus until the programming sequence is
completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).
If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible.
Data, however can still be written through the SDA/SCL bus to the internal register to change device function on the fly, but new data
can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.
Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no
longer available. However, if VDDOUT is forced to GND, the two control pins, S1 and S2, temporarily act as serial programming pins
(SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.
These are the bits of the control terminal register (see Table 10 ). The user can predefine up to eight different control settings. These
settings then can be selected by the external control pins, S0, S1, and S2.
The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors should be used only to
finely adjust CL by a few picofarads. The value of CL can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20
pF. For CL > 20 pF, use additional external capacitors. The device input capacitance value must be considered, which always adds 1.5
pF (6 pF//2 pF) to the selected CL. For more about VCXO config. and crystal recommendation, see application report SCAA085.
The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The
EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The
EEWRITE bit must be reset to low after the programming is completed. The programming status can be monitored by reading out
EEPIP. If EELOCK is set to high, no EEPROM programming is possible.
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Table 12. PLL1 Configuration Register
OFFSET
10h
11h
12h
13h
14h
15h
(1)
(2)
(3)
(4)
18
(1)
ACRONYM
DEFAULT (3)
7:5
SSC1_7 [2:0]
000b
4:2
SSC1_6 [2:0]
000b
1:0
SSC1_5 [2:1]
7
SSC1_5 [0]
6:4
SSC1_4 [2:0]
000b
3:1
SSC1_3 [2:0]
000b
0
SSC1_2 [2]
7:6
SSC1_2 [1:0]
5:3
SSC1_1 [2:0]
000b
2:0
SSC1_0 [2:0]
000b
7
FS1_7
0b
6
FS1_6
0b
5
FS1_5
0b
4
FS1_4
0b
3
FS1_3
0b
2
FS1_2
0b
1
FS1_1
0b
0
FS1_0
0b
7
MUX1
1b
PLL1 multiplexer:
0 – PLL1
1 – PLL1 bypass (PLL1 is in power down)
6
M2
1b
Output Y2 multiplexer:
0 – Pdiv1
1 – Pdiv2
5:4
M3
10b
Output Y3 Multiplexer:
00 –
01 –
10 –
11 –
3:2
Y2Y3_ST1
11b
00 – Y2/Y3 disabled to 3-state (PLL1 is in power down)
01 – Y2/Y3 disabled to 3-State
10–Y2/Y3 disabled to low
11 – Y2/Y3 enabled
BIT
(2)
000b
000b
DESCRIPTION
SSC1: PLL1 SSC selection (modulation amount).
Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%
(4)
Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
FS1_x: PLL1 frequency selection (4)
0 – fVCO1_0 (predefined by PLL1_0 – multiplier/divider value)
1 – fVCO1_1 (predefined by PLL1_1 – multiplier/divider value)
1:0
Y2Y3_ST0
01b
Y2, Y3State0/1definition:
7
Y2Y3_7
0b
Y2Y3_x output state selection.
6
Y2Y3_6
0b
5
Y2Y3_5
0b
4
Y2Y3_4
0b
3
Y2Y3_3
0b
2
Y2Y3_2
0b
1
Y2Y3_1
1b
0
Y2Y3_0
0b
Pdiv1-divider
Pdiv2-divider
Pdiv3-divider
Reserved
(4)
0 – State0 (predefined by Y2Y3_ST0)
1 – State1 (predefined by Y2Y3_ST1)
Writing data beyond 20h may adversely affect device function.
All data is transferred MSB-first.
Unless a custom setting is used
The user can predefine up to eight different control settings. In normal device operation, these settings can be selected by the external
control pins, S0, S1, and S2.
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Table 12. PLL1 Configuration Register (continued)
OFFSET
(1)
BIT
(2)
ACRONYM
DEFAULT (3)
DESCRIPTION
7
SSC1DC
0b
PLL1 SSC down/center selection:
0 – Down
1 – Center
6:0
Pdiv2
01h
7-bit Y2-output-divider Pdiv2:
0 – Reset and stand-by
1 to 127 – Divider value
7
—
0b
Reserved – do not write others than 0
6:0
Pdiv3
01h
7-bit Y3-output-divider Pdiv3:
7:0
PLL1_0N [11:4]
7:4
PLL1_0N [3:0]
3:0
PLL1_0R [8:5]
7:3
PLL1_0R[4:0]
2:0
PLL1_0Q [5:3]
7:5
PLL1_0Q [2:0]
4:2
PLL1_0P [2:0]
010b
1:0
VCO1_0_RANGE
00b
7:0
PLL1_1N [11:4]
7:4
PLL1_1N [3:0]
3:0
PLL1_1R [8:5]
7:3
PLL1_1R[4:0]
2:0
PLL1_1Q [5:3]
7:5
PLL1_1Q [2:0]
4:2
PLL1_1P [2:0]
010b
1:0
VCO1_1_RANGE
00b
16h
17h
18h
19h
1Ah
004h
000h
PLL1_0 (5): 30-bit multiplier/divider value for frequency fVCO1_0
(for more information, see the PLL Multiplier/Divider Definition paragraph).
10h
1Bh
1Ch
1Dh
1Eh
1Fh
(5)
0 – Reset and stand-by
1 to 127 – Divider value
fVCO1_0 range selection:
00 –
01 –
10 –
11 –
fVCO1_0 < 125 MHz
125 MHz ≤ fVCO1_0 < 150 MHz
150 MHz ≤ fVCO1_0 < 175 MHz
fVCO1_0 ≥ 175 MHz
004h
000h
PLL1_1 (5): 30-bit multiplier/divider value for frequency fVCO1_1
(for more information see the PLL Multiplier/Divider Definition).
10h
fVCO1_1 range selection:
00 –
01 –
10 –
11 –
fVCO1_1 < 125 MHz
125 MHz ≤ fVCO1_1 < 150 MHz
150 MHz ≤ fVCO1_1 < 175 MHz
fVCO1_1 ≥ 175 MHz
PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCE913 device is an easy-to-use high-performance, programmable CMOS clock synthesizer. it can be
used as a crystal buffer, clock synthesizer with separate output supply pin. The CDCE913 features an on-chip
loop filter and Spread-spectrum modulation. Programming can be done through SPI, pin-mode, or using on-chip
EEPROM. This section shows some examples of using CDCE913 in various applications.
9.2 Typical Application
Figure 14 shows the use of the CDCEL913 in an audio/video application using a 1.8-V single supply.
Figure 14. Single-Chip Solution Using CDCE913 for Generating Audio/Video Frequencies
9.2.1 Design Requirements
CDCE913 supports spread spectrum clocking (SSC) with multiple control parameters:
• Modulation amount (%)
• Modulation frequency (>20 kHz)
• Modulation shape (triangular, hershey, and others)
• Center spread / down spread (± or –)
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Typical Application (continued)
Figure 15. Modulation Frequency (fm) and Modulation Amount
Figure 16. Spread Spectrum Modulation Shapes
9.2.2 Detailed Design Procedure
9.2.2.1 Spread Spectrum Clock (SSC)
Spread Spectrum modulation is a method to spread emitted energy over a larger bandwidth. In clocking, spread
spectrum can reduce Electromagnetic Interference (EMI) by reducing the level of emission from clock distribution
network.
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Typical Application (continued)
CDCS502 with a 25-MHz Crystal, FS = 1, Fout = 100 MHz, and 0%, ±0.5, ±1%, and ±2% SSC
Figure 17. Comparison Between Typical Clock Power Spectrum and Spread-Spectrum Clock
9.2.2.2 PLL Frequency Planning
At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCE913/CDCEL913 can be calculated:
ƒ
N
ƒOUT = IN ´
Pdiv M
where
•
M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output divider.
(1)
The target VCO frequency (ƒVCO) of each PLL can be calculated:
N
ƒ VCO = ƒIN ´
M
(2)
The PLL internally operates as fractional divider and needs the following multiplier/divider settings:
• N
• P = 4 – int(log2N/M; if P < 0 then P = 0
• Q = int(N'/M)
• R = N′ – M × Q
where
N′ = N × 2P
N ≥ M;
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Typical Application (continued)
80 MHz ≤ ƒVCO ≤ 230 MHz
16 ≤ Q ≤ 63 µs
0 ≤ P ≤ 4 µs
0 ≤ R ≤ 51 µs
Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2
for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2
→ fOUT = 54 MHz
→ fOUT = 74.25 MHz
→ fVCO = 108 MHz
→ fVCO = 148.50 MHz
→ P = 4 – int(log24) = 4 – 2 = 2
→ P = 4 – int(log25.5) = 4 – 2 = 2
2
→ N' = 4 × 2 = 16
→ N' = 11 × 22 = 44
→ Q = int(16) = 16
→ Q = int(22) = 22
→ R = 16 – 16 = 0
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.
9.2.2.3 Crystal Oscillator Start-up
When the CDCE913/CDCEL913 is used as a crystal buffer, crystal oscillator start-up dominates the start-up time
compared to the internal PLL lock time. The following diagram shows the oscillator start-up sequence for a 27MHz crystal input with an 8-pF load. The start-up time for the crystal is in the order of approximately 250 µs
compared to approximately 10 µs of lock time. In general, lock time will be an order of magnitude less compared
to the crystal start-up time.
Figure 18. Crystal Oscillator Start-up vs PLL Lock Time
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Typical Application (continued)
9.2.2.4 Frequency Adjustment with Crystal Oscillator Pulling
The frequency for the CDCE913/CDCEL913 is adjusted for media and other applications with the VCXO control
input Vctrl. If a PWM modulated signal is used as a control signal for the VCXO, an external filter is needed.
LP
PWM
control
signal
Vctrl
CDCE(L)913
Xin/CLK
Xout
Figure 19. Frequency Adjustment using PWM Input to the VCXO Control
9.2.2.5 Unused Inputs/Outputs
If VCXO pulling functionality is not required, Vctrl should be left floating. All other unused inputs should be set to
GND. Unused outputs should be left floating.
If one output block is not used, it is recommended to disable it. However, it is always recommended to provide
the supply for the second output block even if it is disabled.
9.2.2.6 Switching Between XO and VCXO Mode
When the CDCE(L)913 is in crystal oscillator or in VCXO configuration, the internal capacitors require different
internal capacitance. The following steps are recommended to switch to VCXO mode when the configuration for
the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:
1. While in XO mode, put Vctrl = Vdd/2
2. Switch from X0 mode to VCXO mode
3. Program the internal capacitors in order to obtain 0ppm at the output.
9.2.3 Application Curves
Figure 20, Figure 21, Figure 22, and Figure 23 show CDCE913 measurements with the SSC feature enabled.
Device Configuration: 27-MHz input, 27-MHz output.
Figure 20. fout = 27 MHz, VCO frequency < 125 MHz, SSC
(2% center)
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Figure 21. fout = 27 MHz, VCO frequency > 175 MHz, SSC
(1%, center)
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Typical Application (continued)
Figure 22. Output Spectrum With SSC Off
Figure 23. Output Spectrum With SSC On, 2% Center
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10 Power Supply Recommendations
There is no restriction on the power-up sequence. In case VDDOUT is applied first, it is recommended to ground
VDD. In case VDDOUT is powered while VDD is floating, there is a risk of high current flowing on the VDDOUT.
The device has a power-up control that is connected to the 1.8-V supply. This will keep the whole device
disabled until the 1.8-V supply reaches a sufficient voltage level. Then the device switches on all internal
components, including the outputs. If there is a 3.3-V Vddout available before the 1.8-V, the outputs will stay
disabled until the 1.8-V supply has reached a certain level.
11 Layout
11.1 Layout Guidelines
When the CDCE913 is used as a crystal buffer, any parasitics across the crystal affects the pulling range of the
VCXO. Therefore, care must be taken in placing the crystal units on the board. Crystals should be placed as
close to the device as possible, ensuring that the routing lines from the crystal terminals to XIN and XOUT have
the same length.
If possible, cut out both ground plane and power plane under the area where the crystal and the routing to the
device are placed. In this area, always avoid routing any other signal line, as it could be a source of noise
coupling.
Additional discrete capacitors can be required to meet the load capacitance specification of certain crystal. For
example, a 10.7-pF load capacitor is not fully programmable on the chip, because the internal capacitor can
range from 0 pF to 20 pF with steps of 1 pF. The 0.7-pF capacitor therefore can be discretely added on top of an
internal 10 pF.
To minimize the inductive influence of the trace, it is recommended to place this small capacitor as close to the
device as possible and symmetrically with respect to XIN and XOUT.
Figure 24 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For
component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
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11.2 Layout Example
1
4
3
2
1
3
Place crystal with associated load
caps as close to the chip
Place bypass caps close to the device
pins, ensure wide freq. range
2
Place series termination resistors at
Clock outputs to improve signal integrity
4
Use ferrite beads to isolate the device
supply pins from board noise sources
Figure 24. Annotated Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
VCXO Application Guideline for CDCE(L)9xx Family, (SCAA085)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 13. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
CDCE913
Click here
Click here
Click here
Click here
Click here
CDCEL913
Click here
Click here
Click here
Click here
Click here
12.3 Trademarks
DaVinci, OMAP, Pro-Clock are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
CDCE913PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE913
CDCE913PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE913
CDCE913PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE913
CDCE913PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDCE913
CDCEL913PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKEL913
CDCEL913PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKEL913
CDCEL913PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKEL913
CDCEL913PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKEL913
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CDCEL913 :
• Automotive: CDCEL913-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCE913PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CDCEL913PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCE913PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
CDCEL913PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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