LINER LTC2865 20mbps rs485 transceiver Datasheet

LTC2859/LTC2861
20Mbps RS485 Transceivers
with Integrated Switchable
Termination
Description
Features
n
n
n
n
n
n
n
n
n
n
n
n
n
Integrated, Logic-Selectable 120Ω Termination
Resistor
20Mbps Max Data Rate
No Damage or Latchup to ESD: ±15kV HBM
High Input Impedance Supports 256 Nodes
(C-, I-Grades)
Operation Up to 105°C (LTC2859H)
250kbps Low-EMI Mode
Guaranteed Failsafe Receiver Operation Over the
Entire Common Mode Range
Current Limited Drivers and Thermal Shutdown
Delayed Micropower Shutdown (5µA Max)
Power Up/Down Glitch-Free Driver Outputs
Low Operating Current (900µA Max in Receive Mode)
Meets All TIA/EIA-485-A Specifications
Available in 10-Pin 3mm × 3mm DFN, 12-Pin
4mm × 3mm DFN and 16-Pin SSOP Packages
Applications
n
n
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Low Power RS485/RS422 Transceiver
Level Translator
Backplane Transceiver
The LTC®2859 and LTC2861 are low power, 20Mbps
RS485/422 transceivers operating on 5V supplies. The
receiver includes a logic-selectable 120Ω termination,
one-eighth unit load supporting up to 256 nodes per bus
(C-, I-grades), and a failsafe feature that guarantees a high
output state under conditions of floating or shorted inputs.
The driver features a logic-selectable low-EMI 250kbps
operating mode, and maintains a high output impedance
over the entire common mode range when disabled or
when the supply is removed. Excessive power dissipation
caused by bus contention or a fault is prevented by current
limiting all outputs and by a thermal shutdown.
Enhanced ESD protection allows the LTC2859 and LTC2861
to withstand ±15kV (human body model) on the transceiver
interface pins without latchup or damage.
Product Selection Guide
PART NUMBER
DUPLEX
PACKAGE
LTC2859
Half
DFN-10
LTC2861
Full
SSOP-16, DFN-12
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
LTC2859
LTC2859
DE
DI
R
R
RO
RE
TE
120Ω
120Ω
SLO
DI
DE
D
D
LTC2859 at 20Mbps
RO
RE
TE
Y
DI
Z
SLO
LTC2859
Y–Z
2859/61 TA01
120Ω
2V/DIV
20ns/DIV
285961 TA02
R
D
RO RE TE DE
DI
SLO
285961fc
1
LTC2859/LTC2861
Absolute Maximum Ratings
(Note 1)
Supply Voltage (VCC).................................... –0.3V to 7V
Logic Input Voltages (RE, DE, DI, TE, SLO)..... –0.3V to 7V
Interface I/O:
A, B, Y, Z........................................(VCC –15V) to +15V
(A-B) or (B-A) with Terminator Enabled...................6V
Receiver Output Voltage (RO).........–0.3V to (VCC +0.3V)
Operating Temperature (Note 4)
LTC2859C, LTC2861C............................... 0°C to 70°C
LTC2859I, LTC2861I.............................–40°C to 85°C
LTC2859H........................................... –40°C to 105°C
Storage Temperature Range................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
GN Package....................................................... 300°C
Pin Configuration
TOP VIEW
TOP VIEW
TOP VIEW
RO
1
12 VCC
10 VCC
RE
2
11 A
9 B
DE
3
DI
4
9
Z
TE
5
8
Y
GND
6
7
SLO
RO
1
RE
2
DE
3
8 A
DI
4
7 SLO
TE
5
6 GND
11
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 11) PCB GND CONNECTION
TJMAX = 125°C, θJA = 43°C/W
θJC = 3°C/W
13
10 B
DE PACKAGE
12-LEAD (4mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 13) PCB GND CONNECTION
TJMAX = 125°C, θJA = 43°C/W
θJC = 4.3°C/W
RO
1
16 VCC
RE
2
15 A
DE
3
14 B
DI
4
13 Z
TE
5
12 Y
GND
6
11 SLO
NC
7
10 NC
NC
8
9
NC
GN PACKAGE
16-LEAD (NARROW 0.150) PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
θJC = 40°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2861CDE#PBF
LTC2861CDE#TRPBF
2861
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2861IDE#PBF
LTC2861IDE#TRPBF
2861
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC2861CGN#PBF
LTC2861CGN#TRPBF
2861
16-Lead Plastic SSOP
0°C to 70°C
LTC2861IGN#PBF
LTC2861IGN#TRPBF
2861I
16-Lead Plastic SSOP
–40°C to 85°C
LTC2859CDD#PBF
LTC2859CDD#TRPBF
LBNX
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 105°C
LTC2859IDD#PBF
LTC2859IDD#TRPBF
LBNX
LTC2859HDD#PBF
LTC2859HDD#TRPBF
LBNX
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
285961fc
2
LTC2859/LTC2861
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VCC = 5V unless otherwise noted (Note 2).
SYMBOL
PARAMETER
CONDITIONS
MIN
|VOD|
Differential Driver Output Voltage
R = ∞, IO = 0mA, VCC = 4.5V (Figure 1)
R = 27Ω (RS485), VCC = 4.5V (Figure 1)
R = 50Ω (RS422), VCC = 4.5V (Figure 1)
l
l
l
D|VOD|
Change in Magnitude of Driver
Differential Output Voltage for
Complementary Output States
R = 27Ω or R = 50Ω (Figure 1)
VOC
Driver Common Mode Output Voltage
D|VOC|
TYP
MAX
UNITS
VCC
VCC
VCC
V
V
V
l
0.2
V
R = 27Ω or R = 50Ω (Figure 1)
l
3.0
V
Change in Magnitude of Driver
Common Mode Output Voltage for
Complementary Output States
R = 27Ω or R = 50Ω (Figure 1)
l
0.2
V
IOZD
Driver Three-State (High Impedance)
Output Current on Y and Z
DE = OV, VO = –7V, +12V
(LTC2861 Only)
l
±10
µA
IOSD
Maximum Driver Short-Circuit Current –7V ≤ (Y or Z) ≤ 12 (Figure 2)
l
±250
mA
Receiver Input Current (A, B)
DE = TE = 0V, VCC = 0V or 5V, VA or VB = 12V,
Other at 0V
(H-Grade)
l
125
µA
DE = TE = 0V, VCC = 0V or 5V, VA or VB = –7V,
Other at 0V
(H-Grade)
l
–100
µA
l
–145
µA
l
Driver
1.5
2.0
±120
Receiver
IIN2
VTH
Receiver Differential Input Threshold
Voltage
–7V ≤ VCM ≤ 12
DVTH
Receiver Input Hysteresis
VCM = 0V
250
l
±0.2
25
µA
V
mV
VOH
Receiver Output HIGH Voltage
I0 = –4mA, VID = 200mV, VCC = 4.5V
l
VOL
Receiver Output LOW Voltage
I0 = 4mA, VID = –200mV, VCC = 4.5V
l
0.4
V
IOZR
Receiver Three-State (High
Impedance) Output Current on RO
RE = 5V, 0V ≤ VO ≤ VCC
l
±1
µA
RIN
Receiver Input Resistance
RE = 5V or 0V, DE = TE = 0V
l
96
125
kΩ
–7V ≤ VA = VB ≤ 12V
(H-Grade)
l
48
125
kΩ
120
RTERM
2.4
Receiver Input Terminating Resistor
TE = 5V, VAB = 2V, VB = –7, 0, 10V
(Figure 7)
l
108
Logic Input High Voltage
DE, DI, RE, TE, SLO, VCC = 4.5V
l
2
V
156
Ω
Logic
VIH
V
VIL
Logic Input Low Voltage
DE, DI, RE, TE, SLO, VCC = 4.5V
l
0.8
V
IIN1
Logic Input Current
DE, DI, RE, TE, SLO
l
0
±10
µA
ISHDN
Supply Current in Shutdown Mode
DE = 0V, RE = VCC, TE = 0V
l
0
5
µA
ICCR
Supply Current in Receive Mode
No Load, DE = 0V, RE = 0V, TE = 0V
l
540
900
µA
Supplies
ICCT
Supply Current in Transmit Mode
No Load, DE = VCC, RE = VCC, SLO = VCC, TE = 0V
l
630
1000
µA
ICCTS
Supply Current in Transmit SLO Mode
No Load, DE = VCC, RE = VCC, SLO = 0V, TE = 0V
l
670
1100
µA
ICCL
Supply Current in Loopback Mode
(Both Driver and Receiver Enabled)
No Load, DE = VCC, RE= 0V, SLO = VCC, TE = 0V
l
660
1100
µA
ICCRT
Supply Current in Termination Mode
DE = 0V, RE = VCC, TE = VCC, SLO = VCC
l
640
1180
µA
285961fc
3
LTC2859/LTC2861
Switching Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VCC = 5V, TE = 0 unless otherwise noted (Note 2).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Driver in Normal Mode (SLO HIGH)
fMAX
Maximum Data Rate
Note 3
l
tPLHD, tPHLD
Driver Input to Output
RDIFF = 54Ω, CL = 100pF (Figure 3)
l
20
10
50
Mbps
ns
DtPD
Driver Input to Output Difference
|tPLHD-tPHLD|
RDIFF = 54Ω, CL = 100pF (Figure 3)
l
1
6
ns
tSKEWD
Driver Output Y to Output Z
RDIFF = 54Ω, CL = 100pF (Figure 3)
l
1
±6
ns
tRD, tFD
Driver Rise or Fall Time
RDIFF = 54Ω, CL = 100pF (Figure 3)
l
4
12.5
ns
tZLD, tZHD, tLZD, Driver Enable or Disable Time
tHZD
RL = 500Ω, CL = 50pF, RE = 0 (Figure 4)
l
70
ns
tZHSD, tZLSD
Driver Enable from Shutdown
RL = 500Ω, CL = 50pF, RE = VCC (Figure 4)
l
8
µs
tSHDN
Time to Shutdown
(DE = ↓, RE = VCC) or (DE = 0, RE ↑)
(Figure 4)
l
100
ns
Driver in SLO Mode (SLO LOW)
fMAXS
Maximum Data Rate
Note 3
l
tPLHDS, tPHLDS
Driver Input to Output
RDIFF = 54Ω, CL = 100pF (Figure 3)
l
250
kbps
0.95
1.5
µs
DtPDS
Driver Input to Output Difference
|tPLHR-tPHLR|
RDIFF = 54Ω, CL = 100pF (Figure 3)
l
50
500
ns
tSKEWDS
Driver Output A to Output B
RDIFF = 54Ω, CL = 100pF (Figure 3)
(H-Grade)
l
l
200
200
±500
±750
ns
ns
tRDS, tFDS
Driver Rise or Fall Time
RDIFF = 54Ω, CL = 100pF (Figure 3)
l
0.9
1.5
µs
tZHDS, tZLDS
Driver Enable Time
RL = 500Ω, CL = 50pF, RE = 0 (Figure 4)
l
300
ns
tLZDS, tHZDS
Driver Disable Time
RL = 500Ω, CL = 50pF, RE = 0 (Figure 4)
l
70
ns
tZHSDS, tZLSDS
Driver Enable from Shutdown
RL = 500Ω, CL = 50pF, RE = VCC (Figure 4)
l
8
µs
tSHDNS
Time to Shutdown
(DE = 0, RE = ↑) or (DE = ↓, RE = VCC) (Figure 4)
l
500
ns
tPLHR, tPHLR
Receiver Input to Output
CL = 15pF, VCM = 1.5V, |VAB| = 1.5V, tR and tF <
4ns (Figure 5)
l
50
70
ns
tSKEWR
Differential Receiver Skew
|tPLHR-tPHLR|
CL = 15pF (Figure 5)
l
1
6
ns
tRR, tFR
Receiver Output Rise or Fall Time
CL = 15pF (Figure 5)
l
3
12.5
ns
tZLR, tZHR, tLZR, Receiver Enable/Disable
tHZR
RL = 1kΩ, CL =15pF, DE = VCC (Figure 6)
DI = 0 or VCC
l
50
ns
tZHSR, tZLSR
Receiver Enable from Shutdown
RL = 1kΩ, CL = 15pF, DE = 0V (Figure 6)
DI = 0 or VCC
l
8
µs
tRTEN, tRTZ
Termination Enable or Disable Time
VB = 0V, VAB = 2V, RE = VCC, DE = 0V (Figure 7)
l
100
µs
Receiver
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime..
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to device ground unless
otherwise specified.
Note 3: Maximum data rate is guaranteed by other measured parameters
and is not tested directly.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may result in device degradation or failure.
285961fc
4
LTC2859/LTC2861
Test Circuits
Y
GND
DI
OR
VCC
DRIVER
Z
Y
R
+
VOD
–
R
GND
OR
DI
VCC
+
VOC
–
IOSD
DRIVER
Z
+
–
–7V to +12V
2859/61 F01-2
Figure 1. Driver DC Characteristics
Figure 2. Driver Output Short-Circuit Current
DI
Y
DI
DRIVER
RDIFF
tPLHD,
tPLHDS
OV
CL
CL
VCC
VO
Y, Z
tSKEWD, tSKEWDS
tPHLD,
tPHLDS
1/2 VO
Z
90%
10%
(Y-Z)
0
0
tRD,
tRDS
90%
10%
tFD,
tFDS
2859/61 F03
Figure 3. Driver Timing Measurement
RL
Y
VCC
OR DI
GND
CL
GND
OR
VCC
DRIVER
VCC
DE
Y or Z
Z
RL
DE
CL
VCC
OR
GND
Z or Y
1/2 VCC
OV
VCC
VOL
VOH
OV
tZLD,
tZLDS,
tZLSD,
tZLSDS
1/2 VCC
VO
1/2 VCC
tZHD,
tZHDS,
tZHSD,
tZHSDS
tLZD,
tLZDS
0.5V
tHZD,
tHZDS,
tSHDN,
tSHDNS
0.5V
2859/61 F04
Figure 4. Driver Enable and Disable Timing Measurement
285961fc
5
LTC2859/LTC2861
test circuits
±VAB/2
A-B
A
VCM
0V
–VAB
RO
RECEIVER
B
VAB
VCC
RO
CL
±VAB/2
0V
tPLHR
VO
90%
10%
1/2 VCC
1/2 VCC
tRR
tPHLR
90%
10%
tFR
tSKEWR = tPLHR – tPHLR
2859/61 F05
Figure 5. Receiver Propagation Delay Measurements
0V OR VCC
RE
A
RECEIVER
VCC OR 0V
RL
RO
CL
B
VCC
OR
GND
RO
RE
RO
DI = 0V OR VCC
VCC
0V
VCC
VOL
VOH
tZLR,
tZLSR
1/2 VCC
tLZR
VO
1/2 VCC
0.5V
0.5V
1/2 VCC
0V
tZHR,
tZHSR
tHZR
2859/61 F06
Figure 6. Receiver Enable/Disable Time Measurements
A
RO
RECEIVER
B
TE
RTERM = VAB
IA
+
–
TE
VAB
1/2 VCC
0V
IA
+
–
VCC
tRTEN
90%
tRTZ
10%
VB
2859/61 F07
Figure 7. Termination Resistance and Timing Measurements
285961fc
6
LTC2859/LTC2861
Typical Performance Characteristics
Receiver Skew
vs Temperature
Driver Propagation Delay
vs Temperature
Driver Skew vs Temperature
3
18
RDIFF = 54Ω
CL = 100pF
SLO = VCC
16
DRIVER PROP DELAY (ns)
VAB = 1.5V
CL = 15pF
2
TA = 25°C, VCC = 5V, unless otherwise noted.
DRIVER SKEW (ns)
RECEIVER SKEW (ns)
2
1
1
0
0
14
12
10
8
6
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
–1
–40 –20
100 120
0
285961 G01
20 40 60 80
TEMPERATURE (°C)
4
–40 –20
100 120
115
110
105
80
100 120
285961 G03
R=∞
4
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
120
60
5
4
125
40
Driver Differential Output Voltage
vs Temperature
VOH
130
20
TEMPERATURE (°C)
5
135
0
285961 G02
Driver Output Low/High Voltage
vs Output Current
RTERM vs Temperature
RESISTANCE (Ω)
RDIFF = 54Ω
CL = 100pF
SLO = VCC
3
2
VOL
1
3
R = 100Ω
2
R = 54Ω
1
100
95
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
0
100 120
40
20
50
30
OUTPUT CURRENT (mA)
60
70
SOURCE
65
4
285961 G05
2
VAB = 1.5V
CL = 15pF
50
55
50
45
40
1
1
3
4
2
OUTPUT CURRENT (mA)
5
285961 G07
30
–40 –20
100 120
285961 G06
R = 54Ω
40
R = 100Ω
30
20
10
35
SINK
20 40
60 80
TEMPERATURE (°C)
Supply Current vs Data Rate
SUPPLY CURRENT (mA)
PROP DELAY (ns)
3
0
60
60
0
0
–40 –20
70
Receiver Propagation Delay
vs Temperature
5
OUTPUT VOLTAGE (V)
10
285961 G04
Receiver Output Voltage vs
Output Current (Source and Sink)
0
0
R=∞
0
20 40 60 80
TEMPERATURE (°C)
100 120
285961 G08
0
0.1
10
1
DATA RATE (Mbps)
100
285961 G09
285961fc
7
LTC2859/LTC2861
Pin Functions
(DD/DE/GN)
RO (Pin 1): Receiver Output. If the receiver output is enabled
(RE low) and A > B by 200mV, then RO will be high. If A
< B by 200mV, then RO will be low. If the receiver inputs
are open, shorted, or terminated without a valid signal, RO
will be high.
RE (Pin 2): Receiver Enable. A low enables the receiver.
A high input forces the receiver output into a high impedance state.
DE (Pin 3): Driver Enable. A high on DE enables the driver.
A low input will force the driver outputs into a high impedance. If RE is high with DE and TE LOW, the part will enter
a low power shutdown state.
DI (Pin 4): Driver Input. If the driver outputs are enabled
(DE HIGH), then a low on DI forces the driver positive
output LOW and negative output HIGH. A high on DI,
with the driver outputs enabled, forces the driver positive
output HIGH and negative output LOW.
TE (Pin 5): Internal Termination Resistance Enable. A high
input will connect a termination resistor (120Ω typical)
between pins A and B.
GND (Pins 6,11/6,13/6): Ground. Pins 11 and 13 are
backside thermal pad, connected to Ground.
SLO (Pins 7/7/11): Driver Slew Rate Control. A low input
will force the driver into a reduced slew rate mode.
Y (Pins -/8/12): Positive Driver Output for LTC2861.
Z (Pins -/9/13): Negative Driver Output for LTC2861.
B (Pins 9/10/14): Negative Receiver Input (and Negative
Driver Output for LTC2859).
A (Pins 8/11/15): Positive Receiver Input (and Positive
Driver Output for LTC2859).
VCC (Pins 10/12/16): Positive Supply. 4.5V < VCC < 5.5V.
Bypass with 0.1µF ceramic capacitor.
285961fc
8
LTC2859/LTC2861
Function Tables
LTC2859
LOGIC INPUTS
DE
RE
TE
MODE
A, B
RO
TERMINATOR
0
0
0
Receive
RIN
Enabled
Off
0
0
1
Receive with Term
RIN
Enabled
On
0
1
0
Shutdown
RIN
Hi-Z
Off
0
1
1
Term Only
RIN
Hi-Z
On
1
0
0
Transmit with Receive
Driven
Enabled
Off
1
0
1
Transmit with Receive
and Term
Driven
Enabled
On
1
1
0
Transmit
Driven
Hi-Z
Off
1
1
1
Transmit with Term
Driven
Hi-Z
On
LTC2861
LOGIC INPUTS
DE
RE
TE
MODE
A, B
Y, Z
RO
TERMINATOR
0
0
0
Receive
RIN
Hi-Z
Enabled
Off
0
0
1
Receive with Term
RIN
Hi-Z
Enabled
On
0
1
0
Shutdown
RIN
Hi-Z
Hi-Z
Off
0
1
1
Term Only
RIN
Hi-Z
Hi-Z
On
1
0
0
Transmit with Receive
RIN
Driven
Enabled
Off
1
0
1
Transmit with Receive
and Term
RIN
Driven
Enabled
On
1
1
0
Transmit
RIN
Driven
Hi-Z
Off
1
1
1
Transmit with Term
RIN
Driven
Hi-Z
On
Block Diagrams
LTC2859
RE
DE
SLEEP/SHUTDOWN
LOGIC AND DELAY
LTC2861
A
(15kV)
120Ω
RE
DE
SLEEP/SHUTDOWN
LOGIC AND DELAY
A
(15kV)
120Ω
TE
RO
TE
RO
RECEIVER
RECEIVER
B
(15kV)
SLO
DI
B
(15kV)
SLO
DRIVER
DI
Z
(15kV)
DRIVER
Y
(15kV)
2859/61 BD
285961fc
9
LTC2859/LTC2861
Applications Information
Driver
The driver provides full RS485 and RS422 compatibility.
When enabled, if DI is high, Y-Z is positive for the full
duplex device (LTC2861) and A-B is positive for the halfduplex device (LTC2859).
When the driver is disabled, both outputs are highimpedance. For the full duplex LTC2861, the leakage on
the driver output pins is guaranteed to be less than 10µA
over the entire common mode range of –7V to +12V. On
the half-duplex LTC2859, the impedance is dominated by
the receiver input resistance, RIN.
Driver Overvoltage and Overcurrent Protection
The driver outputs are protected from short circuits to
any voltage within the Absolute Maximum range of (VCC
–15V) to +15V. The maximum current in this condition
is 250mA. If the pin voltage exceeds about ±10V, current
limit folds back to about half of the peak value to reduce
overall power dissipation and avoid damaging the part.
The LTC2859/LTC2861 also feature thermal shutdown
protection that disables the driver, terminator, and receiver
in case of excessive power dissipation.
SLO Mode: Slew Limiting for EMI Emissions Control
The LTC2859/LTC2861 feature a logic-selectable reducedslew mode (SLO mode) that softens the driver output
edges to control the high frequency EMI emissions from
equipment and data cables. The reduced slew rate mode
is entered by taking the SLO pin low, where the data rate is
limited to about 250kbps. Slew limiting also mitigates the
adverse effects of imperfect transmission line termination
caused by stubs or mismatched cables.
Figures 8a and 8b show the LTC2861 driver outputs in
normal and SLO mode with their corresponding frequency
spectrums operating at 250kbps. SLO mode significantly
reduces the high frequency harmonics.
Y, Z
Y–Z
Y–Z
1V/DIV
2µs/DIV
10dB/DIV
Driver Output at 125kHz into 100Ω Resistor
1.25MHz/DIV
285961 F08a
Frequency Spectrum of the Same Signal
Figure 8a. Driver Output in Normal Mode
Y, Z
Y–Z
Y–Z
1V/DIV
2µs/DIV
10dB/DIV
Driver Output at 125kHz into 100Ω Resistor
1.25MHz/DIV
285961 F08b
Frequency Spectrum of the Same Signal
Figure 8b. Driver Output in SLO Mode
285961fc
10
LTC2859/LTC2861
Applications Information
Receiver and Failsafe
With the receiver enabled, when the absolute value of the
differential voltage between the A and B pins is greater than
200mV, the state of RO will reflect the polarity of (A-B).
The LTC2859/LTC2861 have a failsafe feature that guarantees the receiver output to be in a logic HIGH state when
the inputs are either shorted, left open, or terminated
(externally or internally), but not driven for more than
about 3µs. The delay prevents signal zero crossings from
being interpreted as shorted inputs and causing RO to go
high inadvertently. This failsafe feature is guaranteed to
work for inputs spanning the entire common mode range
of –7V to +12V.
The receiver output is internally driven high (to VCC) or
low (to ground) with no external pull-up needed. When the
receiver is disabled the RO pin becomes Hi-Z with leakage
of less than ±1µA for voltages within the supply range.
Receiver Input Resistance
The receiver input resistance from A or B to ground is
greater than 96k permitting up to a total of 256 receivers
per system without exceeding the RS485 receiver load-
ing specification. High temperature H-Grade operation
reduces the minimum input resistance to 48k permitting
128 receivers on the bus. The input resistance of the
receiver is unaffected by enabling/disabling the receiver
or by powering/unpowering the part. The equivalent input
resistance looking into A and B is shown in Figure 9.
Switchable Termination
Proper cable termination is very important for good signal
fidelity. If the cable is not terminated with its characteristic
impedance, reflections will result in distorted waveforms.
The LTC2859/LTC2861 are the first RS485 transceivers
to offer integrated switchable termination resistors on the
receiver input pins. This provides the tremendous advantage of being able to easily change, through logic control,
the proper line termination for optimal performance when
configuring transceiver networks.
When the TE pin is high, the termination resistor is enabled and the differential resistance from A to B is 120Ω.
Figure 10 shows the I/V characteristics between pins A
and B with the termination resistor enabled and disabled.
The resistance is maintained over the entire RS485 common mode range of –7V to +12V as shown in Figure 11.
A
>96k
60Ω
TE
60Ω
>96k
2859/61 F09
B
Figure 9. Equivalent Input Resistance into A and B
(on the LTC2859, Valid if Driver is Disabled)
Figure 10. Curve Trace Between A and B
with Termination Enabled and Disabled
285961fc
11
LTC2859/LTC2861
applications information
150
140
RESISTANCE (Ω)
The integrated termination resistor has a high frequency
response which does not limit performance at the maximum specified data rate. Figure 12 shows the magnitude
and phase of the termination impedance vs frequency. The
termination resistor cannot be enabled by TE if the device
is unpowered or in thermal shutdown mode.
Supply Current
120
110
–10
The logic inputs of the LTC2859/LTC2861 have 50mV of
hysteresis to provide noise immunity. Fast edges on the
outputs can cause glitches in the ground and power supplies
which are exacerbated by capacitive loading. If a logic input
is held near its threshold (typically 1.5V), a noise glitch
30
185
15
MAGNITUDE (Ω)
170
PHASE
155
0
–15
140
MAGNITUDE
125
–30
110
–45
95
–60
80
10–1
–75
101
100
FREQUENCY (MHz)
285455 F12
Figure 12. Termination Magnitude
and Phase vs Frequency
75
RDIFF = 54Ω
70
CURRENT (mA)
Care should be taken to route outputs away from any sensitive inputs to reduce feedback effects that might cause
noise, jitter, or even oscillations. For example, in the full
duplex LTC2861, DI and A/B should not be routed near
the driver or receiver outputs.
15
285961 F11
Figure 11. Termination Resistance
vs Common Mode Voltage
High Speed Considerations
A ground plane layout is recommended for the LTC2859/
LTC2861. A 0.1µF bypass capacitor less than one quarter
inch away from the VCC pin is also recommended. The PC
board traces connected to signals A/B and Z/Y (LTC2861)
should be symmetrical and as short as possible to maintain
good differential signal integrity. To minimize capacitive
effects, the differential signals should be separated by
more than the width of a trace and should not be routed
on top of each other if they are on different signal planes.
–5
5
10
0
COMMON MODE VOLTAGE (V)
PHASE (°)
The unloaded static supply currents in the LTC2859/
LTC2861 are very low —typically under 700µA for all modes
of operation without the internal terminator enabled. In
applications with resistively terminated cables, the supply
current is dominated by the driver load. For example, when
using two 120Ω terminators with a differential driver output
voltage of 2V, the DC current is 33mA, which is sourced
by the positive voltage supply. This is true whether the
terminators are external or internal such as in the LTC2859/
LTC2861. Power supply current increases with toggling
data due to capacitive loading and this term can increase
significantly at high data rates. Figure 13 shows supply
current vs data rate for two different capacitive loads (for
the circuit configuration of Figure 3).
130
65
60
CL = 1000pF
55
50
45
102
CL = 100pF
103
104
DATA RATE (kbps)
105
285961 F13
Figure 13. Supply Current vs Data Rate
285961fc
12
LTC2859/LTC2861
Applications Information
Cable Length vs Data Rate
For a given data rate, the maximum transmission distance
is bounded by the cable properties. A typical curve of cable
length vs data rate compliant with the RS485 standard is
shown in Figure 14. Three regions of this curve reflect
different performance limiting factors in data transmission. In the flat region of the curve, maximum distance is
determined by resistive losses in the cable. The downward
sloping region represents limits in distance and data
rate due to AC losses in the cable. The solid vertical line
represents the specified maximum data rate in the RS485
standard. The dashed lines at 250kbps and 20Mbps show
the maximum data rates of the LTC2859/LTC2861 in LowEMI and normal modes, respectively.
10k
CABLE LENGTH (FT)
from a driver transition may exceed the hysteresis levels
on the logic and data inputs pins causing an unintended
state change. This can be avoided by maintaining normal
logic levels on the pins and by slewing inputs through
their thresholds by faster than 1V/µs when transitioning.
Good supply decoupling and proper line termination also
reduces glitches caused by driver transitions.
LOW-EMI MODE
MAX DATA RATE
1k
NORMAL
MODE MAX
DATA RATE
100
RS485 MAX
DATA RATE
10
10k
100k
1M
10M
DATA RATE (bps)
100M
285961 F14
Figure 14. Cable Length vs Data Rate
(RS485 Standard Shown in Solid Lines)
Typical Applications
Multi-Node Network with End Termination Using LTC2859
TE = 0V
TE = 0V
D
R
LTC2859
LTC2859
R
D
R
LTC2859
LTC2859
R
TE = 5V
TE = 5V
D
D
2859/61 TA04
285961fc
13
LTC2859/LTC2861
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.125
TYP
6
3.00 ±0.10
(4 SIDES)
0.40 ±0.10
10
1.65 ±0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.75 ±0.05
0.00 – 0.05
5
1
(DD) DFN REV C 0310
0.25 ±0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
285961fc
14
LTC2859/LTC2861
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
0.70 ±0.05
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
1.70 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
7
R = 0.115
TYP
0.40 ±0.10
12
R = 0.05
TYP
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ±0.10
0.75 ±0.05
6
0.25 ±0.05
1
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
(UE12/DE12) DFN 0806 REV D
0.50 BSC
2.50 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
285961fc
15
LTC2859/LTC2861
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
× 45°
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
285961fc
16
LTC2859/LTC2861
Revision History
(Revision history begins at Rev C)
REV
DATE
DESCRIPTION
C
3/12
Added H-grade Order Information and Electrical Characteristics parameters
PAGE NUMBER
2, 3, 4
Revised Receiver Input Resistance section
11
Replaced Figure 12
12
Added Termination Resistor restriction information
12
285961fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC2859/LTC2861
Typical Application
Failsafe “0” Application (Idle State = Logic “0”)
VCC
100kΩ
RO
LTC2859
R
I1
B
120Ω
DI
I2
A
D
"A"
"B"
2859/61 TA03
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285961fc
18
Linear Technology Corporation
LT 0312 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2006